Texas Instruments AN-1574 LM5073, LM5073 User Manual
1 Introduction
The LM5073 evaluation board is designed as a low cost solution for both IEEE802.3af fully compliant and
non-compliant Power over Ethernet (PoE) PD applications. The board also supports PD operation with
auxiliary power sources like AC wall adaptors, solar cells, and so on. The maximum intake power of the
PD interface can be programmed up to 25W. In order to facilitate an overall PD evaluation, the board also
includes integrated Ethernet RX and TX magnetics, an RJ45 interface to user’s PHY circuit, and an
LM5576 buck regulator. The board can be conveniently reconfigured with built-in jumpers to realize an
optimal solution for a particular application.
For detailed information on the LM5073 and LM5576, refer to the device data sheets.
2 Features of the Evaluation Board
• IEEE 802.3af fully compliant
• Programmable maximum input dc current through PD interface: 800mA
• Input voltage ranges:
– PoE input voltage range at startup: 40 to 57V
– PoE input voltage range with normal operation: 33 to 57V
– Front Aux voltage range: 20 to 57V
– Rear Aux input voltage range: 10 to 57V
• Flexible selection of external DC-DC converter for optimal solution
• On board DC-DC converter:
– Output voltage: 3.3V
– Maximum output current: 3.0A
– Switching frequency: 150kHz
• Easily reconfigurable for different applications
• Complete PD interface including Ethernet magnetics and RJ45 connector interface to PHY
• Two layer PCB with single side component placement
User's Guide
SNVA214A–April 2007–Revised April 2013
AN-1574 LM5073 Evaluation Board
3 Precautions
Before powering up the evaluation board, please carefully read this article. As seen below, the evaluation
board is easily reconfigurable to realize optimal solutions for various applications, while the factory original
configuration of the board is Configuration 1.
4 An Important Note About the Maximum Power Capability and Cable Usage
The LM5073 PD interface supports a maximum intake power of 25W. The user must make sure that the
Power Sourcing Equipment (PSE) in use can provide at least 30W.
Important: Please note that the CAT-5 cable may not support the maximum power over two pairs of
twisted wires under strict safety considerations. Users shall select the proper cable wires to support the
design power level without compromising the applicable safety standards. Using an improper cable at
such power levels may violate various safety regulations and may cause damage.
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A Note About PoE Input Potentials
5 A Note About PoE Input Potentials
PoE applications are typically -48V systems, in which the notations GND and -48V normally refer to the
high and low input potentials, respectively. However, for easy readability, the LM5072 datasheet was
written in the positive voltage convention with positive input potentials referenced to the VEE pin of the
LM5073. Therefore, when testing the evaluation board with a bench power supply, the negative terminal of
the power supply is equivalent to the PoE system’s -48V potential, and the positive terminal is equivalent
to the PoE system ground. To prevent confusion between the datasheet and this application note, the
same positive voltage convention is used.
6 Connection and Custom Configurations
This section contains information about the setup and configuration of the LM5073 evaluation board.
Figure 1 shows the evaluation board PCB layout.
The following are the connections:
• J1, RJ45 connector for PoE input and data link.
• J2, PJ102A power jack for the front Aux (FAUX) power input. The center pin of J2 is the high potential
pin.
• J3, PJ102A power jack for the rear Aux (RAUX) power input. The center pin of J3 is the high potential
pin.
• J4, RJ45 connector interface for data link to PHY circuit.
• J5 and J6, 3.3V output port of the onboard buck regulator. J5 is the high potential pin.
• P1 and P2, a pair of pins for quick PoE input connection from a bench power supply to the center taps
of the Ethernet RX and TX magnetics. Pin polarity reversible.
• P3 and P4, a pair of pins for quick PoE input connection from a bench power supply to the nodes of
the spare pairs. Pin polarity reversible.
• P5 and P6, a pair of pins for quick FAUX power input connection to a bench power supply. P5 is the
high potential pin.
• P7 and P8, a pair of pins for quick RAUX power input connection to a bench power supply. P7 is the
high potential pin.
• P9 and P10, PD interface power output port to an external DC-DC converter. P9 is the high potential
pin.
• P11, active high shutdown signal pin to control an external DC-DC converter.
• P12, active low shutdown signal pin to control an external DC-DC converter.
• P13, bias voltage (Vcc) to or from an external DC-DC converter, limited from 9V to 14V.
• P14, chassis ground pin.
• P15, 3.3V from external DC-DC converter to bias the secondary windings’ center taps of the Ethernet
RX and TX transformers.
The evaluation board is designed with multi function features. Jumpers are used for easy reconfiguration
of the evaluation board to meet various application requirements. The jumpers are listed in Table 1.
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Connection and Custom Configurations
Figure 1. The Evaluation Board Layout
Table 1. Jumpers
Jumper Function
JMP1
JMP2
JMP3 Short pins 2 and 3 to select low loss RAUX input inrush limit by MOSFET.
JMP4, JMP5 Short pins 2 and 3 to bypass common mode input filter.
JMP6 Short pins 2 and 3 to bypass the differential input filter.
JMP7
JMP8 Short pins 2 and 3 to select external pull up for the nSD pin by Vcc.
JMP9, JMP11, JMP12, Short to connect the PD interface with the onboard buck regulator.
JMP13 Open when an external DC-DC converter is used.
Short for Aux dominant.
Open for non-Aux dominant.
Short pins 1 and 2 to produce startup bias voltage directly from RAUX
input.
Short pins 2 and 3 to produce startup bias voltage through linear regulator.
Open all pins when above two functions are not required.
Short pins 1 and 2 to select the simple RAUX inrush limit by resistor.
Either of the two settings must be selected.
Short pins 1 and 2 to use common mode input filter.
Either of the two settings must be selected.
Short pins 1 and 2 to use the differential input filter.
Either of the two settings must be selected.
Short to activate the PoE power indicator LED.
Open to not select the PoE power indicator LED.
Short pins 1 and 2 to select external pull up for the SD pin by Vcc.
Open all pins when no external pull up is required.
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Applicable External DC-DC Converters
7 Applicable External DC-DC Converters
The external DC-DC converter can be chosen from, but not limited to, the following standard evaluation
boards for quick evaluation tests. The required voltage rating of applicable DC-DC converter is 75V min.
• LM5005 Evaluation Board, a 2.5A buck regulator for low cost non-isolated PD application (Note: the
LM5005 is a drop-in replacement for the LM5576 on the LM5073 evaluation board).
• LM5020 Evaluation Board, a current mode flyback converter.
• LM5025 Evaluation Board, a voltage mode active clamp forward converter.
• LM5026 Evaluation Board, a current mode active clamp forward converter.
• LM5032 Evaluation Board, a current mode dual interleaved converter.
• LM5034 Evaluation Board, a current mode dual interleaved converter with active clamp.
• LM5115 Evaluation Board, a 5A buck regulator with synchronous rectification.
Note that per IEEE 802.3af the DC-DC converter input capacitor should be at least 5 µF. Considering the
typical capacitor’s tolerance and variations over temperature, a minimum 10 µF nominal is required. This
10 µF minimum value can be combinations of ceramic and electrolytic capacitors for cost considerations.
When the external DC-DC converter’s input capacitance is not enough, C8 of the evaluation board can be
used. Using C8 but excluding L1, JMP6’s three pins should be all shorted together.
8 A Note About the Onboard Buck Regulator
The onboard LM5576 buck regulator is a low cost solution that is ideal for continuous power levels not
greater than 6W. Although the maximum output current is 3.0A maximum power is limited because the
regulator employs a diode in the freewheeling branch, which sacrifices the efficiency under normal 48V
PoE operation. In order to obtain higher efficiency, a synchronous rectification buck regulator like the
LM5115 evaluation board is recommended.
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9 Configuration 1: IEEE 802.3af Fully Compliant PD Interface
Figure 2 shows the evaluation board configuration simplified for an IEEE 802.3af fully compliant PD
interface implementation. The following table shows the jumper positions for this configuration.
Table 2. Jumper Positions of Configuration 1
Jumper Function
JMP4, JMP5 Pins 2 and 3 short, Pin 1 open.
JMP6 Pins 2 and 3 short, Pin 1 open.
JMP7 Pins open.
JMP8 All three pins open.
JMP9, JMP11, JMP12, JMP13
Other Jumpers Not relevant.
Jumper pins short when the on-board buck regulator is used.
Jumper pins open when an external dc-dc converter is used.
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Configuration 2: 802.3af Fully Compliant PD Interface with Front Aux Power Support
Note:
1.The sum of C1 and C2 comprises the valid signature capacitance. In practice, this configuration can delete C2 and
change C1 to 0.1µF.
2. R6 may need to be installed for classification other than the default Class 0. Refer to LM5073 datasheet for R6
selection.
3. The installed R7 (15.8k) is intended for high power PD applications, which sets the dc current limit to 800 mA. For
fully compliant applications, R7 may need to be removed or replaced in order to limit the dc current per IEEE 802.3af.
Refer to LM5073 datasheet for R7 selection.
Figure 2. IEEE 802.3af Fully Compliant PD Interface
10 Configuration 2: 802.3af Fully Compliant PD Interface with Front Aux Power Support
Figure 3 shows the evaluation board configuration for an IEEE 802.3af fully compliant PD interface with
front Aux power support. In order to obtain IEEE 802.3af specified maximum power, the Aux source
voltage should be greater than 20V. Otherwise the obtainable power from the Aux source will be limited by
the LM5073’s maximum current limit of 800 mA. For higher power PD applications, the Aux source voltage
applicable to the FAUX input depends on the power level, conversion efficiency, and the 800mA limit.
Note that R11 (24.9k) is used to overcome any leakage current of D1 and avoid faulty FAUX pin potential
during PoE operation when the FAUX source is absent.
The following table shows the jumper positions for this configuration.
Table 3. Jumper Positions of Configuration 2
Jumper Function
JMP4, JMP5 Pins 2 and 3 short, Pin 1 open.
JMP6 Pins 2 and 3 short, Pin 1 open.
JMP7 Pins open.
JMP8 All three pins open.
JMP9, JMP11, JMP12, JMP13
Other Jumpers Not relevant.
Jumper pins short when the on-board buck regulator is used.
Jumper pins open when an external dc-dc converter is used.
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Configuration 3: 802.3af Fully Compliant PD Interface with Rear Aux Power Support
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Note:
1.The sum of C1 and C2 comprises the valid signature capacitance. In practice, this configuration can delete C2 and
change C1 to 0.1µF.
2. R6 may need to be installed for classification other than the default Class 0. Refer to LM5073 datasheet for R6
selection.
3. The installed R7 (15.8k) is intended for high power PD applications, which sets the dc current limit to 800 mA. For
fully compliant applications, R7 may need to be removed or replaced in order to limit the dc current per IEEE 802.3af.
Refer to LM5073 datasheet for R7 selection.
Figure 3. IEEE 802.3af Fully Compliant PD Interface with Front Aux Power Support
11 Configuration 3: 802.3af Fully Compliant PD Interface with Rear Aux Power Support
shows the evaluation board configuration for an IEEE 802.3af fully compliant PD interface with rear Aux
power support. This configuration is recommended for low voltage Aux power sources such as 12V or 24
ac adapters. The minimum RAUX input voltage can be as low as 10V. Note that R12 (24.9k) is used to
overcome any leakage current of D2 in order to avoid faulty RAUX pin potential during PoE operation.
Also note that R1 and R2 are used to provide simple RAUX input filtering as well as inrush limit.
The following table shows the jumper positions for this configuration.
Table 4. Jumper Positions of Configuration 3
Jumper Function
JMP1 Jumper pins short for Aux dominant.
Jumper pins open for non-Aux dominant feature.
JMP2 All three pins open.
JMP3 Pins 2 and 3 short, Pin 1 open.
JMP4, JMP5 Pins 2 and 3 short, Pin 1 open.
JMP6 Pins 2 and 3 short, Pin 1 open.
JMP7 Pins open.
JMP8 All three pins open.
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