Texas Instruments LM5020 User Manual

OUT

CS

SS

FB

COMP

/

UVLO

VIN

VCC

COMPENSATION

GND

V

OUT

LM5020

V

IN

RT SYNC

LM5020

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SNVS275F –MAY 2004–REVISED APRIL 2006

LM5020 100V Current Mode PWM Controller

Check for Samples: LM5020

1

FEATURES

2

• Internal Start-up Bias Regulator

• Error Amplifier • WSON-10 (4 mm x 4 mm)

• Precision Voltage Reference

• Programmable Softstart

• 1A Peak Gate Driver

• Maximum Duty Cycle Limiting (80% for
LM5020-1 or 50% for LM5020-2)

• Programmable Line Under Voltage Lockout
(UVLO) with Adjustable Hysteresis

• Cycle-by-Cycle Over-Current Protection

• Slope Compensation (LM5020-1)

• Programmable Oscillator Frequency with
Synchronization Capability

• Current Sense Leading Edge Blanking

• Thermal Shutdown Protection

APPLICATIONS

• Telecommunication Power Converters

• Industrial Power Converters

• +42V Automotive Systems

PACKAGES

• VSSOP-10

DESCRIPTION

The LM5020 high voltage pulse-width-modulation
(PWM) controller contains all of the features needed
to implement single ended primary power converter
topologies. Output voltage regulation is based on
current-mode control, which eases the design of loop
compensation while providing inherent line feed­forward. The LM5020 includes a high-voltage start-up
regulator that operates over a wide input range up to
100V. The PWM controller is designed for high speed
capability including an oscillator frequency range to
1MHz and total propagation delays less than 100ns.
Additional features include an error amplifier,
precision reference, line under-voltage lockout, cycle­by-cycle current limit, slope compensation, softstart,
oscillator synchronization capability and thermal
shutdown. The controller is available in both VSSOP­10 and WSON-10 packages.

Typical Application Circuit

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Figure 1. Non-Isolated Flyback Converter

Copyright © 2004–2006, Texas Instruments Incorporated

1
2
3
4
5

6

7

8

9

10

FB

VCC

OUT

VIN

COMP

UVLO
GND

CS

RT/SYNC

SS

LM5020

SNVS275F –MAY 2004–REVISED APRIL 2006

Connection Diagram

Top View

Figure 2. 10-Lead VSSOP, WSON

PIN DESCRIPTIONS

Pin Name Description Application Information

1 VIN Source Input Voltage Input to the start-up regulator. Input range is 13V to 100V.
2 FB Feedback Signal Inverting input of the internal error amplifier. The non-

inverting input is internally connected to a 1.25V reference.

3 COMP The output of the error amplifier and input to the COMP pull-up is provided by an internal 5K resistor which

Pulse Width Modulator may be used to bias an opto-coupler transistor.

4 VCC Output of the internal high voltage series pass If an auxiliary winding raises the voltage on this pin above

regulator. Regulated output voltage is 7.7V the regulation set point, the internal series pass regulator

will shut down, reducing the internal power dissipation.
5 OUT Output of the PWM controller Gate driver output with a 1A peak current capability.
6 GND Ground return
7 UVLO Line Under-Voltage Shutdown An external resistor divider from the power converter

source voltage sets the shutdown levels. The threshold at

this pin is 1.25V. Hysteresis is set by a switched internal

20µA current source.
8 CS Current Sense input Current sense input for current mode control and over-

current protection. Current limiting is accomplished using a

dedicated current sense comparator. If the CS pin voltage

exceeds 0.5V the OUT pin switches low for cycle-by-cycle

current limiting. CS is held low for 50ns after OUT switches

high to blank leading edge current spikes.
9 RT / SYNC Oscillator timing resistor pin and synchronization An external resistor connected from RT to GND sets the

input oscillator frequency. This pin also accepts synchronization

pulses from an external clock.

10 SS Softstart Input An external capacitor and an internal 10µA current source

set the soft-start ramp rate.

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

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Absolute Maximum Ratings

(1)(2)

SNVS275F –MAY 2004–REVISED APRIL 2006

VIN to GND -0.3V to 100V
VCC to GND -0.3V to 16V
RT to GND -0.3V to 5.5V
All other pins to GND -0.3V to 7V
Power Dissipation Internally Limited
ESD Rating

(3)

Human Body Model 2kV
Storage Temperature -65°C to +150°C
Junction Temperature 150°C

(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which

operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(3) The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor.

Operating Ratings

VIN Voltage 13V to 90V
External Voltage applied to VCC 8V to 15V
Operating Junction Temperature -40°C to +125°C

Electrical Characteristics

Specifications in standard type face are for TJ= +25°C and those in boldface type apply over the full operating junction
temperature range. Unless otherwise specified: VIN = 48V, VCC = 10V, and RT = 31.6kΩ.

Symbol Parameter Conditions Min Typ Max Units

Startup Regulator

VCCReg VCCRegulation VCC= Open 7.4 7.7 8.0 V

VCCCurrent Limit See
I-V
I

IN

IN

Startup Regulator Leakage VIN= 100V 150 500 µA

Shutdown Current V

VCC Supply

VCCUVLO (Rising) VccReg VccReg - V

VCCUVLO (Falling) 5.3 6.0 6.7 V
I

CC

Supply Current Cload = 0 2 3 mA

Error Amplifier

GBW Gain Bandwidth 4 MHz

DC Gain 75 dB

Reference Voltage FB = COMP 1.225 1.25 1.275 V

COMP Sink Capability FB = 1.5V COMP= 1V 5 17 mA

UVLO Pin

Shutdown Threshold 1.225 1.25 1.275 V

Undervoltage Shutdown Hysteresis 16 20 24 µA

Current Source

Current Limit

ILIM Delay to Output CS step from 0 to 0.6V 30 ns

Cycle by Cycle CS Threshold 0.45 0.5 0.55 V

Voltage

Leading Edge Blanking Time 50 ns

(2)

= 0V, VCC= open 250 350 µA

UVLO

15 22 mA

- 300mV 100mV

Time to onset of OUT
Transition (90%)

(1)

(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using

Statistical Quality Control (SQC) methods. The limits are used to calculate National's Average Outgoing Quality Level (AOQL).

(2) Device thermal limitations may limit usable range.

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Electrical Characteristics (continued)

Specifications in standard type face are for TJ= +25°C and those in boldface type apply over the full operating junction
temperature range. Unless otherwise specified: VIN = 48V, VCC = 10V, and RT = 31.6kΩ.

Symbol Parameter Conditions Min Typ Max Units

CS Sink Impedance (clocked) 35 55 Ω
Soft Start

Softstart Current Source 7 10 13 µA

Softstart to COMP Offset 0.35 0.55 0.75 V

Oscillator

Frequency1 (RT = 31.6k) See

Frequency2 (RT = 9.76k) See

Sync threshold 2.4 3.2 3.8 V

PWM Comparator

Delay to Output COMP set to 2V, 25 ns

Min Duty Cycle COMP=0V 0 %

Max Duty Cycle (-1 Device) 75 80 85 %

Max Duty Cycle (-2 Device) 50 %

COMP to PWM Comparator Gain 0.33

COMP Open Circuit Voltage 4.3 5.2 6.1 V

COMP Short Circuit Current COMP=0V 0.6 1.1 1.5 mA

Slope Compensation

Slope Comp Amplitude Delta increase at PWM 80 105 130 mV

(LM5020-1 Device Only) Comparator to CS

Output Section

Output High Saturation Iout = 50mA, VCC- V

Output Low Saturation I

Rise Time Cload = 1nF 18 ns

Fall Time Cload = 1nF 15 ns

Thermal Shutdown

Tsd Thermal Shutdown Temp. 165 °C

Thermal Shutdown Hysteresis 25 °C

(3)
(3)

CS stepped 0 to 0.4V,
Time to onset of OUT
transition low

= 100mA, V

OUT

OUT

175 200 225 kHz
560 630 700 kHz

OUT

(1)

0.25 0.75 V

0.25 0.75 V

(3) Specification applies to the oscillator frequency. The operational frequency of the LM5020-2 devices is divided by two.

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10k

-225

-180

-135

-90

-45

0

45

90

135

180

225

GAIN (dB)

FREQUENCY (Hz)

PHASE

(

o

)

-50

-40

-30

-20

-10

0

10

20

30

40

50

100k 1M 10M

CURRENT (PA)

7.0

8.2

9.4

10.6

11.8

13.0

TEMPERATURE (oC)

-40

10

60

110

TEMPERATURE (oC)

FREQUENCY (kHz)

190

195

200

205

210

-40

10

60

110

RT (k:)

FREQUENCY (Hz)

1 10 100

1.00E+04

1.00E+05

1.00E+06

0 5 10 15 20 25

1

2

3

4

5

6

7

8

9

V

CC

(V)

ICC (mA)

0

10

20

V

IN

(V)

0

2

4

6

8

10

12

14

16

18

20

V

CC

(V)

LM5020

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SNVS275F –MAY 2004–REVISED APRIL 2006

Typical Performance Characteristics

Unless otherwise specified: TJ= 25°C.

VCCand V

IN

vs vs

V

IN

Figure 3. Figure 4.

Oscillator Frequency vs

vs Temperature

RT RT = 31.6kΩ

Oscillator Frequency

V

ICC(VIN= 48V)

CC

Figure 5. Figure 6.

Soft Start Current

vs

Temperature Error Amp. Gain/Phase Plot

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Figure 7. Figure 8.

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LOGIC

OSC

VIN

VCC

LOGIC

OUT

7.7V SERIES
REGULATOR

REFERENCE

SLOPECOMP

RAMP

GENERATOR

(LM5020-1 Only)

DRIVER

RT/SYNC

CLK

V

CC

ENABLE

5V

1.25V

S

Q

R

Q

UVLO

HYSTERESIS

(20 PA)

UVLO

+

-

1.25V

GND

Max Duty Limit
LM5020-1 (80%)
LM5020-2 (50%)

10 PA

SS

CS

0.5V

PWM

50 PA

0

2k

FB

5k

5V

1.4V

2R

R

COMP

1.25V

SS

+

-

+

-

CLK + LEB

SS

LM5020

SNVS275F –MAY 2004–REVISED APRIL 2006

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Block Diagram

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