TEXAS INSTRUMENTS LM3S6965 Technical data
PRELIMINARY
LM3S6965 Microcontroller
DATA SHEET
Copyright © 2007 Luminary Micro, Inc.DS-LM3S6965-1972
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LM3S6965 Microcontroller
Table of Contents
About This Document .................................................................................................................... 20
Audience .............................................................................................................................................. 20
About This Manual ................................................................................................................................ 20
Related Documents ............................................................................................................................... 20
Documentation Conventions .................................................................................................................. 20
1 Architectural Overview ...................................................................................................... 22
1.1 Product Features ...................................................................................................................... 22
1.2 Target Applications .................................................................................................................... 28
1.3 High-Level Block Diagram ......................................................................................................... 29
1.4 Functional Overview .................................................................................................................. 30
1.4.1 ARM Cortex™-M3 ..................................................................................................................... 30
1.4.2 Motor Control Peripherals .......................................................................................................... 30
1.4.3 Analog Peripherals .................................................................................................................... 31
1.4.4 Serial Communications Peripherals ............................................................................................ 32
1.4.5 System Peripherals ................................................................................................................... 33
1.4.6 Memory Peripherals .................................................................................................................. 34
1.4.7 Additional Features ................................................................................................................... 35
1.4.8 Hardware Details ...................................................................................................................... 35
2 ARM Cortex-M3 Processor Core ...................................................................................... 37
2.1 Block Diagram .......................................................................................................................... 38
2.2 Functional Description ............................................................................................................... 38
2.2.1 Serial Wire and JTAG Debug ..................................................................................................... 38
2.2.2 Embedded Trace Macrocell (ETM) ............................................................................................. 39
2.2.3 Trace Port Interface Unit (TPIU) ................................................................................................. 39
2.2.4 ROM Table ............................................................................................................................... 39
2.2.5 Memory Protection Unit (MPU) ................................................................................................... 39
2.2.6 Nested Vectored Interrupt Controller (NVIC) ................................................................................ 39
3 Memory Map ....................................................................................................................... 43
4 Interrupts ............................................................................................................................ 45
5 JTAG Interface .................................................................................................................... 48
5.1 Block Diagram .......................................................................................................................... 49
5.2 Functional Description ............................................................................................................... 49
5.2.1 JTAG Interface Pins .................................................................................................................. 50
5.2.2 JTAG TAP Controller ................................................................................................................. 51
5.2.3 Shift Registers .......................................................................................................................... 52
5.2.4 Operational Considerations ........................................................................................................ 52
5.3 Initialization and Configuration ................................................................................................... 55
5.4 Register Descriptions ................................................................................................................ 55
5.4.1 Instruction Register (IR) ............................................................................................................. 55
5.4.2 Data Registers .......................................................................................................................... 57
6 System Control ................................................................................................................... 59
6.1 Functional Description ............................................................................................................... 59
6.1.1 Device Identification .................................................................................................................. 59
6.1.2 Reset Control ............................................................................................................................ 59
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6.1.3 Power Control ........................................................................................................................... 62
6.1.4 Clock Control ............................................................................................................................ 62
6.1.5 System Control ......................................................................................................................... 64
6.2 Initialization and Configuration ................................................................................................... 65
6.3 Register Map ............................................................................................................................ 65
6.4 Register Descriptions ................................................................................................................ 66
7 Hibernation Module .......................................................................................................... 120
7.1 Block Diagram ........................................................................................................................ 121
7.2 Functional Description ............................................................................................................. 121
7.2.1 Register Access Timing ........................................................................................................... 121
7.2.2 Clock Source .......................................................................................................................... 122
7.2.3 Battery Management ............................................................................................................... 122
7.2.4 Real-Time Clock ...................................................................................................................... 122
7.2.5 Non-Volatile Memory ............................................................................................................... 123
7.2.6 Power Control ......................................................................................................................... 123
7.2.7 Interrupts and Status ............................................................................................................... 123
7.3 Initialization and Configuration ................................................................................................. 124
7.3.1 Initialization ............................................................................................................................. 124
7.3.2 RTC Match Functionality (No Hibernation) ................................................................................ 124
7.3.3 RTC Match/Wake-Up from Hibernation ..................................................................................... 124
7.3.4 External Wake-Up from Hibernation .......................................................................................... 125
7.3.5 RTC/External Wake-Up from Hibernation .................................................................................. 125
7.4 Register Map .......................................................................................................................... 125
7.5 Register Descriptions .............................................................................................................. 126
8 Internal Memory ............................................................................................................... 139
8.1 Block Diagram ........................................................................................................................ 139
8.2 Functional Description ............................................................................................................. 139
8.2.1 SRAM Memory ........................................................................................................................ 139
8.2.2 Flash Memory ......................................................................................................................... 140
8.3 Flash Memory Initialization and Configuration ........................................................................... 141
8.3.1 Flash Programming ................................................................................................................. 141
8.3.2 Nonvolatile Register Programming ........................................................................................... 142
8.4 Register Map .......................................................................................................................... 142
8.5 Flash Register Descriptions (Flash Control Offset) ..................................................................... 143
8.6 Flash Register Descriptions (System Control Offset) .................................................................. 150
9 General-Purpose Input/Outputs (GPIOs) ....................................................................... 163
9.1 Functional Description ............................................................................................................. 163
9.1.1 Data Control ........................................................................................................................... 164
9.1.2 Interrupt Control ...................................................................................................................... 165
9.1.3 Mode Control .......................................................................................................................... 166
9.1.4 Commit Control ....................................................................................................................... 166
9.1.5 Pad Control ............................................................................................................................. 166
9.1.6 Identification ........................................................................................................................... 166
9.2 Initialization and Configuration ................................................................................................. 166
9.3 Register Map .......................................................................................................................... 168
9.4 Register Descriptions .............................................................................................................. 169
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10 General-Purpose Timers ................................................................................................. 204
10.1 Block Diagram ........................................................................................................................ 204
10.2 Functional Description ............................................................................................................. 205
10.2.1 GPTM Reset Conditions .......................................................................................................... 206
10.2.2 32-Bit Timer Operating Modes .................................................................................................. 206
10.2.3 16-Bit Timer Operating Modes .................................................................................................. 207
10.3 Initialization and Configuration ................................................................................................. 211
10.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 211
10.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 212
10.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 212
10.3.4 16-Bit Input Edge Count Mode ................................................................................................. 213
10.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 213
10.3.6 16-Bit PWM Mode ................................................................................................................... 214
10.4 Register Map .......................................................................................................................... 214
10.5 Register Descriptions .............................................................................................................. 215
11 Watchdog Timer ............................................................................................................... 240
11.1 Block Diagram ........................................................................................................................ 240
11.2 Functional Description ............................................................................................................. 240
11.3 Initialization and Configuration ................................................................................................. 241
11.4 Register Map .......................................................................................................................... 241
11.5 Register Descriptions .............................................................................................................. 242
12 Analog-to-Digital Converter (ADC) ................................................................................. 263
12.1 Block Diagram ........................................................................................................................ 264
12.2 Functional Description ............................................................................................................. 264
12.2.1 Sample Sequencers ................................................................................................................ 264
12.2.2 Module Control ........................................................................................................................ 265
12.2.3 Hardware Sample Averaging Circuit ......................................................................................... 266
12.2.4 Analog-to-Digital Converter ...................................................................................................... 266
12.2.5 Test Modes ............................................................................................................................. 266
12.2.6 Internal Temperature Sensor .................................................................................................... 266
12.3 Initialization and Configuration ................................................................................................. 267
12.3.1 Module Initialization ................................................................................................................. 267
12.3.2 Sample Sequencer Configuration ............................................................................................. 267
12.4 Register Map .......................................................................................................................... 268
12.5 Register Descriptions .............................................................................................................. 269
13 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 296
13.1 Block Diagram ........................................................................................................................ 297
13.2 Functional Description ............................................................................................................. 297
13.2.1 Transmit/Receive Logic ........................................................................................................... 297
13.2.2 Baud-Rate Generation ............................................................................................................. 298
13.2.3 Data Transmission .................................................................................................................. 299
13.2.4 Serial IR (SIR) ......................................................................................................................... 299
13.2.5 FIFO Operation ....................................................................................................................... 300
13.2.6 Interrupts ................................................................................................................................ 300
13.2.7 Loopback Operation ................................................................................................................ 301
13.2.8 IrDA SIR block ........................................................................................................................ 301
13.3 Initialization and Configuration ................................................................................................. 301
13.4 Register Map .......................................................................................................................... 302
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13.5 Register Descriptions .............................................................................................................. 303
14 Synchronous Serial Interface (SSI) ................................................................................ 337
14.1 Block Diagram ........................................................................................................................ 337
14.2 Functional Description ............................................................................................................. 337
14.2.1 Bit Rate Generation ................................................................................................................. 338
14.2.2 FIFO Operation ....................................................................................................................... 338
14.2.3 Interrupts ................................................................................................................................ 338
14.2.4 Frame Formats ....................................................................................................................... 339
14.3 Initialization and Configuration ................................................................................................. 346
14.4 Register Map .......................................................................................................................... 347
14.5 Register Descriptions .............................................................................................................. 348
15 Inter-Integrated Circuit (I2C) Interface ............................................................................ 374
15.1 Block Diagram ........................................................................................................................ 374
15.2 Functional Description ............................................................................................................. 374
15.2.1 I2C Bus Functional Overview .................................................................................................... 375
15.2.2 Available Speed Modes ........................................................................................................... 377
15.2.3 Interrupts ................................................................................................................................ 378
15.2.4 Loopback Operation ................................................................................................................ 378
15.2.5 Command Sequence Flow Charts ............................................................................................ 379
15.3 Initialization and Configuration ................................................................................................. 385
15.4 I2C Register Map ..................................................................................................................... 386
15.5 Register Descriptions (I2C Master) ........................................................................................... 387
15.6 Register Descriptions (I2C Slave) ............................................................................................. 400
16 Ethernet Controller .......................................................................................................... 409
16.1 Block Diagram ........................................................................................................................ 410
16.2 Functional Description ............................................................................................................. 410
16.2.1 Internal MII Operation .............................................................................................................. 410
16.2.2 PHY Configuration/Operation ................................................................................................... 411
16.2.3 MAC Configuration/Operation .................................................................................................. 412
16.2.4 Interrupts ................................................................................................................................ 414
16.3 Initialization and Configuration ................................................................................................. 415
16.4 Ethernet Register Map ............................................................................................................. 415
16.5 Ethernet MAC Register Descriptions ......................................................................................... 417
16.6 MII Management Register Descriptions ..................................................................................... 434
17 Analog Comparators ....................................................................................................... 453
17.1 Block Diagram ........................................................................................................................ 453
17.2 Functional Description ............................................................................................................. 454
17.2.1 Internal Reference Programming .............................................................................................. 455
17.3 Initialization and Configuration ................................................................................................. 456
17.4 Register Map .......................................................................................................................... 456
17.5 Register Descriptions .............................................................................................................. 457
18 Pulse Width Modulator (PWM) ........................................................................................ 465
18.1 Block Diagram ........................................................................................................................ 465
18.2 Functional Description ............................................................................................................. 465
18.2.1 PWM Timer ............................................................................................................................. 465
18.2.2 PWM Comparators .................................................................................................................. 466
18.2.3 PWM Signal Generator ............................................................................................................ 467
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18.2.4 Dead-Band Generator ............................................................................................................. 468
18.2.5 Interrupt/ADC-Trigger Selector ................................................................................................. 468
18.2.6 Synchronization Methods ......................................................................................................... 468
18.2.7 Fault Conditions ...................................................................................................................... 469
18.2.8 Output Control Block ............................................................................................................... 469
18.3 Initialization and Configuration ................................................................................................. 469
18.4 Register Map .......................................................................................................................... 470
18.5 Register Descriptions .............................................................................................................. 472
19 Quadrature Encoder Interface (QEI) ............................................................................... 501
19.1 Block Diagram ........................................................................................................................ 501
19.2 Functional Description ............................................................................................................. 502
19.3 Initialization and Configuration ................................................................................................. 504
19.4 Register Map .......................................................................................................................... 505
19.5 Register Descriptions .............................................................................................................. 505
20 Pin Diagram ...................................................................................................................... 518
21 Signal Tables .................................................................................................................... 519
22 Operating Characteristics ............................................................................................... 534
23 Electrical Characteristics ................................................................................................ 535
23.1 DC Characteristics .................................................................................................................. 535
23.1.1 Maximum Ratings ................................................................................................................... 535
23.1.2 Recommended DC Operating Conditions .................................................................................. 535
23.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 536
23.1.4 Power Specifications ............................................................................................................... 536
23.1.5 Flash Memory Characteristics .................................................................................................. 538
23.2 AC Characteristics ................................................................................................................... 538
23.2.1 Load Conditions ...................................................................................................................... 538
23.2.2 Clocks .................................................................................................................................... 538
23.2.3 Analog-to-Digital Converter ...................................................................................................... 539
23.2.4 Analog Comparator ................................................................................................................. 540
23.2.5 I2C ......................................................................................................................................... 540
23.2.6 Ethernet Controller .................................................................................................................. 541
23.2.7 Hibernation Module ................................................................................................................. 544
23.2.8 Synchronous Serial Interface (SSI) ........................................................................................... 544
23.2.9 JTAG and Boundary Scan ........................................................................................................ 546
23.2.10 General-Purpose I/O ............................................................................................................... 547
23.2.11 Reset ..................................................................................................................................... 548
24 Package Information ........................................................................................................ 550
A Serial Flash Loader .......................................................................................................... 552
A.1 Serial Flash Loader ................................................................................................................. 552
A.2 Interfaces ............................................................................................................................... 552
A.2.1 UART ..................................................................................................................................... 552
A.2.2 SSI ......................................................................................................................................... 552
A.3 Packet Handling ...................................................................................................................... 553
A.3.1 Packet Format ........................................................................................................................ 553
A.3.2 Sending Packets ..................................................................................................................... 553
A.3.3 Receiving Packets ................................................................................................................... 553
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A.4 Commands ............................................................................................................................. 554
A.4.1 COMMAND_PING (0X20) ........................................................................................................ 554
A.4.2 COMMAND_GET_STATUS (0x23) ........................................................................................... 554
A.4.3 COMMAND_DOWNLOAD (0x21) ............................................................................................. 554
A.4.4 COMMAND_SEND_DATA (0x24) ............................................................................................. 555
A.4.5 COMMAND_RUN (0x22) ......................................................................................................... 555
A.4.6 COMMAND_RESET (0x25) ..................................................................................................... 555
B Register Quick Reference ............................................................................................... 557
C Ordering and Contact Information ................................................................................. 577
C.1 Ordering Information ................................................................................................................ 577
C.2 Kits ......................................................................................................................................... 577
C.3 Company Information .............................................................................................................. 577
C.4 Support Information ................................................................................................................. 578
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List of Figures
Figure 1-1. Stellaris®6000 Series High-Level Block Diagram ............................................................... 29
Figure 2-1. CPU Block Diagram ......................................................................................................... 38
Figure 2-2. TPIU Block Diagram ........................................................................................................ 39
Figure 5-1. JTAG Module Block Diagram ............................................................................................ 49
Figure 5-2. Test Access Port State Machine ....................................................................................... 52
Figure 5-3. IDCODE Register Format ................................................................................................. 57
Figure 5-4. BYPASS Register Format ................................................................................................ 58
Figure 5-5. Boundary Scan Register Format ....................................................................................... 58
Figure 6-1. External Circuitry to Extend Reset .................................................................................... 60
Figure 7-1. Hibernation Module Block Diagram ................................................................................. 121
Figure 8-1. Flash Block Diagram ...................................................................................................... 139
Figure 9-1. GPIO Port Block Diagram ............................................................................................... 164
Figure 9-2. GPIODATA Write Example ............................................................................................. 165
Figure 9-3. GPIODATA Read Example ............................................................................................. 165
Figure 10-1. GPTM Module Block Diagram ........................................................................................ 205
Figure 10-2. 16-Bit Input Edge Count Mode Example .......................................................................... 209
Figure 10-3. 16-Bit Input Edge Time Mode Example ........................................................................... 210
Figure 10-4. 16-Bit PWM Mode Example ............................................................................................ 211
Figure 11-1. WDT Module Block Diagram .......................................................................................... 240
Figure 12-1. ADC Module Block Diagram ........................................................................................... 264
Figure 12-2. Internal Temperature Sensor Characteristic ..................................................................... 267
Figure 13-1. UART Module Block Diagram ......................................................................................... 297
Figure 13-2. UART Character Frame ................................................................................................. 298
Figure 13-3. IrDA Data Modulation ..................................................................................................... 300
Figure 14-1. SSI Module Block Diagram ............................................................................................. 337
Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 339
Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 340
Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 341
Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 341
Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 342
Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 343
Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 343
Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 344
Figure 14-10. MICROWIRE Frame Format (Single Frame) .................................................................... 345
Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 346
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 346
Figure 15-1. I2C Block Diagram ......................................................................................................... 374
Figure 15-2. I2C Bus Configuration .................................................................................................... 375
Figure 15-3. START and STOP Conditions ......................................................................................... 375
Figure 15-4. Complete Data Transfer with a 7-Bit Address ................................................................... 376
Figure 15-5. R/S Bit in First Byte ........................................................................................................ 376
Figure 15-6. Data Validity During Bit Transfer on the I2C Bus ............................................................... 376
Figure 15-7. Master Single SEND ...................................................................................................... 379
Figure 15-8. Master Single RECEIVE ................................................................................................. 380
Figure 15-9. Master Burst SEND ....................................................................................................... 381
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Figure 15-10. Master Burst RECEIVE .................................................................................................. 382
Figure 15-11. Master Burst RECEIVE after Burst SEND ........................................................................ 383
Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 384
Figure 15-13. Slave Command Sequence ............................................................................................ 385
Figure 16-1. Ethernet Controller Block Diagram .................................................................................. 410
Figure 16-2. Ethernet Controller ......................................................................................................... 410
Figure 16-3. Ethernet Frame ............................................................................................................. 412
Figure 17-1. Analog Comparator Module Block Diagram ..................................................................... 453
Figure 17-2. Structure of Comparator Unit .......................................................................................... 454
Figure 17-3. Comparator Internal Reference Structure ........................................................................ 455
Figure 18-1. PWM Module Block Diagram .......................................................................................... 465
Figure 18-2. PWM Count-Down Mode ................................................................................................ 466
Figure 18-3. PWM Count-Up/Down Mode .......................................................................................... 467
Figure 18-4. PWM Generation Example In Count-Up/Down Mode ....................................................... 467
Figure 18-5. PWM Dead-Band Generator ........................................................................................... 468
Figure 19-1. QEI Block Diagram ........................................................................................................ 502
Figure 19-2. Quadrature Encoder and Velocity Predivider Operation .................................................... 503
Figure 20-1. Pin Connection Diagram ................................................................................................ 518
Figure 23-1. Load Conditions ............................................................................................................ 538
Figure 23-2. I2C Timing ..................................................................................................................... 541
Figure 23-3. External XTLP Oscillator Characteristics ......................................................................... 543
Figure 23-4. Hibernation Module Timing ............................................................................................. 544
Figure 23-5. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 545
Figure 23-6. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 545
Figure 23-7. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 546
Figure 23-8. JTAG Test Clock Input Timing ......................................................................................... 547
Figure 23-9. JTAG Test Access Port (TAP) Timing .............................................................................. 547
Figure 23-10. JTAG TRST Timing ........................................................................................................ 547
Figure 23-11. External Reset Timing (RST) .......................................................................................... 548
Figure 23-12. Power-On Reset Timing ................................................................................................. 549
Figure 23-13. Brown-Out Reset Timing ................................................................................................ 549
Figure 23-14. Software Reset Timing ................................................................................................... 549
Figure 23-15. Watchdog Reset Timing ................................................................................................. 549
Figure 24-1. 100-Pin LQFP Package .................................................................................................. 550
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LM3S6965 Microcontroller
List of Tables
Table 1. Documentation Conventions ............................................................................................ 20
Table 3-1. Memory Map ................................................................................................................... 43
Table 4-1. Exception Types .............................................................................................................. 45
Table 4-2. Interrupts ........................................................................................................................ 46
Table 5-1. JTAG Port Pins Reset State ............................................................................................. 50
Table 5-2. JTAG Instruction Register Commands ............................................................................... 55
Table 6-1. System Control Register Map ........................................................................................... 65
Table 7-1. Hibernation Module Register Map ................................................................................... 125
Table 8-1. Flash Protection Policy Combinations ............................................................................. 141
Table 8-2. Flash Resident Registers ............................................................................................... 142
Table 8-3. Flash Register Map ........................................................................................................ 142
Table 9-1. GPIO Pad Configuration Examples ................................................................................. 167
Table 9-2. GPIO Interrupt Configuration Example ............................................................................ 167
Table 9-3. GPIO Register Map ....................................................................................................... 168
Table 10-1. Available CCP Pins ........................................................................................................ 205
Table 10-2. 16-Bit Timer With Prescaler Configurations ..................................................................... 208
Table 10-3. Timers Register Map ...................................................................................................... 214
Table 11-1. Watchdog Timer Register Map ........................................................................................ 241
Table 12-1. Samples and FIFO Depth of Sequencers ........................................................................ 264
Table 12-2. ADC Register Map ......................................................................................................... 268
Table 13-1. UART Register Map ....................................................................................................... 302
Table 14-1. SSI Register Map .......................................................................................................... 347
Table 15-1. Examples of I2C Master Timer Period versus Speed Mode ............................................... 377
Table 15-2. Inter-Integrated Circuit (I2C) Interface Register Map ......................................................... 386
Table 15-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 391
Table 16-1. TX & RX FIFO Organization ........................................................................................... 413
Table 16-2. Ethernet Register Map ................................................................................................... 416
Table 17-1. Comparator 0 Operating Modes ...................................................................................... 454
Table 17-2. Comparator 1 Operating Modes ..................................................................................... 455
Table 17-3. Internal Reference Voltage and ACREFCTL Field Values ................................................. 455
Table 17-4. Analog Comparators Register Map ................................................................................. 457
Table 18-1. PWM Register Map ........................................................................................................ 470
Table 19-1. QEI Register Map .......................................................................................................... 505
Table 21-1. Signals by Pin Number ................................................................................................... 519
Table 21-2. Signals by Signal Name ................................................................................................. 523
Table 21-3. Signals by Function, Except for GPIO ............................................................................. 528
Table 21-4. GPIO Pins and Alternate Functions ................................................................................. 532
Table 22-1. Temperature Characteristics ........................................................................................... 534
Table 22-2. Thermal Characteristics ................................................................................................. 534
Table 23-1. Maximum Ratings .......................................................................................................... 535
Table 23-2. Recommended DC Operating Conditions ........................................................................ 535
Table 23-3. LDO Regulator Characteristics ....................................................................................... 536
Table 23-4. Detailed Power Specifications ........................................................................................ 537
Table 23-5. Flash Memory Characteristics ........................................................................................ 538
Table 23-6. Phase Locked Loop (PLL) Characteristics ....................................................................... 538
Table 23-7. Clock Characteristics ..................................................................................................... 538
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Table 23-8. Crystal Characteristics ................................................................................................... 539
Table 23-9. ADC Characteristics ....................................................................................................... 539
Table 23-10. Analog Comparator Characteristics ................................................................................. 540
Table 23-11. Analog Comparator Voltage Reference Characteristics .................................................... 540
Table 23-12. I2C Characteristics ......................................................................................................... 540
Table 23-13. 100BASE-TX Transmitter Characteristics ........................................................................ 541
Table 23-14. 100BASE-TX Transmitter Characteristics (informative) ..................................................... 541
Table 23-15. 100BASE-TX Receiver Characteristics ............................................................................ 541
Table 23-16. 10BASE-T Transmitter Characteristics ............................................................................ 541
Table 23-17. 10BASE-T Transmitter Characteristics (informative) ......................................................... 542
Table 23-18. 10BASE-T Receiver Characteristics ................................................................................ 542
Table 23-19. Isolation Transformers ................................................................................................... 542
Table 23-20. Ethernet Reference Crystal ............................................................................................ 543
Table 23-21. External XTLP Oscillator Characteristics ......................................................................... 543
Table 23-22. Hibernation Module Characteristics ................................................................................. 544
Table 23-23. SSI Characteristics ........................................................................................................ 544
Table 23-24. JTAG Characteristics ..................................................................................................... 546
Table 23-25. GPIO Characteristics ..................................................................................................... 548
Table 23-26. Reset Characteristics ..................................................................................................... 548
Table C-1. Part Ordering Information ............................................................................................... 577
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LM3S6965 Microcontroller
List of Registers
System Control .............................................................................................................................. 59
Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 67
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 69
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 70
Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 71
Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 72
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 73
Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 74
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 75
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 79
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 80
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 82
Register 12: Device Identification 1 (DID1), offset 0x004 ....................................................................... 83
Register 13: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 85
Register 14: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 86
Register 15: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 88
Register 16: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 90
Register 17: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 92
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 94
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 96
Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 98
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 100
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 103
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 106
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 109
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 111
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 113
Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 115
Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 116
Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 118
Hibernation Module ..................................................................................................................... 120
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 127
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 128
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 129
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 130
Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 131
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 133
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 134
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 135
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 136
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 137
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 138
Internal Memory ........................................................................................................................... 139
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 144
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 145
Preliminary
13November 30, 2007
Table of Contents
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 146
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 148
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 149
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 150
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 151
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 152
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 153
Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 154
Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 155
Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 156
Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 157
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 158
Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 159
Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 160
Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 161
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 162
General-Purpose Input/Outputs (GPIOs) ................................................................................... 163
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 170
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 171
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 172
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 173
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 174
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 175
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 176
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 177
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 178
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 179
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 181
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 182
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 183
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 184
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 185
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 186
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 187
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 188
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 189
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 190
Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 192
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 193
Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 194
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 195
Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 196
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 197
Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 198
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 199
Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 200
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 201
Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 202
Preliminary
November 30, 200714
LM3S6965 Microcontroller
Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 203
General-Purpose Timers ............................................................................................................. 204
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 216
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 217
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 219
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 221
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 224
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 226
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 227
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 228
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 230
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 231
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 232
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 233
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 234
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 235
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 236
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 237
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 238
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 239
Watchdog Timer ........................................................................................................................... 240
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 243
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 244
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 245
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 246
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 247
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 248
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 249
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 250
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 251
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 252
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 253
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 254
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 255
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 256
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 257
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 258
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 259
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 260
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 261
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 262
Analog-to-Digital Converter (ADC) ............................................................................................. 263
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 270
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 271
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 272
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 273
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 274
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 275
Preliminary
15November 30, 2007
Table of Contents
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 278
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 279
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 280
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 281
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 282
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 284
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 287
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 287
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 287
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 287
Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 288
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 288
Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 288
Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 288
Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 289
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 289
Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 290
Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 290
Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 292
Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 293
Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 294
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 296
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 304
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 306
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 308
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 310
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 311
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 312
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 313
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 315
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 317
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 319
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 321
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 322
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 323
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 325
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 326
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 327
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 328
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 329
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 330
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 331
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 332
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 333
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 334
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 335
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 336
Preliminary
November 30, 200716
LM3S6965 Microcontroller
Synchronous Serial Interface (SSI) ............................................................................................ 337
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 349
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 351
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 353
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 354
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 356
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 357
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 359
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 360
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 361
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 362
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 363
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 364
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 365
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 366
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 367
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 368
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 369
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 370
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 371
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 372
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 373
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 374
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 388
Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 389
Register 3: I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 393
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 394
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 395
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 396
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 397
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 398
Register 9: I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 399
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 401
Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 402
Register 12: I2C Slave Data (I2CSDR), offset 0x008 ........................................................................... 404
Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 405
Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 406
Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 407
Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 408
Ethernet Controller ...................................................................................................................... 409
Register 1: Ethernet MAC Raw Interrupt Status (MACRIS), offset 0x000 ............................................ 418
Register 2: Ethernet MAC Interrupt Acknowledge (MACIACK), offset 0x000 ....................................... 420
Register 3: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... 421
Register 4: Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ 422
Register 5: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... 423
Register 6: Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. 424
Register 7: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 426
17November 30, 2007
Preliminary
Table of Contents
Register 8: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. 427
Register 9: Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... 428
Register 10: Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ 429
Register 11: Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 430
Register 12: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 431
Register 13: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. 432
Register 14: Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... 433
Register 15: Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... 434
Register 16: Ethernet PHY Management Register 0 – Control (MR0), address 0x00 ............................. 435
Register 17: Ethernet PHY Management Register 1 – Status (MR1), address 0x01 .............................. 437
Register 18: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 ................. 439
Register 19: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 ................. 440
Register 20: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address
0x04 ............................................................................................................................. 441
Register 21: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability
(MR5), address 0x05 ..................................................................................................... 443
Register 22: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address
0x06 ............................................................................................................................. 444
Register 23: Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 ............. 445
Register 24: Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address
0x11 .............................................................................................................................. 447
Register 25: Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12 ..................... 449
Register 26: Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13 ....... 450
Register 27: Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17 ......... 451
Register 28: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), address 0x18 .......... 452
Analog Comparators ................................................................................................................... 453
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 458
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 459
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 460
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 461
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 462
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40 ....................................................... 462
Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 463
Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x44 ....................................................... 463
Pulse Width Modulator (PWM) .................................................................................................... 465
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 473
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 474
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 475
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 476
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 477
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 478
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 479
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 480
Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 481
Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 482
Register 11: PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 482
Register 12: PWM2 Control (PWM2CTL), offset 0x0C0 ...................................................................... 482
Register 13: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 .................................... 484
Preliminary
November 30, 200718
LM3S6965 Microcontroller
Register 14: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 .................................... 484
Register 15: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 .................................... 484
Register 16: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 486
Register 17: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 .................................................... 486
Register 18: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 ................................................... 486
Register 19: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 487
Register 20: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ........................................... 487
Register 21: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC ........................................... 487
Register 22: PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 488
Register 23: PWM1 Load (PWM1LOAD), offset 0x090 ....................................................................... 488
Register 24: PWM2 Load (PWM2LOAD), offset 0x0D0 ....................................................................... 488
Register 25: PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 489
Register 26: PWM1 Counter (PWM1COUNT), offset 0x094 ................................................................ 489
Register 27: PWM2 Counter (PWM2COUNT), offset 0x0D4 ............................................................... 489
Register 28: PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 490
Register 29: PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................. 490
Register 30: PWM2 Compare A (PWM2CMPA), offset 0x0D8 ............................................................. 490
Register 31: PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 491
Register 32: PWM1 Compare B (PWM1CMPB), offset 0x09C ............................................................. 491
Register 33: PWM2 Compare B (PWM2CMPB), offset 0x0DC ............................................................ 491
Register 34: PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 492
Register 35: PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ................................................ 492
Register 36: PWM2 Generator A Control (PWM2GENA), offset 0x0E0 ................................................ 492
Register 37: PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 495
Register 38: PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ................................................ 495
Register 39: PWM2 Generator B Control (PWM2GENB), offset 0x0E4 ................................................ 495
Register 40: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 498
Register 41: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ................................................. 498
Register 42: PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 ................................................ 498
Register 43: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 499
Register 44: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ............................. 499
Register 45: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC ............................. 499
Register 46: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 500
Register 47: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ............................. 500
Register 48: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 ............................. 500
Quadrature Encoder Interface (QEI) .......................................................................................... 501
Register 1: QEI Control (QEICTL), offset 0x000 ................................................................................ 506
Register 2: QEI Status (QEISTAT), offset 0x004 ................................................................................ 508
Register 3: QEI Position (QEIPOS), offset 0x008 .............................................................................. 509
Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C ....................................................... 510
Register 5: QEI Timer Load (QEILOAD), offset 0x010 ....................................................................... 511
Register 6: QEI Timer (QEITIME), offset 0x014 ................................................................................. 512
Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018 ............................................................. 513
Register 8: QEI Velocity (QEISPEED), offset 0x01C .......................................................................... 514
Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020 ............................................................... 515
Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024 ............................................................. 516
Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028 ..................................................... 517
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19November 30, 2007
About This Document
About This Document
This data sheet provides reference information for the LM3S6965 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following documents are referenced by the data sheet, and available on the documentation CD
or from the Luminary Micro web site at www.luminarymicro.com:
■
ARM® Cortex™-M3 Technical Reference Manual
■
ARM® CoreSight Technical Reference Manual
■
ARM® v7-M Architecture Application Level Reference Manual
The following related documents are also referenced:
■
IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the Luminary Micro web
site for additional documentation, including application notes and white papers.
Documentation Conventions
This document uses the conventions shown in Table 1 on page 20.
Table 1. Documentation Conventions
MeaningNotation
General Register Notation
REGISTER
offset 0xnnn
Register N
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
A single bit in a register.bit
Two or more consecutive and related bits.bit field
A hexadecimal increment to a register's address, relative to that module's base address as specified
in “Memory Map” on page 43.
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
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November 30, 200720
reserved
yy:xx
Register Bit/Field
Types
R/W1C
W1C
Reset Value
Pin/Signal Notation
assert a signal
SIGNAL
SIGNAL
Numbers
X
0x
LM3S6965 Microcontroller
MeaningNotation
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.RC
Software can read this field. Always write the chip reset value.RO
Software can read or write this field.R/W
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
Only a write by software is valid; a read of the register returns no meaningful data.WO
This value in the register bit diagram shows the bit/field value after any reset, unless noted.Register Bit/Field
Bit cleared to 0 on chip reset.0
Bit set to 1 on chip reset.1
Nondeterministic.-
Pin alternate function; a pin defaults to the signal without the brackets.[ ]
Refers to the physical connection on the package.pin
Refers to the electrical signal encoding of a pin.signal
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
Change the value of the signal from the logically True state to the logically False state.deassert a signal
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
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21November 30, 2007
Architectural Overview
1 Architectural Overview
The Luminary Micro Stellaris®family of microcontrollers—the first ARM® Cortex™-M3 based
controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller
applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to
legacy 8- and 16-bit devices, all in a package with a small footprint.
The Stellaris®family offers efficient performance and extensive integration, favorably positioning
the device into cost-conscious applications requiring significant control-processing and connectivity
capabilities. The Stellaris®LM3S1000 series extends the Stellaris®family with larger on-chip
memories, enhanced power management, and expanded I/O and control capabilities. The Stellaris
LM3S2000 series, designed for Controller Area Network (CAN) applications, extends the Stellaris
family with Bosch CAN networking technology, the golden standard in short-haul industrial networks.
The Stellaris®LM3S2000 series also marks the first integration of CAN capabilities with the
revolutionary Cortex-M3 core. The Stellaris®LM3S6000 series combines both a 10/100 Ethernet
Media Access Control (MAC) and Physical (PHY) layer, marking the first time that integrated
connectivity is available with an ARM Cortex-M3 MCU and the only integrated 10/100 Ethernet MAC
and PHY available in an ARM architecture MCU. The Stellaris®LM3S8000 series combines Bosch
Controller Area Network technology with both a 10/100 Ethernet Media Access Control (MAC) and
Physical (PHY) layer.
®
The LM3S6965 microcontroller is targeted for industrial applications, including remote monitoring,
electronic point-of-sale machines, test and measurement equipment, network appliances and
switches, factory automation, HVAC and building control, gaming equipment, motion control, medical
instrumentation, and fire and security.
For applications requiring extreme conservation of power, the LM3S6965 microcontroller features
a Battery-backed Hibernation module to efficiently power down the LM3S6965 to a low-power state
during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time
counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated
non-volatile memory, the Hibernation module positions the LM3S6965 microcontroller perfectly for
battery applications.
In addition, the LM3S6965 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S6965 microcontroller is code-compatible
to all members of the extensive Stellaris®family; providing flexibility to fit our customers' precise
needs.
Luminary Micro offers a complete solution to get to market quickly, with evaluation and development
boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong
support, sales, and distributor network.
1.1 Product Features
The LM3S6965 microcontroller includes the following product features:
■ 32-Bit RISC Performance
– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
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LM3S6965 Microcontroller
– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
– Thumb®-compatible Thumb-2-only instruction set processor core for high code density
– 50-MHz operation
– Hardware-division and single-cycle-multiplication
– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
– 38 interrupts with eight priority levels
– Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
– Unaligned data access, enabling data to be efficiently packed into memory
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
■ Internal Memory
– 256 KB single-cycle flash
• User-managed flash block protection on a 2-KB block basis
• User-managed flash data programming
• User-defined and managed flash-protection block
– 64 KB single-cycle SRAM
■ General-Purpose Timers
– Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers.
Each GPTM can be configured to operate independently:
• As a single 32-bit timer
• As one 32-bit Real-Time Clock (RTC) to event capture
• For Pulse Width Modulation (PWM)
• To trigger analog-to-digital conversions
– 32-bit Timer modes
• Programmable one-shot timer
• Programmable periodic timer
• Real-Time Clock when using an external 32.768-KHz clock as the input
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23November 30, 2007
Architectural Overview
• User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU
• ADC event trigger
– 16-bit Timer modes
• General-purpose timer function with an 8-bit prescaler
• Programmable one-shot timer
• Programmable periodic timer
• User-enabled stalling when the controller asserts CPU Halt flag during debug
• ADC event trigger
– 16-bit Input Capture modes
• Input edge count capture
• Input edge time capture
Halt flag during debug
– 16-bit PWM mode
• Simple PWM mode with software-programmable output inversion of the PWM signal
■ ARM FiRM-compliant Watchdog Timer
– 32-bit down counter with a programmable load register
– Separate watchdog clock with an enable
– Programmable interrupt generation logic with interrupt masking
– Lock register protection from runaway software
– Reset generation logic with an enable/disable
– User-enabled stalling when the controller asserts the CPU Halt flag during debug
■ 10/100 Ethernet Controller
– Conforms to the IEEE 802.3-2002 Specification
– Full- and half-duplex for both 100 Mbps and 10 Mbps operation
– Integrated 10/100 Mbps Transceiver (PHY)
– Automatic MDI/MDI-X cross-over correction
– Programmable MAC address
– Power-saving and power-down modes
■ Synchronous Serial Interface (SSI)
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Preliminary
LM3S6965 Microcontroller
– Master or slave operation
– Programmable clock bit rate and prescale
– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
– Programmable data frame size from 4 to 16 bits
– Internal loopback test mode for diagnostic/debug testing
■ UART
– Three fully programmable 16C550-type UARTs with IrDA support
– Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service
loading
– Programmable baud-rate generator with fractional divider
– Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
– Standard asynchronous communication bits for start, stop, and parity
– False-start-bit detection
– Line-break generation and detection
■ ADC
– Single- and differential-input configurations
– Four 10-bit channels (inputs) when used as single-ended inputs
– Sample rate of one million samples/second
– Flexible, configurable analog-to-digital conversion
– Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
– Each sequence triggered by software or internal event (timers, analog comparators, PWM
or GPIO)
– On-chip temperature sensor
■ Analog Comparators
– Two independent integrated analog comparators
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25November 30, 2007
Architectural Overview
– Configurable for output to: drive an output pin, generate an interrupt, or initiate an ADC sample
sequence
– Compare external pin input to external pin input or to internal programmable voltage reference
■ I2C
– Two I2C modules
– Master and slave receive and transmit operation with transmission speed up to 100 Kbps in
Standard mode and 400 Kbps in Fast mode
– Interrupt generation
– Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
■ PWM
– Three PWM generator blocks, each with one 16-bit counter, two comparators, a PWM
generator, and a dead-band generator
– One 16-bit counter
• Runs in Down or Up/Down mode
• Output frequency controlled by a 16-bit load value
• Load value updates can be synchronized
• Produces output signals at zero and load value
– Two PWM comparators
• Comparator value updates can be synchronized
• Produces output signals on match
– PWM generator
• Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals
• Produces two independent PWM signals
– Dead-band generator
• Produces two PWM signals with programmable dead-band delays suitable for driving a
half-H bridge
• Can be bypassed, leaving input PWM signals unmodified
– Flexible output control block with PWM output enable of each PWM signal
• PWM output enable of each PWM signal
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November 30, 200726
LM3S6965 Microcontroller
• Optional output inversion of each PWM signal (polarity control)
• Optional fault handling for each PWM signal
• Synchronization of timers in the PWM generator blocks
• Synchronization of timer/comparator updates across the PWM generator blocks
• Interrupt status summary of the PWM generator blocks
– Can initiate an ADC sample sequence
■ QEI
– Two QEI modules
– Hardware position integrator tracks the encoder position
– Velocity capture using built-in timer
– Interrupt generation on index pulse, velocity-timer expiration, direction change, and quadrature
error detection
■ GPIOs
– 0-42 GPIOs, depending on configuration
– 5-V-tolerant input/outputs
– Programmable interrupt generation as either edge-triggered or level-sensitive
– Bit masking in both read and write operations through address lines
– Can initiate an ADC sample sequence
– Programmable control for GPIO pad configuration:
• Weak pull-up or pull-down resistors
• 2-mA, 4-mA, and 8-mA pad drive
• Slew rate control for the 8-mA drive
• Open drain enables
• Digital input enables
■ Power
– On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
– Hibernation module handles the power-up/down 3.3 V sequencing and control for the core
digital logic and analog circuits
– Low-power options on controller: Sleep and Deep-sleep modes
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27November 30, 2007
Architectural Overview
– Low-power options for peripherals: software controls shutdown of individual peripherals
– User-enabled LDO unregulated voltage detection and automatic reset
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Flexible Reset Sources
– Power-on reset (POR)
– Reset pin assertion
– Brown-out (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
– Internal low drop-out (LDO) regulator output goes unregulated
■ Additional Features
– Six reset sources
– Programmable clock source control
– Clock gating to individual peripherals for power savings
– IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
– Debug access via JTAG and Serial Wire interfaces
– Full JTAG boundary scan
■ Industrial-range 100-pin RoHS-compliant LQFP package
1.2 Target Applications
■ Remote monitoring
■ Electronic point-of-sale (POS) machines
■ Test and measurement equipment
■ Network appliances and switches
■ Factory automation
■ HVAC and building control
■ Gaming equipment
■ Motion control
■ Medical instrumentation
■ Fire and security
November 30, 200728
Preliminary
■ Power and energy
■ Transportation
1.3 High-Level Block Diagram
Figure 1-1 on page 29 represents the full set of features in the Stellaris®6000 series of devices;
not all features may be available on the LM3S6965 microcontroller.
Figure 1-1. Stellaris®6000 Series High-Level Block Diagram
LM3S6965 Microcontroller
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29November 30, 2007
Architectural Overview
1.4 Functional Overview
The following sections provide an overview of the features of the LM3S6965 microcontroller. The
page number in parenthesis indicates where that feature is discussed in detail. Ordering and support
information can be found in “Ordering and Contact Information” on page 577.
1.4.1 ARM Cortex™-M3
1.4.1.1 Processor Core (see page 37)
All members of the Stellaris®product family, including the LM3S6965 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
“ARM Cortex-M3 Processor Core” on page 37 provides an overview of the ARM core; the core is
detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.1.2 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
1.4.1.3 Nested Vectored Interrupt Controller (NVIC)
The LM3S6965 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the
ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions
are handled in Handler Mode. The processor state is automatically stored to the stack on an
exception, and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed without
the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions
(system handlers) and 38 interrupts.
“Interrupts” on page 45 provides an overview of the NVIC controller and the interrupt map. Exceptions
and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.2 Motor Control Peripherals
To enhance motor control, the LM3S6965 controller features Pulse Width Modulation (PWM) outputs
and the Quadrature Encoder Interface (QEI).
November 30, 200730
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