TEXAS INSTRUMENTS LM3S6610 Technical data
PRELIMINARY
LM3S6610 Microcontroller
DATA SHEET
Copyright © 2007 Luminary Micro, Inc.DS-LM3S6610-1972
Legal Disclaimers and Trademark Information
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH LUMINARY MICRO PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN LUMINARY MICRO'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, LUMINARY MICRO ASSUMES NO
LIABILITY WHATSOEVER,AND LUMINARYMICRO DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY,RELATING TO SALE AND/OR
USE OF LUMINARY MICRO'S PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
LUMINARY MICRO'S PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE-SUSTAINING APPLICATIONS.
Luminary Micro may make changes to specications and product descriptions at any time, without notice. Contact your local Luminary Micro sales ofce
or your distributor to obtain the latest specications before placing your product order.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undened." Luminary Micro reserves these
for future denition and shall have no responsibility whatsoever for conicts or incompatibilities arising from future changes to them.
Copyright © 2007 Luminary Micro, Inc. All rights reserved. Stellaris, Luminary Micro, and the Luminary Micro logo are registered trademarks of
Luminary Micro, Inc. or its subsidiaries in the United States and other countries. ARM and Thumb are registered trademarks and Cortex is a trademark
of ARM Limited. Other names and brands may be claimed as the property of others.
Luminary Micro, Inc.
108 Wild Basin, Suite 350
Austin, TX 78746
Main: +1-512-279-8800
Fax: +1-512-279-8879
http://www.luminarymicro.com
Preliminary
November 30, 20072
LM3S6610 Microcontroller
Table of Contents
About This Document .................................................................................................................... 19
Audience .............................................................................................................................................. 19
About This Manual ................................................................................................................................ 19
Related Documents ............................................................................................................................... 19
Documentation Conventions .................................................................................................................. 19
1 Architectural Overview ...................................................................................................... 21
1.1 Product Features ...................................................................................................................... 21
1.2 Target Applications .................................................................................................................... 27
1.3 High-Level Block Diagram ......................................................................................................... 27
1.4 Functional Overview .................................................................................................................. 28
1.4.1 ARM Cortex™-M3 ..................................................................................................................... 29
1.4.2 Motor Control Peripherals .......................................................................................................... 29
1.4.3 Analog Peripherals .................................................................................................................... 30
1.4.4 Serial Communications Peripherals ............................................................................................ 31
1.4.5 System Peripherals ................................................................................................................... 32
1.4.6 Memory Peripherals .................................................................................................................. 33
1.4.7 Additional Features ................................................................................................................... 33
1.4.8 Hardware Details ...................................................................................................................... 34
2 ARM Cortex-M3 Processor Core ...................................................................................... 35
2.1 Block Diagram .......................................................................................................................... 36
2.2 Functional Description ............................................................................................................... 36
2.2.1 Serial Wire and JTAG Debug ..................................................................................................... 36
2.2.2 Embedded Trace Macrocell (ETM) ............................................................................................. 37
2.2.3 Trace Port Interface Unit (TPIU) ................................................................................................. 37
2.2.4 ROM Table ............................................................................................................................... 37
2.2.5 Memory Protection Unit (MPU) ................................................................................................... 37
2.2.6 Nested Vectored Interrupt Controller (NVIC) ................................................................................ 37
3 Memory Map ....................................................................................................................... 41
4 Interrupts ............................................................................................................................ 43
5 JTAG Interface .................................................................................................................... 46
5.1 Block Diagram .......................................................................................................................... 47
5.2 Functional Description ............................................................................................................... 47
5.2.1 JTAG Interface Pins .................................................................................................................. 48
5.2.2 JTAG TAP Controller ................................................................................................................. 49
5.2.3 Shift Registers .......................................................................................................................... 50
5.2.4 Operational Considerations ........................................................................................................ 50
5.3 Initialization and Configuration ................................................................................................... 53
5.4 Register Descriptions ................................................................................................................ 53
5.4.1 Instruction Register (IR) ............................................................................................................. 53
5.4.2 Data Registers .......................................................................................................................... 55
6 System Control ................................................................................................................... 57
6.1 Functional Description ............................................................................................................... 57
6.1.1 Device Identification .................................................................................................................. 57
6.1.2 Reset Control ............................................................................................................................ 57
Preliminary
3November 30, 2007
Table of Contents
6.1.3 Power Control ........................................................................................................................... 60
6.1.4 Clock Control ............................................................................................................................ 60
6.1.5 System Control ......................................................................................................................... 62
6.2 Initialization and Configuration ................................................................................................... 63
6.3 Register Map ............................................................................................................................ 63
6.4 Register Descriptions ................................................................................................................ 64
7 Hibernation Module .......................................................................................................... 118
7.1 Block Diagram ........................................................................................................................ 119
7.2 Functional Description ............................................................................................................. 119
7.2.1 Register Access Timing ........................................................................................................... 119
7.2.2 Clock Source .......................................................................................................................... 120
7.2.3 Battery Management ............................................................................................................... 120
7.2.4 Real-Time Clock ...................................................................................................................... 120
7.2.5 Non-Volatile Memory ............................................................................................................... 121
7.2.6 Power Control ......................................................................................................................... 121
7.2.7 Interrupts and Status ............................................................................................................... 121
7.3 Initialization and Configuration ................................................................................................. 122
7.3.1 Initialization ............................................................................................................................. 122
7.3.2 RTC Match Functionality (No Hibernation) ................................................................................ 122
7.3.3 RTC Match/Wake-Up from Hibernation ..................................................................................... 122
7.3.4 External Wake-Up from Hibernation .......................................................................................... 123
7.3.5 RTC/External Wake-Up from Hibernation .................................................................................. 123
7.4 Register Map .......................................................................................................................... 123
7.5 Register Descriptions .............................................................................................................. 124
8 Internal Memory ............................................................................................................... 137
8.1 Block Diagram ........................................................................................................................ 137
8.2 Functional Description ............................................................................................................. 137
8.2.1 SRAM Memory ........................................................................................................................ 137
8.2.2 Flash Memory ......................................................................................................................... 138
8.3 Flash Memory Initialization and Configuration ........................................................................... 139
8.3.1 Flash Programming ................................................................................................................. 139
8.3.2 Nonvolatile Register Programming ........................................................................................... 140
8.4 Register Map .......................................................................................................................... 140
8.5 Flash Register Descriptions (Flash Control Offset) ..................................................................... 141
8.6 Flash Register Descriptions (System Control Offset) .................................................................. 148
9 General-Purpose Input/Outputs (GPIOs) ....................................................................... 161
9.1 Functional Description ............................................................................................................. 161
9.1.1 Data Control ........................................................................................................................... 162
9.1.2 Interrupt Control ...................................................................................................................... 163
9.1.3 Mode Control .......................................................................................................................... 164
9.1.4 Commit Control ....................................................................................................................... 164
9.1.5 Pad Control ............................................................................................................................. 164
9.1.6 Identification ........................................................................................................................... 164
9.2 Initialization and Configuration ................................................................................................. 164
9.3 Register Map .......................................................................................................................... 165
9.4 Register Descriptions .............................................................................................................. 167
Preliminary
November 30, 20074
LM3S6610 Microcontroller
10 General-Purpose Timers ................................................................................................. 202
10.1 Block Diagram ........................................................................................................................ 202
10.2 Functional Description ............................................................................................................. 203
10.2.1 GPTM Reset Conditions .......................................................................................................... 204
10.2.2 32-Bit Timer Operating Modes .................................................................................................. 204
10.2.3 16-Bit Timer Operating Modes .................................................................................................. 205
10.3 Initialization and Configuration ................................................................................................. 209
10.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 209
10.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 210
10.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 210
10.3.4 16-Bit Input Edge Count Mode ................................................................................................. 211
10.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 211
10.3.6 16-Bit PWM Mode ................................................................................................................... 212
10.4 Register Map .......................................................................................................................... 212
10.5 Register Descriptions .............................................................................................................. 213
11 Watchdog Timer ............................................................................................................... 238
11.1 Block Diagram ........................................................................................................................ 238
11.2 Functional Description ............................................................................................................. 238
11.3 Initialization and Configuration ................................................................................................. 239
11.4 Register Map .......................................................................................................................... 239
11.5 Register Descriptions .............................................................................................................. 240
12 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 261
12.1 Block Diagram ........................................................................................................................ 262
12.2 Functional Description ............................................................................................................. 262
12.2.1 Transmit/Receive Logic ........................................................................................................... 262
12.2.2 Baud-Rate Generation ............................................................................................................. 263
12.2.3 Data Transmission .................................................................................................................. 264
12.2.4 Serial IR (SIR) ......................................................................................................................... 264
12.2.5 FIFO Operation ....................................................................................................................... 265
12.2.6 Interrupts ................................................................................................................................ 265
12.2.7 Loopback Operation ................................................................................................................ 266
12.2.8 IrDA SIR block ........................................................................................................................ 266
12.3 Initialization and Configuration ................................................................................................. 266
12.4 Register Map .......................................................................................................................... 267
12.5 Register Descriptions .............................................................................................................. 268
13 Synchronous Serial Interface (SSI) ................................................................................ 302
13.1 Block Diagram ........................................................................................................................ 302
13.2 Functional Description ............................................................................................................. 302
13.2.1 Bit Rate Generation ................................................................................................................. 303
13.2.2 FIFO Operation ....................................................................................................................... 303
13.2.3 Interrupts ................................................................................................................................ 303
13.2.4 Frame Formats ....................................................................................................................... 304
13.3 Initialization and Configuration ................................................................................................. 311
13.4 Register Map .......................................................................................................................... 312
13.5 Register Descriptions .............................................................................................................. 313
14 Inter-Integrated Circuit (I2C) Interface ............................................................................ 339
14.1 Block Diagram ........................................................................................................................ 339
Preliminary
5November 30, 2007
Table of Contents
14.2 Functional Description ............................................................................................................. 339
14.2.1 I2C Bus Functional Overview .................................................................................................... 340
14.2.2 Available Speed Modes ........................................................................................................... 342
14.2.3 Interrupts ................................................................................................................................ 343
14.2.4 Loopback Operation ................................................................................................................ 343
14.2.5 Command Sequence Flow Charts ............................................................................................ 343
14.3 Initialization and Configuration ................................................................................................. 350
14.4 I2C Register Map ..................................................................................................................... 351
14.5 Register Descriptions (I2C Master) ........................................................................................... 352
14.6 Register Descriptions (I2C Slave) ............................................................................................. 365
15 Ethernet Controller .......................................................................................................... 374
15.1 Block Diagram ........................................................................................................................ 375
15.2 Functional Description ............................................................................................................. 375
15.2.1 Internal MII Operation .............................................................................................................. 375
15.2.2 PHY Configuration/Operation ................................................................................................... 376
15.2.3 MAC Configuration/Operation .................................................................................................. 377
15.2.4 Interrupts ................................................................................................................................ 379
15.3 Initialization and Configuration ................................................................................................. 380
15.4 Ethernet Register Map ............................................................................................................. 380
15.5 Ethernet MAC Register Descriptions ......................................................................................... 382
15.6 MII Management Register Descriptions ..................................................................................... 399
16 Analog Comparators ....................................................................................................... 418
16.1 Block Diagram ........................................................................................................................ 419
16.2 Functional Description ............................................................................................................. 419
16.2.1 Internal Reference Programming .............................................................................................. 421
16.3 Initialization and Configuration ................................................................................................. 422
16.4 Register Map .......................................................................................................................... 422
16.5 Register Descriptions .............................................................................................................. 423
17 Pulse Width Modulator (PWM) ........................................................................................ 431
17.1 Block Diagram ........................................................................................................................ 431
17.2 Functional Description ............................................................................................................. 431
17.2.1 PWM Timer ............................................................................................................................. 431
17.2.2 PWM Comparators .................................................................................................................. 432
17.2.3 PWM Signal Generator ............................................................................................................ 433
17.2.4 Dead-Band Generator ............................................................................................................. 434
17.2.5 Interrupt Selector ..................................................................................................................... 434
17.2.6 Synchronization Methods ......................................................................................................... 434
17.2.7 Fault Conditions ...................................................................................................................... 435
17.2.8 Output Control Block ............................................................................................................... 435
17.3 Initialization and Configuration ................................................................................................. 435
17.4 Register Map .......................................................................................................................... 436
17.5 Register Descriptions .............................................................................................................. 437
18 Quadrature Encoder Interface (QEI) ............................................................................... 466
18.1 Block Diagram ........................................................................................................................ 466
18.2 Functional Description ............................................................................................................. 467
18.3 Initialization and Configuration ................................................................................................. 469
18.4 Register Map .......................................................................................................................... 469
Preliminary
November 30, 20076
LM3S6610 Microcontroller
18.5 Register Descriptions .............................................................................................................. 470
19 Pin Diagram ...................................................................................................................... 483
20 Signal Tables .................................................................................................................... 484
21 Operating Characteristics ............................................................................................... 499
22 Electrical Characteristics ................................................................................................ 500
22.1 DC Characteristics .................................................................................................................. 500
22.1.1 Maximum Ratings ................................................................................................................... 500
22.1.2 Recommended DC Operating Conditions .................................................................................. 500
22.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 501
22.1.4 Power Specifications ............................................................................................................... 501
22.1.5 Flash Memory Characteristics .................................................................................................. 503
22.2 AC Characteristics ................................................................................................................... 503
22.2.1 Load Conditions ...................................................................................................................... 503
22.2.2 Clocks .................................................................................................................................... 503
22.2.3 Analog Comparator ................................................................................................................. 504
22.2.4 I2C ......................................................................................................................................... 504
22.2.5 Ethernet Controller .................................................................................................................. 505
22.2.6 Hibernation Module ................................................................................................................. 508
22.2.7 Synchronous Serial Interface (SSI) ........................................................................................... 509
22.2.8 JTAG and Boundary Scan ........................................................................................................ 510
22.2.9 General-Purpose I/O ............................................................................................................... 512
22.2.10 Reset ..................................................................................................................................... 512
23 Package Information ........................................................................................................ 515
A Serial Flash Loader .......................................................................................................... 517
A.1 Serial Flash Loader ................................................................................................................. 517
A.2 Interfaces ............................................................................................................................... 517
A.2.1 UART ..................................................................................................................................... 517
A.2.2 SSI ......................................................................................................................................... 517
A.3 Packet Handling ...................................................................................................................... 518
A.3.1 Packet Format ........................................................................................................................ 518
A.3.2 Sending Packets ..................................................................................................................... 518
A.3.3 Receiving Packets ................................................................................................................... 518
A.4 Commands ............................................................................................................................. 519
A.4.1 COMMAND_PING (0X20) ........................................................................................................ 519
A.4.2 COMMAND_GET_STATUS (0x23) ........................................................................................... 519
A.4.3 COMMAND_DOWNLOAD (0x21) ............................................................................................. 519
A.4.4 COMMAND_SEND_DATA (0x24) ............................................................................................. 520
A.4.5 COMMAND_RUN (0x22) ......................................................................................................... 520
A.4.6 COMMAND_RESET (0x25) ..................................................................................................... 520
B Register Quick Reference ............................................................................................... 522
C Ordering and Contact Information ................................................................................. 539
C.1 Ordering Information ................................................................................................................ 539
C.2 Kits ......................................................................................................................................... 539
C.3 Company Information .............................................................................................................. 539
C.4 Support Information ................................................................................................................. 540
Preliminary
7November 30, 2007
Table of Contents
List of Figures
Figure 1-1. Stellaris®6000 Series High-Level Block Diagram ............................................................... 28
Figure 2-1. CPU Block Diagram ......................................................................................................... 36
Figure 2-2. TPIU Block Diagram ........................................................................................................ 37
Figure 5-1. JTAG Module Block Diagram ............................................................................................ 47
Figure 5-2. Test Access Port State Machine ....................................................................................... 50
Figure 5-3. IDCODE Register Format ................................................................................................. 55
Figure 5-4. BYPASS Register Format ................................................................................................ 56
Figure 5-5. Boundary Scan Register Format ....................................................................................... 56
Figure 6-1. External Circuitry to Extend Reset .................................................................................... 58
Figure 7-1. Hibernation Module Block Diagram ................................................................................. 119
Figure 8-1. Flash Block Diagram ...................................................................................................... 137
Figure 9-1. GPIO Port Block Diagram ............................................................................................... 162
Figure 9-2. GPIODATA Write Example ............................................................................................. 163
Figure 9-3. GPIODATA Read Example ............................................................................................. 163
Figure 10-1. GPTM Module Block Diagram ........................................................................................ 203
Figure 10-2. 16-Bit Input Edge Count Mode Example .......................................................................... 207
Figure 10-3. 16-Bit Input Edge Time Mode Example ........................................................................... 208
Figure 10-4. 16-Bit PWM Mode Example ............................................................................................ 209
Figure 11-1. WDT Module Block Diagram .......................................................................................... 238
Figure 12-1. UART Module Block Diagram ......................................................................................... 262
Figure 12-2. UART Character Frame ................................................................................................. 263
Figure 12-3. IrDA Data Modulation ..................................................................................................... 265
Figure 13-1. SSI Module Block Diagram ............................................................................................. 302
Figure 13-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 305
Figure 13-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 305
Figure 13-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 306
Figure 13-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 306
Figure 13-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 307
Figure 13-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 308
Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 308
Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 309
Figure 13-10. MICROWIRE Frame Format (Single Frame) .................................................................... 310
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 311
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 311
Figure 14-1. I2C Block Diagram ......................................................................................................... 339
Figure 14-2. I2C Bus Configuration .................................................................................................... 340
Figure 14-3. START and STOP Conditions ......................................................................................... 340
Figure 14-4. Complete Data Transfer with a 7-Bit Address ................................................................... 341
Figure 14-5. R/S Bit in First Byte ........................................................................................................ 341
Figure 14-6. Data Validity During Bit Transfer on the I2C Bus ............................................................... 341
Figure 14-7. Master Single SEND ...................................................................................................... 344
Figure 14-8. Master Single RECEIVE ................................................................................................. 345
Figure 14-9. Master Burst SEND ....................................................................................................... 346
Figure 14-10. Master Burst RECEIVE .................................................................................................. 347
Figure 14-11. Master Burst RECEIVE after Burst SEND ........................................................................ 348
Preliminary
November 30, 20078
LM3S6610 Microcontroller
Figure 14-12. Master Burst SEND after Burst RECEIVE ........................................................................ 349
Figure 14-13. Slave Command Sequence ............................................................................................ 350
Figure 15-1. Ethernet Controller Block Diagram .................................................................................. 375
Figure 15-2. Ethernet Controller ......................................................................................................... 375
Figure 15-3. Ethernet Frame ............................................................................................................. 377
Figure 16-1. Analog Comparator Module Block Diagram ..................................................................... 419
Figure 16-2. Structure of Comparator Unit .......................................................................................... 420
Figure 16-3. Comparator Internal Reference Structure ........................................................................ 421
Figure 17-1. PWM Module Block Diagram .......................................................................................... 431
Figure 17-2. PWM Count-Down Mode ................................................................................................ 432
Figure 17-3. PWM Count-Up/Down Mode .......................................................................................... 433
Figure 17-4. PWM Generation Example In Count-Up/Down Mode ....................................................... 433
Figure 17-5. PWM Dead-Band Generator ........................................................................................... 434
Figure 18-1. QEI Block Diagram ........................................................................................................ 466
Figure 18-2. Quadrature Encoder and Velocity Predivider Operation .................................................... 468
Figure 19-1. Pin Connection Diagram ................................................................................................ 483
Figure 22-1. Load Conditions ............................................................................................................ 503
Figure 22-2. I2C Timing ..................................................................................................................... 505
Figure 22-3. External XTLP Oscillator Characteristics ......................................................................... 508
Figure 22-4. Hibernation Module Timing ............................................................................................. 509
Figure 22-5. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 509
Figure 22-6. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 510
Figure 22-7. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 510
Figure 22-8. JTAG Test Clock Input Timing ......................................................................................... 511
Figure 22-9. JTAG Test Access Port (TAP) Timing .............................................................................. 512
Figure 22-10. JTAG TRST Timing ........................................................................................................ 512
Figure 22-11. External Reset Timing (RST) .......................................................................................... 513
Figure 22-12. Power-On Reset Timing ................................................................................................. 513
Figure 22-13. Brown-Out Reset Timing ................................................................................................ 513
Figure 22-14. Software Reset Timing ................................................................................................... 514
Figure 22-15. Watchdog Reset Timing ................................................................................................. 514
Figure 23-1. 100-Pin LQFP Package .................................................................................................. 515
Preliminary
9November 30, 2007
Table of Contents
List of Tables
Table 1. Documentation Conventions ............................................................................................ 19
Table 3-1. Memory Map ................................................................................................................... 41
Table 4-1. Exception Types .............................................................................................................. 43
Table 4-2. Interrupts ........................................................................................................................ 44
Table 5-1. JTAG Port Pins Reset State ............................................................................................. 48
Table 5-2. JTAG Instruction Register Commands ............................................................................... 53
Table 6-1. System Control Register Map ........................................................................................... 63
Table 7-1. Hibernation Module Register Map ................................................................................... 123
Table 8-1. Flash Protection Policy Combinations ............................................................................. 139
Table 8-2. Flash Resident Registers ............................................................................................... 140
Table 8-3. Flash Register Map ........................................................................................................ 140
Table 9-1. GPIO Pad Configuration Examples ................................................................................. 164
Table 9-2. GPIO Interrupt Configuration Example ............................................................................ 165
Table 9-3. GPIO Register Map ....................................................................................................... 166
Table 10-1. Available CCP Pins ........................................................................................................ 203
Table 10-2. 16-Bit Timer With Prescaler Configurations ..................................................................... 206
Table 10-3. Timers Register Map ...................................................................................................... 212
Table 11-1. Watchdog Timer Register Map ........................................................................................ 239
Table 12-1. UART Register Map ....................................................................................................... 267
Table 13-1. SSI Register Map .......................................................................................................... 312
Table 14-1. Examples of I2C Master Timer Period versus Speed Mode ............................................... 342
Table 14-2. Inter-Integrated Circuit (I2C) Interface Register Map ......................................................... 351
Table 14-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 356
Table 15-1. TX & RX FIFO Organization ........................................................................................... 378
Table 15-2. Ethernet Register Map ................................................................................................... 381
Table 16-1. Comparator 0 Operating Modes ...................................................................................... 420
Table 16-2. Comparator 1 Operating Modes ...................................................................................... 420
Table 16-3. Comparator 2 Operating Modes ...................................................................................... 421
Table 16-4. Internal Reference Voltage and ACREFCTL Field Values ................................................. 421
Table 16-5. Analog Comparators Register Map ................................................................................. 423
Table 17-1. PWM Register Map ........................................................................................................ 436
Table 18-1. QEI Register Map .......................................................................................................... 469
Table 20-1. Signals by Pin Number ................................................................................................... 484
Table 20-2. Signals by Signal Name ................................................................................................. 488
Table 20-3. Signals by Function, Except for GPIO ............................................................................. 493
Table 20-4. GPIO Pins and Alternate Functions ................................................................................. 497
Table 21-1. Temperature Characteristics ........................................................................................... 499
Table 21-2. Thermal Characteristics ................................................................................................. 499
Table 22-1. Maximum Ratings .......................................................................................................... 500
Table 22-2. Recommended DC Operating Conditions ........................................................................ 500
Table 22-3. LDO Regulator Characteristics ....................................................................................... 501
Table 22-4. Detailed Power Specifications ........................................................................................ 502
Table 22-5. Flash Memory Characteristics ........................................................................................ 503
Table 22-6. Phase Locked Loop (PLL) Characteristics ....................................................................... 503
Table 22-7. Clock Characteristics ..................................................................................................... 503
Table 22-8. Crystal Characteristics ................................................................................................... 504
Preliminary
November 30, 200710
LM3S6610 Microcontroller
Table 22-9. Analog Comparator Characteristics ................................................................................. 504
Table 22-10. Analog Comparator Voltage Reference Characteristics .................................................... 504
Table 22-11. I2C Characteristics ......................................................................................................... 504
Table 22-12. 100BASE-TX Transmitter Characteristics ........................................................................ 505
Table 22-13. 100BASE-TX Transmitter Characteristics (informative) ..................................................... 505
Table 22-14. 100BASE-TX Receiver Characteristics ............................................................................ 506
Table 22-15. 10BASE-T Transmitter Characteristics ............................................................................ 506
Table 22-16. 10BASE-T Transmitter Characteristics (informative) ......................................................... 506
Table 22-17. 10BASE-T Receiver Characteristics ................................................................................ 506
Table 22-18. Isolation Transformers ................................................................................................... 506
Table 22-19. Ethernet Reference Crystal ............................................................................................ 507
Table 22-20. External XTLP Oscillator Characteristics ......................................................................... 508
Table 22-21. Hibernation Module Characteristics ................................................................................. 508
Table 22-22. SSI Characteristics ........................................................................................................ 509
Table 22-23. JTAG Characteristics ..................................................................................................... 510
Table 22-24. GPIO Characteristics ..................................................................................................... 512
Table 22-25. Reset Characteristics ..................................................................................................... 512
Table C-1. Part Ordering Information ............................................................................................... 539
Preliminary
11November 30, 2007
Table of Contents
List of Registers
System Control .............................................................................................................................. 57
Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 65
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 67
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 68
Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 69
Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 70
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 71
Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 72
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 73
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 77
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 78
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 80
Register 12: Device Identification 1 (DID1), offset 0x004 ....................................................................... 81
Register 13: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 83
Register 14: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 84
Register 15: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 86
Register 16: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 88
Register 17: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 90
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 92
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 94
Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 96
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 .................................... 98
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 101
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 104
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 107
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 109
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 111
Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 113
Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 114
Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 116
Hibernation Module ..................................................................................................................... 118
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 125
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 126
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 127
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 128
Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 129
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 131
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 132
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 133
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 134
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 135
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 136
Internal Memory ........................................................................................................................... 137
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 142
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 143
Preliminary
November 30, 200712
LM3S6610 Microcontroller
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 144
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 146
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 147
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 148
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 149
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 150
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 151
Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 152
Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 153
Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 154
Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 155
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 156
Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 157
Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 158
Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 159
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 160
General-Purpose Input/Outputs (GPIOs) ................................................................................... 161
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 168
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 169
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 170
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 171
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 172
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 173
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 174
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 175
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 176
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 177
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 179
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 180
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 181
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 182
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 183
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 184
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 185
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 186
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 187
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 188
Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 190
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 191
Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 192
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 193
Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 194
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 195
Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 196
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 197
Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 198
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 199
Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 200
Preliminary
13November 30, 2007
Table of Contents
Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 201
General-Purpose Timers ............................................................................................................. 202
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 214
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 215
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 217
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 219
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 222
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 224
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 225
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 226
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 228
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 229
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 230
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 231
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 232
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 233
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 234
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 235
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 236
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 237
Watchdog Timer ........................................................................................................................... 238
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 241
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 242
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 243
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 244
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 245
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 246
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 247
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 248
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 249
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 250
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 251
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 252
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 253
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 254
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 255
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 256
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 257
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 258
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 259
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 260
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 261
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 269
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 271
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 273
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 275
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 276
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 277
Preliminary
November 30, 200714
LM3S6610 Microcontroller
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 278
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 280
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 282
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 284
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 286
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 287
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 288
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 290
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 291
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 292
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 293
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 294
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 295
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 296
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 297
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 298
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 299
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 300
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 301
Synchronous Serial Interface (SSI) ............................................................................................ 302
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 314
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 316
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 318
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 319
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 321
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 322
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 324
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 325
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 326
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 327
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 328
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 329
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 330
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 331
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 332
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 333
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 334
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 335
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 336
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 337
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 338
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 339
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 353
Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 354
Register 3: I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 358
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 359
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 360
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 361
Preliminary
15November 30, 2007
Table of Contents
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 362
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 363
Register 9: I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 364
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 366
Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 367
Register 12: I2C Slave Data (I2CSDR), offset 0x008 ........................................................................... 369
Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 370
Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 371
Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 372
Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 373
Ethernet Controller ...................................................................................................................... 374
Register 1: Ethernet MAC Raw Interrupt Status (MACRIS), offset 0x000 ............................................ 383
Register 2: Ethernet MAC Interrupt Acknowledge (MACIACK), offset 0x000 ....................................... 385
Register 3: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... 386
Register 4: Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ 387
Register 5: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... 388
Register 6: Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. 389
Register 7: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 391
Register 8: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. 392
Register 9: Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... 393
Register 10: Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ 394
Register 11: Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 395
Register 12: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 396
Register 13: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. 397
Register 14: Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... 398
Register 15: Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... 399
Register 16: Ethernet PHY Management Register 0 – Control (MR0), address 0x00 ............................. 400
Register 17: Ethernet PHY Management Register 1 – Status (MR1), address 0x01 .............................. 402
Register 18: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 ................. 404
Register 19: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 ................. 405
Register 20: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address
0x04 ............................................................................................................................. 406
Register 21: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability
(MR5), address 0x05 ..................................................................................................... 408
Register 22: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address
0x06 ............................................................................................................................. 409
Register 23: Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 ............. 410
Register 24: Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address
0x11 .............................................................................................................................. 412
Register 25: Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12 ..................... 414
Register 26: Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13 ....... 415
Register 27: Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17 ......... 416
Register 28: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), address 0x18 .......... 417
Analog Comparators ................................................................................................................... 418
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 424
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 425
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 426
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 427
Preliminary
November 30, 200716
LM3S6610 Microcontroller
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 428
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40 ....................................................... 428
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x60 ....................................................... 428
Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 429
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x44 ....................................................... 429
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x64 ...................................................... 429
Pulse Width Modulator (PWM) .................................................................................................... 431
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 438
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 439
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 440
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 441
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 442
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 443
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 444
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 445
Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 446
Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 447
Register 11: PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 447
Register 12: PWM0 Interrupt Enable (PWM0INTEN), offset 0x044 ...................................................... 449
Register 13: PWM1 Interrupt Enable (PWM1INTEN), offset 0x084 ...................................................... 449
Register 14: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 451
Register 15: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 .................................................... 451
Register 16: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 452
Register 17: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ........................................... 452
Register 18: PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 453
Register 19: PWM1 Load (PWM1LOAD), offset 0x090 ....................................................................... 453
Register 20: PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 454
Register 21: PWM1 Counter (PWM1COUNT), offset 0x094 ................................................................ 454
Register 22: PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 455
Register 23: PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................. 455
Register 24: PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 456
Register 25: PWM1 Compare B (PWM1CMPB), offset 0x09C ............................................................. 456
Register 26: PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 457
Register 27: PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ................................................ 457
Register 28: PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 460
Register 29: PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ................................................ 460
Register 30: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 463
Register 31: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ................................................. 463
Register 32: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 464
Register 33: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ............................. 464
Register 34: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 465
Register 35: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ............................. 465
Quadrature Encoder Interface (QEI) .......................................................................................... 466
Register 1: QEI Control (QEICTL), offset 0x000 ................................................................................ 471
Register 2: QEI Status (QEISTAT), offset 0x004 ................................................................................ 473
Register 3: QEI Position (QEIPOS), offset 0x008 .............................................................................. 474
Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C ....................................................... 475
Register 5: QEI Timer Load (QEILOAD), offset 0x010 ....................................................................... 476
Preliminary
17November 30, 2007
Table of Contents
Register 6: QEI Timer (QEITIME), offset 0x014 ................................................................................. 477
Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018 ............................................................. 478
Register 8: QEI Velocity (QEISPEED), offset 0x01C .......................................................................... 479
Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020 ............................................................... 480
Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024 ............................................................. 481
Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028 ..................................................... 482
Preliminary
November 30, 200718
About This Document
This data sheet provides reference information for the LM3S6610 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following documents are referenced by the data sheet, and available on the documentation CD
or from the Luminary Micro web site at www.luminarymicro.com:
■
ARM® Cortex™-M3 Technical Reference Manual
LM3S6610 Microcontroller
■
ARM® CoreSight Technical Reference Manual
■
ARM® v7-M Architecture Application Level Reference Manual
The following related documents are also referenced:
■
IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the Luminary Micro web
site for additional documentation, including application notes and white papers.
Documentation Conventions
This document uses the conventions shown in Table 1 on page 19.
Table 1. Documentation Conventions
MeaningNotation
General Register Notation
REGISTER
offset 0xnnn
Register N
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
A single bit in a register.bit
Two or more consecutive and related bits.bit field
A hexadecimal increment to a register's address, relative to that module's base address as specified
in “Memory Map” on page 41.
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
Preliminary
19November 30, 2007
About This Document
reserved
yy:xx
Register Bit/Field
Types
R/W1C
W1C
Reset Value
Pin/Signal Notation
assert a signal
SIGNAL
SIGNAL
Numbers
X
0x
MeaningNotation
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.RC
Software can read this field. Always write the chip reset value.RO
Software can read or write this field.R/W
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
Only a write by software is valid; a read of the register returns no meaningful data.WO
This value in the register bit diagram shows the bit/field value after any reset, unless noted.Register Bit/Field
Bit cleared to 0 on chip reset.0
Bit set to 1 on chip reset.1
Nondeterministic.-
Pin alternate function; a pin defaults to the signal without the brackets.[ ]
Refers to the physical connection on the package.pin
Refers to the electrical signal encoding of a pin.signal
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
Change the value of the signal from the logically True state to the logically False state.deassert a signal
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
Preliminary
November 30, 200720
1 Architectural Overview
The Luminary Micro Stellaris®family of microcontrollers—the first ARM® Cortex™-M3 based
controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller
applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to
legacy 8- and 16-bit devices, all in a package with a small footprint.
The Stellaris®family offers efficient performance and extensive integration, favorably positioning
the device into cost-conscious applications requiring significant control-processing and connectivity
capabilities. The Stellaris®LM3S1000 series extends the Stellaris®family with larger on-chip
memories, enhanced power management, and expanded I/O and control capabilities. The Stellaris
LM3S2000 series, designed for Controller Area Network (CAN) applications, extends the Stellaris
family with Bosch CAN networking technology, the golden standard in short-haul industrial networks.
The Stellaris®LM3S2000 series also marks the first integration of CAN capabilities with the
revolutionary Cortex-M3 core. The Stellaris®LM3S6000 series combines both a 10/100 Ethernet
Media Access Control (MAC) and Physical (PHY) layer, marking the first time that integrated
connectivity is available with an ARM Cortex-M3 MCU and the only integrated 10/100 Ethernet MAC
and PHY available in an ARM architecture MCU. The Stellaris®LM3S8000 series combines Bosch
Controller Area Network technology with both a 10/100 Ethernet Media Access Control (MAC) and
Physical (PHY) layer.
LM3S6610 Microcontroller
®
The LM3S6610 microcontroller is targeted for industrial applications, including remote monitoring,
electronic point-of-sale machines, test and measurement equipment, network appliances and
switches, factory automation, HVAC and building control, gaming equipment, motion control, medical
instrumentation, and fire and security.
For applications requiring extreme conservation of power, the LM3S6610 microcontroller features
a Battery-backed Hibernation module to efficiently power down the LM3S6610 to a low-power state
during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time
counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated
non-volatile memory, the Hibernation module positions the LM3S6610 microcontroller perfectly for
battery applications.
In addition, the LM3S6610 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S6610 microcontroller is code-compatible
to all members of the extensive Stellaris®family; providing flexibility to fit our customers' precise
needs.
Luminary Micro offers a complete solution to get to market quickly, with evaluation and development
boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong
support, sales, and distributor network.
1.1 Product Features
The LM3S6610 microcontroller includes the following product features:
■ 32-Bit RISC Performance
– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
Preliminary
21November 30, 2007
Architectural Overview
– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
– Thumb®-compatible Thumb-2-only instruction set processor core for high code density
– 25-MHz operation
– Hardware-division and single-cycle-multiplication
– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
– 32 interrupts with eight priority levels
– Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
– Unaligned data access, enabling data to be efficiently packed into memory
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
■ Internal Memory
– 128 KB single-cycle flash
• User-managed flash block protection on a 2-KB block basis
• User-managed flash data programming
• User-defined and managed flash-protection block
– 32 KB single-cycle SRAM
■ General-Purpose Timers
– Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers.
Each GPTM can be configured to operate independently:
• As a single 32-bit timer
• As one 32-bit Real-Time Clock (RTC) to event capture
• For Pulse Width Modulation (PWM)
– 32-bit Timer modes
• Programmable one-shot timer
• Programmable periodic timer
• Real-Time Clock when using an external 32.768-KHz clock as the input
• User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU
Halt flag during debug
November 30, 200722
Preliminary
LM3S6610 Microcontroller
– 16-bit Timer modes
• General-purpose timer function with an 8-bit prescaler
• Programmable one-shot timer
• Programmable periodic timer
• User-enabled stalling when the controller asserts CPU Halt flag during debug
– 16-bit Input Capture modes
• Input edge count capture
• Input edge time capture
– 16-bit PWM mode
• Simple PWM mode with software-programmable output inversion of the PWM signal
■ ARM FiRM-compliant Watchdog Timer
– 32-bit down counter with a programmable load register
– Separate watchdog clock with an enable
– Programmable interrupt generation logic with interrupt masking
– Lock register protection from runaway software
– Reset generation logic with an enable/disable
– User-enabled stalling when the controller asserts the CPU Halt flag during debug
■ 10/100 Ethernet Controller
– Conforms to the IEEE 802.3-2002 Specification
– Full- and half-duplex for both 100 Mbps and 10 Mbps operation
– Integrated 10/100 Mbps Transceiver (PHY)
– Automatic MDI/MDI-X cross-over correction
– Programmable MAC address
– Power-saving and power-down modes
■ Synchronous Serial Interface (SSI)
– Master or slave operation
– Programmable clock bit rate and prescale
– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
Preliminary
23November 30, 2007
Architectural Overview
– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
– Programmable data frame size from 4 to 16 bits
– Internal loopback test mode for diagnostic/debug testing
■ UART
– Three fully programmable 16C550-type UARTs with IrDA support
– Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service
loading
– Programmable baud-rate generator with fractional divider
– Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
– Standard asynchronous communication bits for start, stop, and parity
– False-start-bit detection
– Line-break generation and detection
■ Analog Comparators
– Three independent integrated analog comparators
– Configurable for output to: drive an output pin or generate an interrupt
– Compare external pin input to external pin input or to internal programmable voltage reference
■ I2C
– Master and slave receive and transmit operation with transmission speed up to 100 Kbps in
Standard mode and 400 Kbps in Fast mode
– Interrupt generation
– Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
■ PWM
– Two PWM generator blocks, each with one 16-bit counter, two comparators, a PWM generator,
and a dead-band generator
– One 16-bit counter
• Runs in Down or Up/Down mode
• Output frequency controlled by a 16-bit load value
Preliminary
November 30, 200724
LM3S6610 Microcontroller
• Load value updates can be synchronized
• Produces output signals at zero and load value
– Two PWM comparators
• Comparator value updates can be synchronized
• Produces output signals on match
– PWM generator
• Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals
• Produces two independent PWM signals
– Dead-band generator
• Produces two PWM signals with programmable dead-band delays suitable for driving a
half-H bridge
• Can be bypassed, leaving input PWM signals unmodified
– Flexible output control block with PWM output enable of each PWM signal
• PWM output enable of each PWM signal
• Optional output inversion of each PWM signal (polarity control)
• Optional fault handling for each PWM signal
• Synchronization of timers in the PWM generator blocks
• Synchronization of timer/comparator updates across the PWM generator blocks
• Interrupt status summary of the PWM generator blocks
■ QEI
– Hardware position integrator tracks the encoder position
– Velocity capture using built-in timer
– Interrupt generation on index pulse, velocity-timer expiration, direction change, and quadrature
error detection
■ GPIOs
– 5-46 GPIOs, depending on configuration
– 5-V-tolerant input/outputs
– Programmable interrupt generation as either edge-triggered or level-sensitive
– Bit masking in both read and write operations through address lines
Preliminary
25November 30, 2007
Architectural Overview
– Programmable control for GPIO pad configuration:
• Weak pull-up or pull-down resistors
• 2-mA, 4-mA, and 8-mA pad drive
• Slew rate control for the 8-mA drive
• Open drain enables
• Digital input enables
■ Power
– On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
– Hibernation module handles the power-up/down 3.3 V sequencing and control for the core
digital logic and analog circuits
– Low-power options on controller: Sleep and Deep-sleep modes
– Low-power options for peripherals: software controls shutdown of individual peripherals
– User-enabled LDO unregulated voltage detection and automatic reset
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Flexible Reset Sources
– Power-on reset (POR)
– Reset pin assertion
– Brown-out (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
– Internal low drop-out (LDO) regulator output goes unregulated
■ Additional Features
– Six reset sources
– Programmable clock source control
– Clock gating to individual peripherals for power savings
– IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
– Debug access via JTAG and Serial Wire interfaces
– Full JTAG boundary scan
■ Industrial-range 100-pin RoHS-compliant LQFP package
Preliminary
November 30, 200726
1.2 Target Applications
■ Remote monitoring
■ Electronic point-of-sale (POS) machines
■ Test and measurement equipment
■ Network appliances and switches
■ Factory automation
■ HVAC and building control
■ Gaming equipment
■ Motion control
■ Medical instrumentation
■ Fire and security
LM3S6610 Microcontroller
■ Power and energy
■ Transportation
1.3 High-Level Block Diagram
Figure 1-1 on page 28 represents the full set of features in the Stellaris®6000 series of devices;
not all features may be available on the LM3S6610 microcontroller.
Preliminary
27November 30, 2007
Architectural Overview
Figure 1-1. Stellaris®6000 Series High-Level Block Diagram
1.4 Functional Overview
The following sections provide an overview of the features of the LM3S6610 microcontroller. The
page number in parenthesis indicates where that feature is discussed in detail. Ordering and support
information can be found in “Ordering and Contact Information” on page 539.
November 30, 200728
Preliminary
1.4.1 ARM Cortex™-M3
1.4.1.1 Processor Core (see page 35)
All members of the Stellaris®product family, including the LM3S6610 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
“ARM Cortex-M3 Processor Core” on page 35 provides an overview of the ARM core; the core is
detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.1.2 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
LM3S6610 Microcontroller
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
1.4.1.3 Nested Vectored Interrupt Controller (NVIC)
The LM3S6610 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the
ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions
are handled in Handler Mode. The processor state is automatically stored to the stack on an
exception, and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed without
the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions
(system handlers) and 32 interrupts.
“Interrupts” on page 43 provides an overview of the NVIC controller and the interrupt map. Exceptions
and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.2 Motor Control Peripherals
To enhance motor control, the LM3S6610 controller features Pulse Width Modulation (PWM) outputs
and the Quadrature Encoder Interface (QEI).
1.4.2.1 PWM
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
29November 30, 2007
Preliminary
Architectural Overview
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
On the LM3S6610, PWM motion control functionality can be achieved through:
■ Dedicated, flexible motion control hardware using the PWM pins
■ The motion control features of the general-purpose timers using the CCP pins
PWM Pins (see page 431)
The LM3S6610 PWM module consists of two PWM generator blocks and a control block. Each
PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a
PWM signal generator, a dead-band generator, and an interrupt. The control block determines the
polarity of the PWM signals, and which signals are passed through to the pins.
Each PWM generator block produces two PWM signals that can either be independent signals or
a single pair of complementary signals with dead-band delays inserted. The output of the PWM
generation blocks are managed by the output control block before being passed to the device pins.
CCP Pins (see page 208)
The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable
to support a simple PWM mode with a software-programmable output inversion of the PWM signal.
1.4.2.2 QEI (see page 466)
A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement
into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals,
you can track the position, direction of rotation, and speed. In addition, a third channel, or index
signal, can be used to reset the position counter.
The Stellaris quadrature encoder with index (QEI) module interprets the code produced by a
quadrature encoder wheel to integrate position over time and determine direction of rotation. In
addition, it can capture a running estimate of the velocity of the encoder wheel.
1.4.3 Analog Peripherals
For support of analog signals, the LM3S6610 microcontroller offers three analog comparators.
1.4.3.1 Analog Comparators (see page 418)
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
The LM3S6610 microcontroller provides three independent integrated analog comparators that can
be configured to drive an output or generate an interrupt .
A comparator can compare a test voltage against any one of these voltages:
■ An individual external reference voltage
■ A shared single external reference voltage
■ A shared internal reference voltage
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts to cause it to start
capturing a sample sequence.
November 30, 200730
Preliminary
Loading...