TEXAS INSTRUMENTS LM3S6432 Technical data
PRELIMINARY
LM3S6432 Microcontroller
DATA SHEET
Copyright © 2007 Luminary Micro, Inc.DS-LM3S6432-1972
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Preliminary
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LM3S6432 Microcontroller
Table of Contents
About This Document .................................................................................................................... 18
Audience .............................................................................................................................................. 18
About This Manual ................................................................................................................................ 18
Related Documents ............................................................................................................................... 18
Documentation Conventions .................................................................................................................. 18
1 Architectural Overview ...................................................................................................... 20
1.1 Product Features ...................................................................................................................... 20
1.2 Target Applications .................................................................................................................... 26
1.3 High-Level Block Diagram ......................................................................................................... 26
1.4 Functional Overview .................................................................................................................. 27
1.4.1 ARM Cortex™-M3 ..................................................................................................................... 28
1.4.2 Motor Control Peripherals .......................................................................................................... 28
1.4.3 Analog Peripherals .................................................................................................................... 29
1.4.4 Serial Communications Peripherals ............................................................................................ 30
1.4.5 System Peripherals ................................................................................................................... 31
1.4.6 Memory Peripherals .................................................................................................................. 32
1.4.7 Additional Features ................................................................................................................... 32
1.4.8 Hardware Details ...................................................................................................................... 33
2 ARM Cortex-M3 Processor Core ...................................................................................... 34
2.1 Block Diagram .......................................................................................................................... 35
2.2 Functional Description ............................................................................................................... 35
2.2.1 Serial Wire and JTAG Debug ..................................................................................................... 35
2.2.2 Embedded Trace Macrocell (ETM) ............................................................................................. 36
2.2.3 Trace Port Interface Unit (TPIU) ................................................................................................. 36
2.2.4 ROM Table ............................................................................................................................... 36
2.2.5 Memory Protection Unit (MPU) ................................................................................................... 36
2.2.6 Nested Vectored Interrupt Controller (NVIC) ................................................................................ 36
3 Memory Map ....................................................................................................................... 40
4 Interrupts ............................................................................................................................ 42
5 JTAG Interface .................................................................................................................... 44
5.1 Block Diagram .......................................................................................................................... 45
5.2 Functional Description ............................................................................................................... 45
5.2.1 JTAG Interface Pins .................................................................................................................. 46
5.2.2 JTAG TAP Controller ................................................................................................................. 47
5.2.3 Shift Registers .......................................................................................................................... 48
5.2.4 Operational Considerations ........................................................................................................ 48
5.3 Initialization and Configuration ................................................................................................... 51
5.4 Register Descriptions ................................................................................................................ 51
5.4.1 Instruction Register (IR) ............................................................................................................. 51
5.4.2 Data Registers .......................................................................................................................... 53
6 System Control ................................................................................................................... 55
6.1 Functional Description ............................................................................................................... 55
6.1.1 Device Identification .................................................................................................................. 55
6.1.2 Reset Control ............................................................................................................................ 55
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Table of Contents
6.1.3 Power Control ........................................................................................................................... 58
6.1.4 Clock Control ............................................................................................................................ 58
6.1.5 System Control ......................................................................................................................... 60
6.2 Initialization and Configuration ................................................................................................... 60
6.3 Register Map ............................................................................................................................ 61
6.4 Register Descriptions ................................................................................................................ 62
7 Internal Memory ............................................................................................................... 113
7.1 Block Diagram ........................................................................................................................ 113
7.2 Functional Description ............................................................................................................. 113
7.2.1 SRAM Memory ........................................................................................................................ 113
7.2.2 Flash Memory ......................................................................................................................... 114
7.3 Flash Memory Initialization and Configuration ........................................................................... 115
7.3.1 Flash Programming ................................................................................................................. 115
7.3.2 Nonvolatile Register Programming ........................................................................................... 116
7.4 Register Map .......................................................................................................................... 116
7.5 Flash Register Descriptions (Flash Control Offset) ..................................................................... 117
7.6 Flash Register Descriptions (System Control Offset) .................................................................. 124
8 General-Purpose Input/Outputs (GPIOs) ....................................................................... 137
8.1 Functional Description ............................................................................................................. 137
8.1.1 Data Control ........................................................................................................................... 138
8.1.2 Interrupt Control ...................................................................................................................... 139
8.1.3 Mode Control .......................................................................................................................... 140
8.1.4 Commit Control ....................................................................................................................... 140
8.1.5 Pad Control ............................................................................................................................. 140
8.1.6 Identification ........................................................................................................................... 140
8.2 Initialization and Configuration ................................................................................................. 140
8.3 Register Map .......................................................................................................................... 142
8.4 Register Descriptions .............................................................................................................. 143
9 General-Purpose Timers ................................................................................................. 178
9.1 Block Diagram ........................................................................................................................ 178
9.2 Functional Description ............................................................................................................. 179
9.2.1 GPTM Reset Conditions .......................................................................................................... 179
9.2.2 32-Bit Timer Operating Modes .................................................................................................. 180
9.2.3 16-Bit Timer Operating Modes .................................................................................................. 181
9.3 Initialization and Configuration ................................................................................................. 185
9.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 185
9.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 186
9.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 186
9.3.4 16-Bit Input Edge Count Mode ................................................................................................. 187
9.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 187
9.3.6 16-Bit PWM Mode ................................................................................................................... 188
9.4 Register Map .......................................................................................................................... 188
9.5 Register Descriptions .............................................................................................................. 189
10 Watchdog Timer ............................................................................................................... 214
10.1 Block Diagram ........................................................................................................................ 214
10.2 Functional Description ............................................................................................................. 214
10.3 Initialization and Configuration ................................................................................................. 215
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10.4 Register Map .......................................................................................................................... 215
10.5 Register Descriptions .............................................................................................................. 216
11 Analog-to-Digital Converter (ADC) ................................................................................. 237
11.1 Block Diagram ........................................................................................................................ 238
11.2 Functional Description ............................................................................................................. 238
11.2.1 Sample Sequencers ................................................................................................................ 238
11.2.2 Module Control ........................................................................................................................ 239
11.2.3 Hardware Sample Averaging Circuit ......................................................................................... 240
11.2.4 Analog-to-Digital Converter ...................................................................................................... 240
11.2.5 Test Modes ............................................................................................................................. 240
11.2.6 Internal Temperature Sensor .................................................................................................... 240
11.3 Initialization and Configuration ................................................................................................. 241
11.3.1 Module Initialization ................................................................................................................. 241
11.3.2 Sample Sequencer Configuration ............................................................................................. 241
11.4 Register Map .......................................................................................................................... 242
11.5 Register Descriptions .............................................................................................................. 243
12 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 270
12.1 Block Diagram ........................................................................................................................ 271
12.2 Functional Description ............................................................................................................. 271
12.2.1 Transmit/Receive Logic ........................................................................................................... 271
12.2.2 Baud-Rate Generation ............................................................................................................. 272
12.2.3 Data Transmission .................................................................................................................. 273
12.2.4 Serial IR (SIR) ......................................................................................................................... 273
12.2.5 FIFO Operation ....................................................................................................................... 274
12.2.6 Interrupts ................................................................................................................................ 274
12.2.7 Loopback Operation ................................................................................................................ 275
12.2.8 IrDA SIR block ........................................................................................................................ 275
12.3 Initialization and Configuration ................................................................................................. 275
12.4 Register Map .......................................................................................................................... 276
12.5 Register Descriptions .............................................................................................................. 277
13 Synchronous Serial Interface (SSI) ................................................................................ 311
13.1 Block Diagram ........................................................................................................................ 311
13.2 Functional Description ............................................................................................................. 311
13.2.1 Bit Rate Generation ................................................................................................................. 312
13.2.2 FIFO Operation ....................................................................................................................... 312
13.2.3 Interrupts ................................................................................................................................ 312
13.2.4 Frame Formats ....................................................................................................................... 313
13.3 Initialization and Configuration ................................................................................................. 320
13.4 Register Map .......................................................................................................................... 321
13.5 Register Descriptions .............................................................................................................. 322
14 Inter-Integrated Circuit (I2C) Interface ............................................................................ 348
14.1 Block Diagram ........................................................................................................................ 348
14.2 Functional Description ............................................................................................................. 348
14.2.1 I2C Bus Functional Overview .................................................................................................... 349
14.2.2 Available Speed Modes ........................................................................................................... 351
14.2.3 Interrupts ................................................................................................................................ 352
14.2.4 Loopback Operation ................................................................................................................ 352
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5November 30, 2007
Table of Contents
14.2.5 Command Sequence Flow Charts ............................................................................................ 353
14.3 Initialization and Configuration ................................................................................................. 359
14.4 I2C Register Map ..................................................................................................................... 360
14.5 Register Descriptions (I2C Master) ........................................................................................... 361
14.6 Register Descriptions (I2C Slave) ............................................................................................. 374
15 Ethernet Controller .......................................................................................................... 383
15.1 Block Diagram ........................................................................................................................ 384
15.2 Functional Description ............................................................................................................. 384
15.2.1 Internal MII Operation .............................................................................................................. 384
15.2.2 PHY Configuration/Operation ................................................................................................... 385
15.2.3 MAC Configuration/Operation .................................................................................................. 386
15.2.4 Interrupts ................................................................................................................................ 388
15.3 Initialization and Configuration ................................................................................................. 389
15.4 Ethernet Register Map ............................................................................................................. 389
15.5 Ethernet MAC Register Descriptions ......................................................................................... 391
15.6 MII Management Register Descriptions ..................................................................................... 408
16 Analog Comparators ....................................................................................................... 427
16.1 Block Diagram ........................................................................................................................ 427
16.2 Functional Description ............................................................................................................. 428
16.2.1 Internal Reference Programming .............................................................................................. 429
16.3 Initialization and Configuration ................................................................................................. 430
16.4 Register Map .......................................................................................................................... 430
16.5 Register Descriptions .............................................................................................................. 431
17 Pulse Width Modulator (PWM) ........................................................................................ 439
17.1 Block Diagram ........................................................................................................................ 439
17.2 Functional Description ............................................................................................................. 439
17.2.1 PWM Timer ............................................................................................................................. 439
17.2.2 PWM Comparators .................................................................................................................. 440
17.2.3 PWM Signal Generator ............................................................................................................ 441
17.2.4 Dead-Band Generator ............................................................................................................. 442
17.2.5 Interrupt/ADC-Trigger Selector ................................................................................................. 442
17.2.6 Synchronization Methods ......................................................................................................... 442
17.2.7 Fault Conditions ...................................................................................................................... 443
17.2.8 Output Control Block ............................................................................................................... 443
17.3 Initialization and Configuration ................................................................................................. 443
17.4 Register Map .......................................................................................................................... 444
17.5 Register Descriptions .............................................................................................................. 445
18 Pin Diagram ...................................................................................................................... 474
19 Signal Tables .................................................................................................................... 475
20 Operating Characteristics ............................................................................................... 487
21 Electrical Characteristics ................................................................................................ 488
21.1 DC Characteristics .................................................................................................................. 488
21.1.1 Maximum Ratings ................................................................................................................... 488
21.1.2 Recommended DC Operating Conditions .................................................................................. 488
21.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 489
21.1.4 Power Specifications ............................................................................................................... 489
Preliminary
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21.1.5 Flash Memory Characteristics .................................................................................................. 490
21.2 AC Characteristics ................................................................................................................... 491
21.2.1 Load Conditions ...................................................................................................................... 491
21.2.2 Clocks .................................................................................................................................... 491
21.2.3 Analog-to-Digital Converter ...................................................................................................... 492
21.2.4 Analog Comparator ................................................................................................................. 492
21.2.5 I2C ......................................................................................................................................... 493
21.2.6 Ethernet Controller .................................................................................................................. 493
21.2.7 Synchronous Serial Interface (SSI) ........................................................................................... 496
21.2.8 JTAG and Boundary Scan ........................................................................................................ 498
21.2.9 General-Purpose I/O ............................................................................................................... 499
21.2.10 Reset ..................................................................................................................................... 500
22 Package Information ........................................................................................................ 502
A Serial Flash Loader .......................................................................................................... 504
A.1 Serial Flash Loader ................................................................................................................. 504
A.2 Interfaces ............................................................................................................................... 504
A.2.1 UART ..................................................................................................................................... 504
A.2.2 SSI ......................................................................................................................................... 504
A.3 Packet Handling ...................................................................................................................... 505
A.3.1 Packet Format ........................................................................................................................ 505
A.3.2 Sending Packets ..................................................................................................................... 505
A.3.3 Receiving Packets ................................................................................................................... 505
A.4 Commands ............................................................................................................................. 506
A.4.1 COMMAND_PING (0X20) ........................................................................................................ 506
A.4.2 COMMAND_GET_STATUS (0x23) ........................................................................................... 506
A.4.3 COMMAND_DOWNLOAD (0x21) ............................................................................................. 506
A.4.4 COMMAND_SEND_DATA (0x24) ............................................................................................. 507
A.4.5 COMMAND_RUN (0x22) ......................................................................................................... 507
A.4.6 COMMAND_RESET (0x25) ..................................................................................................... 507
B Register Quick Reference ............................................................................................... 509
C Ordering and Contact Information ................................................................................. 526
C.1 Ordering Information ................................................................................................................ 526
C.2 Kits ......................................................................................................................................... 526
C.3 Company Information .............................................................................................................. 526
C.4 Support Information ................................................................................................................. 527
Preliminary
7November 30, 2007
Table of Contents
List of Figures
Figure 1-1. Stellaris®6000 Series High-Level Block Diagram ............................................................... 27
Figure 2-1. CPU Block Diagram ......................................................................................................... 35
Figure 2-2. TPIU Block Diagram ........................................................................................................ 36
Figure 5-1. JTAG Module Block Diagram ............................................................................................ 45
Figure 5-2. Test Access Port State Machine ....................................................................................... 48
Figure 5-3. IDCODE Register Format ................................................................................................. 53
Figure 5-4. BYPASS Register Format ................................................................................................ 54
Figure 5-5. Boundary Scan Register Format ....................................................................................... 54
Figure 6-1. External Circuitry to Extend Reset .................................................................................... 56
Figure 7-1. Flash Block Diagram ...................................................................................................... 113
Figure 8-1. GPIO Port Block Diagram ............................................................................................... 138
Figure 8-2. GPIODATA Write Example ............................................................................................. 139
Figure 8-3. GPIODATA Read Example ............................................................................................. 139
Figure 9-1. GPTM Module Block Diagram ........................................................................................ 179
Figure 9-2. 16-Bit Input Edge Count Mode Example .......................................................................... 183
Figure 9-3. 16-Bit Input Edge Time Mode Example ........................................................................... 184
Figure 9-4. 16-Bit PWM Mode Example ............................................................................................ 185
Figure 10-1. WDT Module Block Diagram .......................................................................................... 214
Figure 11-1. ADC Module Block Diagram ........................................................................................... 238
Figure 11-2. Internal Temperature Sensor Characteristic ..................................................................... 241
Figure 12-1. UART Module Block Diagram ......................................................................................... 271
Figure 12-2. UART Character Frame ................................................................................................. 272
Figure 12-3. IrDA Data Modulation ..................................................................................................... 274
Figure 13-1. SSI Module Block Diagram ............................................................................................. 311
Figure 13-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 313
Figure 13-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 314
Figure 13-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 315
Figure 13-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 315
Figure 13-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 316
Figure 13-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 317
Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 317
Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 318
Figure 13-10. MICROWIRE Frame Format (Single Frame) .................................................................... 319
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 320
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 320
Figure 14-1. I2C Block Diagram ......................................................................................................... 348
Figure 14-2. I2C Bus Configuration .................................................................................................... 349
Figure 14-3. START and STOP Conditions ......................................................................................... 349
Figure 14-4. Complete Data Transfer with a 7-Bit Address ................................................................... 350
Figure 14-5. R/S Bit in First Byte ........................................................................................................ 350
Figure 14-6. Data Validity During Bit Transfer on the I2C Bus ............................................................... 350
Figure 14-7. Master Single SEND ...................................................................................................... 353
Figure 14-8. Master Single RECEIVE ................................................................................................. 354
Figure 14-9. Master Burst SEND ....................................................................................................... 355
Figure 14-10. Master Burst RECEIVE .................................................................................................. 356
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LM3S6432 Microcontroller
Figure 14-11. Master Burst RECEIVE after Burst SEND ........................................................................ 357
Figure 14-12. Master Burst SEND after Burst RECEIVE ........................................................................ 358
Figure 14-13. Slave Command Sequence ............................................................................................ 359
Figure 15-1. Ethernet Controller Block Diagram .................................................................................. 384
Figure 15-2. Ethernet Controller ......................................................................................................... 384
Figure 15-3. Ethernet Frame ............................................................................................................. 386
Figure 16-1. Analog Comparator Module Block Diagram ..................................................................... 427
Figure 16-2. Structure of Comparator Unit .......................................................................................... 428
Figure 16-3. Comparator Internal Reference Structure ........................................................................ 429
Figure 17-1. PWM Module Block Diagram .......................................................................................... 439
Figure 17-2. PWM Count-Down Mode ................................................................................................ 440
Figure 17-3. PWM Count-Up/Down Mode .......................................................................................... 441
Figure 17-4. PWM Generation Example In Count-Up/Down Mode ....................................................... 441
Figure 17-5. PWM Dead-Band Generator ........................................................................................... 442
Figure 18-1. Pin Connection Diagram ................................................................................................ 474
Figure 21-1. Load Conditions ............................................................................................................ 491
Figure 21-2. I2C Timing ..................................................................................................................... 493
Figure 21-3. External XTLP Oscillator Characteristics ......................................................................... 496
Figure 21-4. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 497
Figure 21-5. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 497
Figure 21-6. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 498
Figure 21-7. JTAG Test Clock Input Timing ......................................................................................... 499
Figure 21-8. JTAG Test Access Port (TAP) Timing .............................................................................. 499
Figure 21-9. JTAG TRST Timing ........................................................................................................ 499
Figure 21-10. External Reset Timing (RST) .......................................................................................... 500
Figure 21-11. Power-On Reset Timing ................................................................................................. 501
Figure 21-12. Brown-Out Reset Timing ................................................................................................ 501
Figure 21-13. Software Reset Timing ................................................................................................... 501
Figure 21-14. Watchdog Reset Timing ................................................................................................. 501
Figure 22-1. 100-Pin LQFP Package .................................................................................................. 502
Preliminary
9November 30, 2007
Table of Contents
List of Tables
Table 1. Documentation Conventions ............................................................................................ 18
Table 3-1. Memory Map ................................................................................................................... 40
Table 4-1. Exception Types .............................................................................................................. 42
Table 4-2. Interrupts ........................................................................................................................ 43
Table 5-1. JTAG Port Pins Reset State ............................................................................................. 46
Table 5-2. JTAG Instruction Register Commands ............................................................................... 51
Table 6-1. System Control Register Map ........................................................................................... 61
Table 7-1. Flash Protection Policy Combinations ............................................................................. 115
Table 7-2. Flash Resident Registers ............................................................................................... 116
Table 7-3. Flash Register Map ........................................................................................................ 116
Table 8-1. GPIO Pad Configuration Examples ................................................................................. 141
Table 8-2. GPIO Interrupt Configuration Example ............................................................................ 141
Table 8-3. GPIO Register Map ....................................................................................................... 142
Table 9-1. Available CCP Pins ........................................................................................................ 179
Table 9-2. 16-Bit Timer With Prescaler Configurations ..................................................................... 182
Table 9-3. Timers Register Map ...................................................................................................... 188
Table 10-1. Watchdog Timer Register Map ........................................................................................ 215
Table 11-1. Samples and FIFO Depth of Sequencers ........................................................................ 238
Table 11-2. ADC Register Map ......................................................................................................... 242
Table 12-1. UART Register Map ....................................................................................................... 276
Table 13-1. SSI Register Map .......................................................................................................... 321
Table 14-1. Examples of I2C Master Timer Period versus Speed Mode ............................................... 351
Table 14-2. Inter-Integrated Circuit (I2C) Interface Register Map ......................................................... 360
Table 14-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 365
Table 15-1. TX & RX FIFO Organization ........................................................................................... 387
Table 15-2. Ethernet Register Map ................................................................................................... 390
Table 16-1. Comparator 0 Operating Modes ...................................................................................... 428
Table 16-2. Comparator 1 Operating Modes ..................................................................................... 429
Table 16-3. Internal Reference Voltage and ACREFCTL Field Values ................................................. 429
Table 16-4. Analog Comparators Register Map ................................................................................. 431
Table 17-1. PWM Register Map ........................................................................................................ 444
Table 19-1. Signals by Pin Number ................................................................................................... 475
Table 19-2. Signals by Signal Name ................................................................................................. 479
Table 19-3. Signals by Function, Except for GPIO ............................................................................. 483
Table 19-4. GPIO Pins and Alternate Functions ................................................................................. 485
Table 20-1. Temperature Characteristics ........................................................................................... 487
Table 20-2. Thermal Characteristics ................................................................................................. 487
Table 21-1. Maximum Ratings .......................................................................................................... 488
Table 21-2. Recommended DC Operating Conditions ........................................................................ 488
Table 21-3. LDO Regulator Characteristics ....................................................................................... 489
Table 21-4. Detailed Power Specifications ........................................................................................ 490
Table 21-5. Flash Memory Characteristics ........................................................................................ 490
Table 21-6. Phase Locked Loop (PLL) Characteristics ....................................................................... 491
Table 21-7. Clock Characteristics ..................................................................................................... 491
Table 21-8. Crystal Characteristics ................................................................................................... 491
Table 21-9. ADC Characteristics ....................................................................................................... 492
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LM3S6432 Microcontroller
Table 21-10. Analog Comparator Characteristics ................................................................................. 492
Table 21-11. Analog Comparator Voltage Reference Characteristics .................................................... 492
Table 21-12. I2C Characteristics ......................................................................................................... 493
Table 21-13. 100BASE-TX Transmitter Characteristics ........................................................................ 493
Table 21-14. 100BASE-TX Transmitter Characteristics (informative) ..................................................... 494
Table 21-15. 100BASE-TX Receiver Characteristics ............................................................................ 494
Table 21-16. 10BASE-T Transmitter Characteristics ............................................................................ 494
Table 21-17. 10BASE-T Transmitter Characteristics (informative) ......................................................... 494
Table 21-18. 10BASE-T Receiver Characteristics ................................................................................ 494
Table 21-19. Isolation Transformers ................................................................................................... 495
Table 21-20. Ethernet Reference Crystal ............................................................................................ 495
Table 21-21. External XTLP Oscillator Characteristics ......................................................................... 496
Table 21-22. SSI Characteristics ........................................................................................................ 496
Table 21-23. JTAG Characteristics ..................................................................................................... 498
Table 21-24. GPIO Characteristics ..................................................................................................... 500
Table 21-25. Reset Characteristics ..................................................................................................... 500
Table C-1. Part Ordering Information ............................................................................................... 526
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11November 30, 2007
Table of Contents
List of Registers
System Control .............................................................................................................................. 55
Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 63
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 65
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 66
Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 67
Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 68
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 69
Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 70
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 71
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 75
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 76
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 78
Register 12: Device Identification 1 (DID1), offset 0x004 ....................................................................... 79
Register 13: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 81
Register 14: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 82
Register 15: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 84
Register 16: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 86
Register 17: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 88
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 90
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 92
Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 94
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 .................................... 96
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 .................................. 98
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 100
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 102
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 104
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 106
Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 108
Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 109
Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 111
Internal Memory ........................................................................................................................... 113
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 118
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 119
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 120
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 122
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 123
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 124
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 125
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 126
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 127
Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 128
Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 129
Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 130
Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 131
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 132
Preliminary
November 30, 200712
LM3S6432 Microcontroller
Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 133
Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 134
Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 135
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 136
General-Purpose Input/Outputs (GPIOs) ................................................................................... 137
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 144
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 145
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 146
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 147
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 148
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 149
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 150
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 151
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 152
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 153
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 155
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 156
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 157
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 158
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 159
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 160
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 161
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 162
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 163
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 164
Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 166
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 167
Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 168
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 169
Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 170
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 171
Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 172
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 173
Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 174
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 175
Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 176
Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 177
General-Purpose Timers ............................................................................................................. 178
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 190
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 191
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 193
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 195
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 198
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 200
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 201
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 202
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 204
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 205
Preliminary
13November 30, 2007
Table of Contents
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 206
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 207
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 208
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 209
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 210
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 211
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 212
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 213
Watchdog Timer ........................................................................................................................... 214
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 217
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 218
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 219
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 220
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 221
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 222
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 223
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 224
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 225
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 226
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 227
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 228
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 229
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 230
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 231
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 232
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 233
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 234
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 235
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 236
Analog-to-Digital Converter (ADC) ............................................................................................. 237
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 244
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 245
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 246
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 247
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 248
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 249
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 252
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 253
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 254
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 255
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 256
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 258
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 261
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 261
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 261
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 261
Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 262
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 262
Preliminary
November 30, 200714
LM3S6432 Microcontroller
Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 262
Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 262
Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 263
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 263
Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 264
Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 264
Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 266
Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 267
Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 268
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 270
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 278
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 280
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 282
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 284
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 285
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 286
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 287
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 289
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 291
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 293
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 295
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 296
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 297
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 299
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 300
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 301
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 302
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 303
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 304
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 305
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 306
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 307
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 308
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 309
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 310
Synchronous Serial Interface (SSI) ............................................................................................ 311
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 323
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 325
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 327
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 328
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 330
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 331
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 333
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 334
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 335
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 336
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 337
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 338
Preliminary
15November 30, 2007
Table of Contents
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 339
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 340
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 341
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 342
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 343
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 344
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 345
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 346
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 347
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 348
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 362
Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 363
Register 3: I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 367
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 368
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 369
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 370
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 371
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 372
Register 9: I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 373
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 375
Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 376
Register 12: I2C Slave Data (I2CSDR), offset 0x008 ........................................................................... 378
Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 379
Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 380
Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 381
Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 382
Ethernet Controller ...................................................................................................................... 383
Register 1: Ethernet MAC Raw Interrupt Status (MACRIS), offset 0x000 ............................................ 392
Register 2: Ethernet MAC Interrupt Acknowledge (MACIACK), offset 0x000 ....................................... 394
Register 3: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... 395
Register 4: Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ 396
Register 5: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... 397
Register 6: Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. 398
Register 7: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 400
Register 8: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. 401
Register 9: Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... 402
Register 10: Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ 403
Register 11: Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 404
Register 12: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 405
Register 13: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. 406
Register 14: Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... 407
Register 15: Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... 408
Register 16: Ethernet PHY Management Register 0 – Control (MR0), address 0x00 ............................. 409
Register 17: Ethernet PHY Management Register 1 – Status (MR1), address 0x01 .............................. 411
Register 18: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 ................. 413
Register 19: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 ................. 414
Preliminary
November 30, 200716
LM3S6432 Microcontroller
Register 20: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address
0x04 ............................................................................................................................. 415
Register 21: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability
(MR5), address 0x05 ..................................................................................................... 417
Register 22: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address
0x06 ............................................................................................................................. 418
Register 23: Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 ............. 419
Register 24: Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address
0x11 .............................................................................................................................. 421
Register 25: Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12 ..................... 423
Register 26: Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13 ....... 424
Register 27: Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17 ......... 425
Register 28: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), address 0x18 .......... 426
Analog Comparators ................................................................................................................... 427
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 432
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 433
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 434
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 435
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 436
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40 ....................................................... 436
Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 437
Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x44 ....................................................... 437
Pulse Width Modulator (PWM) .................................................................................................... 439
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 446
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 447
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 448
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 449
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 450
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 451
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 452
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 453
Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 454
Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 455
Register 11: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 .................................... 457
Register 12: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 459
Register 13: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 460
Register 14: PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 461
Register 15: PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 462
Register 16: PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 463
Register 17: PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 464
Register 18: PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 465
Register 19: PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 468
Register 20: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 471
Register 21: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 472
Register 22: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 473
Preliminary
17November 30, 2007
About This Document
About This Document
This data sheet provides reference information for the LM3S6432 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following documents are referenced by the data sheet, and available on the documentation CD
or from the Luminary Micro web site at www.luminarymicro.com:
■
ARM® Cortex™-M3 Technical Reference Manual
■
ARM® CoreSight Technical Reference Manual
■
ARM® v7-M Architecture Application Level Reference Manual
The following related documents are also referenced:
■
IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the Luminary Micro web
site for additional documentation, including application notes and white papers.
Documentation Conventions
This document uses the conventions shown in Table 1 on page 18.
Table 1. Documentation Conventions
MeaningNotation
General Register Notation
REGISTER
offset 0xnnn
Register N
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
A single bit in a register.bit
Two or more consecutive and related bits.bit field
A hexadecimal increment to a register's address, relative to that module's base address as specified
in “Memory Map” on page 40.
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
Preliminary
November 30, 200718
reserved
yy:xx
Register Bit/Field
Types
R/W1C
W1C
Reset Value
Pin/Signal Notation
assert a signal
SIGNAL
SIGNAL
Numbers
X
0x
LM3S6432 Microcontroller
MeaningNotation
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.RC
Software can read this field. Always write the chip reset value.RO
Software can read or write this field.R/W
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
Only a write by software is valid; a read of the register returns no meaningful data.WO
This value in the register bit diagram shows the bit/field value after any reset, unless noted.Register Bit/Field
Bit cleared to 0 on chip reset.0
Bit set to 1 on chip reset.1
Nondeterministic.-
Pin alternate function; a pin defaults to the signal without the brackets.[ ]
Refers to the physical connection on the package.pin
Refers to the electrical signal encoding of a pin.signal
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
Change the value of the signal from the logically True state to the logically False state.deassert a signal
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
Preliminary
19November 30, 2007
Architectural Overview
1 Architectural Overview
The Luminary Micro Stellaris®family of microcontrollers—the first ARM® Cortex™-M3 based
controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller
applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to
legacy 8- and 16-bit devices, all in a package with a small footprint.
The Stellaris®family offers efficient performance and extensive integration, favorably positioning
the device into cost-conscious applications requiring significant control-processing and connectivity
capabilities. The Stellaris®LM3S1000 series extends the Stellaris®family with larger on-chip
memories, enhanced power management, and expanded I/O and control capabilities. The Stellaris
LM3S2000 series, designed for Controller Area Network (CAN) applications, extends the Stellaris
family with Bosch CAN networking technology, the golden standard in short-haul industrial networks.
The Stellaris®LM3S2000 series also marks the first integration of CAN capabilities with the
revolutionary Cortex-M3 core. The Stellaris®LM3S6000 series combines both a 10/100 Ethernet
Media Access Control (MAC) and Physical (PHY) layer, marking the first time that integrated
connectivity is available with an ARM Cortex-M3 MCU and the only integrated 10/100 Ethernet MAC
and PHY available in an ARM architecture MCU. The Stellaris®LM3S8000 series combines Bosch
Controller Area Network technology with both a 10/100 Ethernet Media Access Control (MAC) and
Physical (PHY) layer.
®
The LM3S6432 microcontroller is targeted for industrial applications, including remote monitoring,
electronic point-of-sale machines, test and measurement equipment, network appliances and
switches, factory automation, HVAC and building control, gaming equipment, motion control, medical
instrumentation, and fire and security.
In addition, the LM3S6432 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S6432 microcontroller is code-compatible
to all members of the extensive Stellaris®family; providing flexibility to fit our customers' precise
needs.
Luminary Micro offers a complete solution to get to market quickly, with evaluation and development
boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong
support, sales, and distributor network.
1.1 Product Features
The LM3S6432 microcontroller includes the following product features:
■ 32-Bit RISC Performance
– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
– Thumb®-compatible Thumb-2-only instruction set processor core for high code density
– 50-MHz operation
– Hardware-division and single-cycle-multiplication
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LM3S6432 Microcontroller
– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
– 29 interrupts with eight priority levels
– Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
– Unaligned data access, enabling data to be efficiently packed into memory
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
■ Internal Memory
– 96 KB single-cycle flash
• User-managed flash block protection on a 2-KB block basis
• User-managed flash data programming
• User-defined and managed flash-protection block
– 32 KB single-cycle SRAM
■ General-Purpose Timers
– Three General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers.
Each GPTM can be configured to operate independently:
• As a single 32-bit timer
• As one 32-bit Real-Time Clock (RTC) to event capture
• For Pulse Width Modulation (PWM)
• To trigger analog-to-digital conversions
– 32-bit Timer modes
• Programmable one-shot timer
• Programmable periodic timer
• Real-Time Clock when using an external 32.768-KHz clock as the input
• User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU
Halt flag during debug
• ADC event trigger
– 16-bit Timer modes
• General-purpose timer function with an 8-bit prescaler
• Programmable one-shot timer
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Architectural Overview
• Programmable periodic timer
• User-enabled stalling when the controller asserts CPU Halt flag during debug
• ADC event trigger
– 16-bit Input Capture modes
• Input edge count capture
• Input edge time capture
– 16-bit PWM mode
• Simple PWM mode with software-programmable output inversion of the PWM signal
■ ARM FiRM-compliant Watchdog Timer
– 32-bit down counter with a programmable load register
– Separate watchdog clock with an enable
– Programmable interrupt generation logic with interrupt masking
– Lock register protection from runaway software
– Reset generation logic with an enable/disable
– User-enabled stalling when the controller asserts the CPU Halt flag during debug
■ 10/100 Ethernet Controller
– Conforms to the IEEE 802.3-2002 Specification
– Full- and half-duplex for both 100 Mbps and 10 Mbps operation
– Integrated 10/100 Mbps Transceiver (PHY)
– Automatic MDI/MDI-X cross-over correction
– Programmable MAC address
– Power-saving and power-down modes
■ Synchronous Serial Interface (SSI)
– Master or slave operation
– Programmable clock bit rate and prescale
– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
– Programmable data frame size from 4 to 16 bits
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LM3S6432 Microcontroller
– Internal loopback test mode for diagnostic/debug testing
■ UART
– Two fully programmable 16C550-type UARTs with IrDA support
– Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service
loading
– Programmable baud-rate generator with fractional divider
– Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
– Standard asynchronous communication bits for start, stop, and parity
– False-start-bit detection
– Line-break generation and detection
■ ADC
– Single- and differential-input configurations
– Three 10-bit channels (inputs) when used as single-ended inputs
– Sample rate of 250 thousand samples/second
– Flexible, configurable analog-to-digital conversion
– Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
– Each sequence triggered by software or internal event (timers, analog comparators, PWM
or GPIO)
– On-chip temperature sensor
■ Analog Comparators
– Two independent integrated analog comparators
– Configurable for output to: drive an output pin, generate an interrupt, or initiate an ADC sample
sequence
– Compare external pin input to external pin input or to internal programmable voltage reference
■ I2C
– Master and slave receive and transmit operation with transmission speed up to 100 Kbps in
Standard mode and 400 Kbps in Fast mode
– Interrupt generation
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Architectural Overview
– Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
■ PWM
– One PWM generator blocks, each with one 16-bit counter, two comparators, a PWM generator,
and a dead-band generator
– One 16-bit counter
• Runs in Down or Up/Down mode
• Output frequency controlled by a 16-bit load value
• Load value updates can be synchronized
• Produces output signals at zero and load value
– Two PWM comparators
• Comparator value updates can be synchronized
• Produces output signals on match
– PWM generator
• Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals
• Produces two independent PWM signals
– Dead-band generator
• Produces two PWM signals with programmable dead-band delays suitable for driving a
half-H bridge
• Can be bypassed, leaving input PWM signals unmodified
– Flexible output control block with PWM output enable of each PWM signal
• PWM output enable of each PWM signal
• Optional output inversion of each PWM signal (polarity control)
• Optional fault handling for each PWM signal
• Synchronization of timers in the PWM generator blocks
• Synchronization of timer/comparator updates across the PWM generator blocks
• Interrupt status summary of the PWM generator blocks
– Can initiate an ADC sample sequence
■ GPIOs
– 14-43 GPIOs, depending on configuration
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LM3S6432 Microcontroller
– 5-V-tolerant input/outputs
– Programmable interrupt generation as either edge-triggered or level-sensitive
– Bit masking in both read and write operations through address lines
– Can initiate an ADC sample sequence
– Programmable control for GPIO pad configuration:
• Weak pull-up or pull-down resistors
• 2-mA, 4-mA, and 8-mA pad drive
• Slew rate control for the 8-mA drive
• Open drain enables
• Digital input enables
■ Power
– On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
– Low-power options on controller: Sleep and Deep-sleep modes
– Low-power options for peripherals: software controls shutdown of individual peripherals
– User-enabled LDO unregulated voltage detection and automatic reset
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Flexible Reset Sources
– Power-on reset (POR)
– Reset pin assertion
– Brown-out (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
– Internal low drop-out (LDO) regulator output goes unregulated
■ Additional Features
– Six reset sources
– Programmable clock source control
– Clock gating to individual peripherals for power savings
– IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
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Architectural Overview
– Debug access via JTAG and Serial Wire interfaces
– Full JTAG boundary scan
■ Industrial-range 100-pin RoHS-compliant LQFP package
1.2 Target Applications
■ Remote monitoring
■ Electronic point-of-sale (POS) machines
■ Test and measurement equipment
■ Network appliances and switches
■ Factory automation
■ HVAC and building control
■ Gaming equipment
■ Motion control
■ Medical instrumentation
■ Fire and security
■ Power and energy
■ Transportation
1.3 High-Level Block Diagram
Figure 1-1 on page 27 represents the full set of features in the Stellaris®6000 series of devices;
not all features may be available on the LM3S6432 microcontroller.
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November 30, 200726
Figure 1-1. Stellaris®6000 Series High-Level Block Diagram
LM3S6432 Microcontroller
1.4 Functional Overview
The following sections provide an overview of the features of the LM3S6432 microcontroller. The
page number in parenthesis indicates where that feature is discussed in detail. Ordering and support
information can be found in “Ordering and Contact Information” on page 526.
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Architectural Overview
1.4.1 ARM Cortex™-M3
1.4.1.1 Processor Core (see page 34)
All members of the Stellaris®product family, including the LM3S6432 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
“ARM Cortex-M3 Processor Core” on page 34 provides an overview of the ARM core; the core is
detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.1.2 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
1.4.1.3 Nested Vectored Interrupt Controller (NVIC)
The LM3S6432 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the
ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions
are handled in Handler Mode. The processor state is automatically stored to the stack on an
exception, and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed without
the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions
(system handlers) and 29 interrupts.
“Interrupts” on page 42 provides an overview of the NVIC controller and the interrupt map. Exceptions
and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.2 Motor Control Peripherals
To enhance motor control, the LM3S6432 controller features Pulse Width Modulation (PWM) outputs.
1.4.2.1 PWM
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
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On the LM3S6432, PWM motion control functionality can be achieved through:
■ Dedicated, flexible motion control hardware using the PWM pins
■ The motion control features of the general-purpose timers using the CCP pins
PWM Pins (see page 439)
The LM3S6432 PWM module consists of one PWM generator blocks and a control block. Each
PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a
PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector. The control
block determines the polarity of the PWM signals, and which signals are passed through to the pins.
Each PWM generator block produces two PWM signals that can either be independent signals or
a single pair of complementary signals with dead-band delays inserted. The output of the PWM
generation blocks are managed by the output control block before being passed to the device pins.
CCP Pins (see page 184)
The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable
to support a simple PWM mode with a software-programmable output inversion of the PWM signal.
1.4.3 Analog Peripherals
LM3S6432 Microcontroller
To handle analog signals, the LM3S6432 microcontroller offers an Analog-to-Digital Converter
(ADC).
For support of analog signals, the LM3S6432 microcontroller offers two analog comparators.
1.4.3.1 ADC (see page 237)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number.
The LM3S6432 ADC module features 10-bit conversion resolution and supports three input channels,
plus an internal temperature sensor. Four buffered sample sequences allow rapid sampling of up
to eight analog input sources without controller intervention. Each sample sequence provides flexible
programming with fully configurable input source, trigger events, interrupt generation, and sequence
priority.
1.4.3.2 Analog Comparators (see page 427)
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
The LM3S6432 microcontroller provides two independent integrated analog comparators that can
be configured to drive an output or generate an interrupt or ADC event.
A comparator can compare a test voltage against any one of these voltages:
■ An individual external reference voltage
■ A shared single external reference voltage
■ A shared internal reference voltage
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
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Architectural Overview
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.
1.4.4 Serial Communications Peripherals
The LM3S6432 controller supports both asynchronous and synchronous serial communications
with:
■ Two fully programmable 16C550-type UARTs
■ One SSI module
■ One I2C module
■ Ethernet controller
1.4.4.1 UART (see page 270)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S6432 controller includes two fully programmable 16C550-type UARTs that support data
transfer speeds up to 460.8 Kbps. (Although similar in functionality to a 16C550 UART, it is not
register-compatible.) In addition, each UART is capable of supporting IrDA.
Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading.
The UART can generate individually masked interrupts from the RX, TX, modem status, and error
conditions. The module provides a single combined interrupt when any of the interrupts are asserted
and are unmasked.
1.4.4.2 SSI (see page 311)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface.
The LM3S6432 controller includes one SSI module that provides the functionality for synchronous
serial communications with peripheral devices, and can be configured to use the Freescale SPI,
MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also
configurable, and can be set between 4 and 16 bits, inclusive.
The SSI module performs serial-to-parallel conversion on data received from a peripheral device,
and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths
are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently.
The SSI module can be configured as either a master or slave device. As a slave device, the SSI
module can also be configured to disable its output, which allows a master device to be coupled
with multiple slave devices.
The SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
1.4.4.3 I2C (see page 348)
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL).
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