TEXAS INSTRUMENTS LM3S6420 Technical data

PRELIMINARY

LM3S6420 Microcontroller

DATA SHEET

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LM3S6420 Microcontroller

About This Document

This data sheet provides reference information for the LM3S6420 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3 core.

Audience

This manual is intended for system software developers, hardware designers, and application developers.

About This Manual

This document is organized into sections that correspond to each major feature.

Documentation Conventions

This document uses the conventions shown in Table 1 on page 16.

Table 1. Documentation Conventions

MeaningNotation

General Register Notation

REGISTER

offset 0xnnn

Register N

APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more than one register. For example, SRCRn represents any (or all) of the three Software Reset Control registers: SRCR0, SRCR1 , and SRCR2.

A single bit in a register.bit

Two or more consecutive and related bits.bit field

A hexadecimal increment to a register's address, relative to that module's base address as specified in “Memory Map” on page 35.

Registers are numbered consecutively throughout the document to aid in referencing them. The register number has no meaning to software.

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November 30, 200716

reserved

yy:xx

Register Bit/Field Types

R/W1C

W1C

Reset Value

Pin/Signal Notation

assert a signal

SIGNAL

Numbers

X

0x

LM3S6420 Microcontroller

MeaningNotation

Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to 0; however, user software should not rely on the value of a reserved bit. To provide software compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in that register.

This value in the register bit diagram indicates whether software running on the controller can change the value of the bit field.

Software can read this field. The bit or field is cleared by hardware after reading the bit/field.RC

Software can read this field. Always write the chip reset value.RO

Software can read or write this field.R/W

Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.

This register type is primarily used for clearing interrupt status bits where the read operation provides the interrupt status and the write of the read value clears only the interrupts being reported at the time the register was read.

Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A read of the register returns no meaningful data.

This register is typically used to clear the corresponding bit in an interrupt register.

Only a write by software is valid; a read of the register returns no meaningful data.WO

This value in the register bit diagram shows the bit/field value after any reset, unless noted.Register Bit/Field

Bit cleared to 0 on chip reset.0

Bit set to 1 on chip reset.1

Nondeterministic.-

Pin alternate function; a pin defaults to the signal without the brackets.[ ]

Refers to the physical connection on the package.pin

Refers to the electrical signal encoding of a pin.signal

Change the value of the signal from the logically False state to the logically True state. For active High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL below).

Change the value of the signal from the logically True state to the logically False state.deassert a signal

Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.

Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.

An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and so on.

Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.

All other numbers within register tables are assumed to be binary. Within conceptual information, binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written without a prefix or suffix.

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Architectural Overview

1 Architectural Overview

The Luminary Micro Stellaris®family of microcontrollers—the first ARM® Cortex™-M3 based controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint.

The Stellaris®family offers efficient performance and extensive integration, favorably positioning the device into cost-conscious applications requiring significant control-processing and connectivity capabilities. The Stellaris®LM3S1000 series extends the Stellaris®family with larger on-chip memories, enhanced power management, and expanded I/O and control capabilities. The Stellaris LM3S2000 series, designed for Controller Area Network (CAN) applications, extends the Stellaris family with Bosch CAN networking technology, the golden standard in short-haul industrial networks. The Stellaris®LM3S2000 series also marks the first integration of CAN capabilities with the revolutionary Cortex-M3 core. The Stellaris®LM3S6000 series combines both a 10/100 Ethernet Media Access Control (MAC) and Physical (PHY) layer, marking the first time that integrated connectivity is available with an ARM Cortex-M3 MCU and the only integrated 10/100 Ethernet MAC and PHY available in an ARM architecture MCU. The Stellaris®LM3S8000 series combines Bosch Controller Area Network technology with both a 10/100 Ethernet Media Access Control (MAC) and Physical (PHY) layer.

®

The LM3S6420 microcontroller is targeted for industrial applications, including remote monitoring, electronic point-of-sale machines, test and measurement equipment, network appliances and switches, factory automation, HVAC and building control, gaming equipment, motion control, medical instrumentation, and fire and security.

In addition, the LM3S6420 microcontroller offers the advantages of ARM's widely available development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community. Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost. Finally, the LM3S6420 microcontroller is code-compatible to all members of the extensive Stellaris®family; providing flexibility to fit our customers' precise needs.

Luminary Micro offers a complete solution to get to market quickly, with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and distributor network.

1.1 Product Features

The LM3S6420 microcontroller includes the following product features:

■ 32-Bit RISC Performance

– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded

applications

– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero

counter with a flexible control mechanism

– Thumb®-compatible Thumb-2-only instruction set processor core for high code density

– 25-MHz operation

– Hardware-division and single-cycle-multiplication

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LM3S6420 Microcontroller

– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt

handling

– 21 interrupts with eight priority levels

– Memory protection unit (MPU), providing a privileged mode for protected operating system

functionality

– Unaligned data access, enabling data to be efficiently packed into memory

– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined

peripheral control

■ Internal Memory

– 96 KB single-cycle flash

• User-managed flash block protection on a 2-KB block basis

• User-managed flash data programming

• User-defined and managed flash-protection block

– 32 KB single-cycle SRAM

■ General-Purpose Timers

– Three General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers.

Each GPTM can be configured to operate independently:

• As a single 32-bit timer

• As one 32-bit Real-Time Clock (RTC) to event capture

• For Pulse Width Modulation (PWM)

– 32-bit Timer modes

• Programmable one-shot timer

• Programmable periodic timer

• Real-Time Clock when using an external 32.768-KHz clock as the input

• User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU Halt flag during debug

– 16-bit Timer modes

• General-purpose timer function with an 8-bit prescaler

• Programmable one-shot timer

• Programmable periodic timer

• User-enabled stalling when the controller asserts CPU Halt flag during debug

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– 16-bit Input Capture modes

• Input edge count capture

• Input edge time capture

– 16-bit PWM mode

• Simple PWM mode with software-programmable output inversion of the PWM signal

■ ARM FiRM-compliant Watchdog Timer

– 32-bit down counter with a programmable load register

– Separate watchdog clock with an enable

– Programmable interrupt generation logic with interrupt masking

– Lock register protection from runaway software

– Reset generation logic with an enable/disable

– User-enabled stalling when the controller asserts the CPU Halt flag during debug

■ 10/100 Ethernet Controller

– Conforms to the IEEE 802.3-2002 Specification

– Full- and half-duplex for both 100 Mbps and 10 Mbps operation

– Integrated 10/100 Mbps Transceiver (PHY)

– Automatic MDI/MDI-X cross-over correction

– Programmable MAC address

– Power-saving and power-down modes

■ Synchronous Serial Interface (SSI)

– Master or slave operation

– Programmable clock bit rate and prescale

– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep

– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments

synchronous serial interfaces

– Programmable data frame size from 4 to 16 bits

– Internal loopback test mode for diagnostic/debug testing

■ UART

– Fully programmable 16C550-type UART with IrDA support

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LM3S6420 Microcontroller

– Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service

loading

– Programmable baud-rate generator with fractional divider

– Programmable FIFO length, including 1-byte deep operation providing conventional

double-buffered interface

– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8

– Standard asynchronous communication bits for start, stop, and parity

– False-start-bit detection

– Line-break generation and detection

■ Analog Comparators

– Two independent integrated analog comparators

– Configurable for output to: drive an output pin or generate an interrupt

– Compare external pin input to external pin input or to internal programmable voltage reference

■ GPIOs

– 23-46 GPIOs, depending on configuration

– 5-V-tolerant input/outputs

– Programmable interrupt generation as either edge-triggered or level-sensitive

– Bit masking in both read and write operations through address lines

– Programmable control for GPIO pad configuration:

• Weak pull-up or pull-down resistors

• 2-mA, 4-mA, and 8-mA pad drive

• Slew rate control for the 8-mA drive

• Open drain enables

• Digital input enables

■ Power

– On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable

from 2.25 V to 2.75 V

– Low-power options on controller: Sleep and Deep-sleep modes

– Low-power options for peripherals: software controls shutdown of individual peripherals

– User-enabled LDO unregulated voltage detection and automatic reset

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– 3.3-V supply brown-out detection and reporting via interrupt or reset

■ Flexible Reset Sources

– Power-on reset (POR)

– Reset pin assertion

– Brown-out (BOR) detector alerts to system power drops

– Software reset

– Watchdog timer reset

– Internal low drop-out (LDO) regulator output goes unregulated

■ Additional Features

– Six reset sources

– Programmable clock source control

– Clock gating to individual peripherals for power savings

– IEEE 1149.1-1990 compliant Test Access Port (TAP) controller

– Debug access via JTAG and Serial Wire interfaces

– Full JTAG boundary scan

■ Industrial-range 100-pin RoHS-compliant LQFP package

1.2 Target Applications

■ Remote monitoring

■ Electronic point-of-sale (POS) machines

■ Test and measurement equipment

■ Network appliances and switches

■ Factory automation

■ HVAC and building control

■ Gaming equipment

■ Motion control

■ Medical instrumentation

■ Fire and security

■ Power and energy

■ Transportation

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1.3 High-Level Block Diagram

Figure 1-1 on page 23 represents the full set of features in the Stellaris®6000 series of devices; not all features may be available on the LM3S6420 microcontroller.

Figure 1-1. Stellaris®6000 Series High-Level Block Diagram

LM3S6420 Microcontroller

1.4 Functional Overview

The following sections provide an overview of the features of the LM3S6420 microcontroller. The page number in parenthesis indicates where that feature is discussed in detail. Ordering and support information can be found in “Ordering and Contact Information” on page 409.

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Architectural Overview

1.4.1 ARM Cortex™-M3

1.4.1.1 Processor Core (see page 29)

All members of the Stellaris®product family, including the LM3S6420 microcontroller, are designed around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low-power consumption, while delivering outstanding computational performance and exceptional system response to interrupts.

“ARM Cortex-M3 Processor Core” on page 29 provides an overview of the ARM core; the core is detailed in the ARM® Cortex™-M3 Technical Reference Manual.

1.4.1.2 System Timer (SysTick)

Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example:

■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a

SysTick routine.

■ A high-speed alarm timer using the system clock.

■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock

used and the dynamic range of the counter.

■ A simple counter. Software can use this to measure time to completion and time used.

■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field

in the control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop.

1.4.1.3 Nested Vectored Interrupt Controller (NVIC)

The LM3S6420 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions are handled in Handler Mode. The processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions (system handlers) and 21 interrupts.

“Interrupts” on page 37 provides an overview of the NVIC controller and the interrupt map. Exceptions and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual.

1.4.2 Motor Control Peripherals

To enhance motor control, the LM3S6420 controller features Pulse Width Modulation (PWM) outputs.

1.4.2.1 PWM

Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels. High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control.

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On the LM3S6420, PWM motion control functionality can be achieved through:

■ The motion control features of the general-purpose timers using the CCP pins

CCP Pins (see page 175)

The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable to support a simple PWM mode with a software-programmable output inversion of the PWM signal.

1.4.3 Analog Peripherals

For support of analog signals, the LM3S6420 microcontroller offers two analog comparators.

1.4.3.1 Analog Comparators (see page 350)

An analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result.

The LM3S6420 microcontroller provides two independent integrated analog comparators that can be configured to drive an output or generate an interrupt .

A comparator can compare a test voltage against any one of these voltages:

■ An individual external reference voltage

LM3S6420 Microcontroller

■ A shared single external reference voltage

■ A shared internal reference voltage

The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts to cause it to start capturing a sample sequence.

1.4.4 Serial Communications Peripherals

The LM3S6420 controller supports both asynchronous and synchronous serial communications with:

■ One fully programmable 16C550-type UART

■ One SSI module

■ Ethernet controller

1.4.4.1 UART (see page 228)

A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately.

The LM3S6420 controller includes one fully programmable 16C550-type UARTthat supports data transfer speeds up to 460.8 Kbps. (Although similar in functionality to a 16C550 UART, it is not register-compatible.) In addition, each UART is capable of supporting IrDA.

Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading. The UART can generate individually masked interrupts from the RX, TX, modem status, and error conditions. The module provides a single combined interrupt when any of the interrupts are asserted and are unmasked.

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Architectural Overview

1.4.4.2 SSI (see page 269)

Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface.

The LM3S6420 controller includes one SSI module that provides the functionality for synchronous serial communications with peripheral devices, and can be configured to use the Freescale SPI, MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also configurable, and can be set between 4 and 16 bits, inclusive.

The SSI module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently.

The SSI module can be configured as either a master or slave device. As a slave device, the SSI module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices.

The SSI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the SSI module's input clock. Bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral.

1.4.4.3 Ethernet Controller (see page 306)

Ethernet is a frame-based computer networking technology for local area networks (LANs). Ethernet has been standardized as IEEE 802.3. It defines a number of wiring and signaling standards for the physical layer, two means of network access at the Media Access Control (MAC)/Data Link Layer, and a common addressing format.

The Stellaris® Ethernet Controller consists of a fully integrated media access controller (MAC) and network physical (PHY) interface device. The Ethernet Controller conforms to IEEE 802.3 specifications and fully supports 10BASE-T and 100BASE-TX standards. In addition, the Ethernet Controller supports automatic MDI/MDI-X cross-over correction.

1.4.5 System Peripherals

1.4.5.1 Programmable GPIOs (see page 128)

General-purpose input/output (GPIO) pins offer flexibility for a variety of connections.

The Stellaris®GPIO module is composed of seven physical GPIO blocks, each corresponding to an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time Microcontrollers specification) and supports 23-46 programmable input/output pins. The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page 363 for the signals available to each GPIO pin).

The GPIO module features programmable interrupt generation as either edge-triggered or level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in both read and write operations through address lines.

1.4.5.2 Three Programmable Timers (see page 169)

Programmable timers can be used to count or time external events that drive the Timer input pins.

The Stellaris®General-Purpose Timer Module (GPTM) contains three GPTM blocks. Each GPTM block provides two 16-bit timers/counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).

When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can

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extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event capture or Pulse Width Modulation (PWM) generation.

1.4.5.3 Watchdog Timer (see page 205)

A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way.

The Stellaris®Watchdog Timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, and a locking register.

The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered.

1.4.6 Memory Peripherals

The LM3S6420 controller offers both single-cycle SRAM and single-cycle Flash memory.

1.4.6.1 SRAM (see page 104)

The LM3S6420 static random access memory (SRAM) controller supports 32 KB SRAM. The internal SRAM of the Stellaris®devices is located at offset 0x0000.0000 of the device memory map. To reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation.

LM3S6420 Microcontroller

1.4.6.2 Flash (see page 105)

The LM3S6420 Flash controller supports 96 KB of flash memory. The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually protected. The blocks can be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger.

1.4.7 Additional Features

1.4.7.1 Memory Map (see page 35)

A memory map lists the location of instructions and data in memory. The memory map for the LM3S6420 controller can be found in “Memory Map” on page 35. Register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map.

The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory map.

1.4.7.2 JTAG TAP Controller (see page 39)

The Joint Test Action Group (JTAG) port provides a standardized serial interface for controlling the Test Access Port (TAP) and associated test logic. The TAP, JTAG instruction register, and JTAG data registers can be used to test the interconnects of assembled printed circuit boards, obtain manufacturing information on the components, and observe and/or control the inputs and outputs

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Architectural Overview

of the controller during normal operation. The JTAG port provides a high degree of testability and chip-level access at a low cost.

The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture.

The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions.

1.4.7.3 System Control and Clocks (see page 50)

System control determines the overall operation of the device. It provides information about the device, controls the clocking of the device and individual peripherals, and handles reset detection and reporting.

1.4.8 Hardware Details

Details on the pins and package can be found in the following sections:

■ “Pin Diagram” on page 362

■ “Signal Tables” on page 363

■ “Operating Characteristics” on page 375

■ “Electrical Characteristics” on page 376

■ “Package Information” on page 389

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2 ARM Cortex-M3 Processor Core

The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Features include:

■ Compact core.

■ Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory

size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications.

■ Rapid application execution through Harvard architecture characterized by separate buses for

instruction and data.

■ Exceptional interrupt handling, by implementing the register manipulations required for handling

an interrupt in hardware.

■ Memory protection unit (MPU) to provide a privileged mode of operation for complex applications.

LM3S6420 Microcontroller

■ Migration from the ARM7™ processor family for better performance and power efficiency.

■ Full-featured debug solution with a:

– Serial Wire JTAG Debug Port (SWJ-DP)

– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints

– Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,

and system profiling

– Instrumentation Trace Macrocell (ITM) for support of printf style debugging

– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer

The Stellaris®family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motors.

For more information on the ARM Cortex-M3 processor core, see the ARM® Cortex™-M3 Technical

Reference Manual. For information on SWJ-DP, see the ARM® CoreSight Technical Reference Manual.

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Private Peripheral

Bus

(internal)

Data

Watchpoint

and Trace

Interrupts

Debug

Sleep

Instrumentation

Trace Macrocell

Trace

Port

Interface

Unit

CM3 Core

Instructions Data

Flash

Patch and

Breakpoint

Memory

Protection

Unit

Adv. High-

Perf. Bus

Access Port

Nested

Vectored

Interrupt

Controller

Serial Wire JTAG

Debug Port

Bus

Matrix

Adv. Peripheral

Bus

I-code bus D-code bus System bus

ROM

Table

Private

Peripheral

Bus

(external)

Serial

Wire

Output

Trace

Port

(SWO)

ARM

Cortex-M3

ARM Cortex-M3 Processor Core

2.1 Block Diagram

Figure 2-1. CPU Block Diagram

2.2 Functional Description

2.2.1 Serial Wire and JTAG Debug

Important:

Luminary Micro has implemented the ARM Cortex-M3 core as shown in Figure 2-1 on page 30. As noted in the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3 components are flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the MPU, and the Nested Vectored Interrupt Controller (NVIC). Each of these is addressed in the sections that follow.

Luminary Micro has replaced the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant Serial Wire JTAG Debug Port (SWJ-DP) interface. This means Chapter 12, “Debug Port,” of the ARM® Cortex™-M3 Technical Reference Manual does not apply to Stellaris®devices.

The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP.

The ARM® Cortex™-M3 Technical Reference Manual describes all the features of an ARM Cortex-M3 in detail. However, these features differ based on the implementation. This section describes the Stellaris®implementation.

Preliminary

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TEXAS INSTRUMENTS LM3S6420 Technical data

LM3S6420 Microcontroller

Table of Contents

List of Figures

List of Tables

List of Registers

About This Document

Audience

About This Manual

Related Documents

Documentation Conventions

Architectural Overview

1.1 Product Features

1.2 Target Applications

1.3 High-Level Block Diagram

1.4 Functional Overview

1.4.1 ARM Cortex™-M3

1.4.1.2 System Timer (SysTick)

1.4.1.3 Nested Vectored Interrupt Controller (NVIC)

1.4.2 Motor Control Peripherals

1.4.2.1 PWM

1.4.3 Analog Peripherals

1.4.4 Serial Communications Peripherals

1.4.5 System Peripherals

1.4.6 Memory Peripherals

1.4.7 Additional Features

1.4.8 Hardware Details

2 ARM Cortex-M3 Processor Core

2.1 Block Diagram

2.2 Functional Description

2.2.1 Serial Wire and JTAG Debug