TEXAS INSTRUMENTS LM3S301 Technical data
PRELIMINARY
LM3S301 Microcontroller
DATA SHEET
Copyright © 2007 Luminary Micro, Inc.DS-LM3S301-1972
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Preliminary
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LM3S301 Microcontroller
Table of Contents
About This Document .................................................................................................................... 17
Audience .............................................................................................................................................. 17
About This Manual ................................................................................................................................ 17
Related Documents ............................................................................................................................... 17
Documentation Conventions .................................................................................................................. 17
1 Architectural Overview ...................................................................................................... 19
1.1 Product Features ...................................................................................................................... 19
1.2 Target Applications .................................................................................................................... 24
1.3 High-Level Block Diagram ......................................................................................................... 24
1.4 Functional Overview .................................................................................................................. 25
1.4.1 ARM Cortex™-M3 ..................................................................................................................... 26
1.4.2 Motor Control Peripherals .......................................................................................................... 26
1.4.3 Analog Peripherals .................................................................................................................... 27
1.4.4 Serial Communications Peripherals ............................................................................................ 28
1.4.5 System Peripherals ................................................................................................................... 28
1.4.6 Memory Peripherals .................................................................................................................. 29
1.4.7 Additional Features ................................................................................................................... 30
1.4.8 Hardware Details ...................................................................................................................... 30
1.4.9 System Block Diagram .............................................................................................................. 31
2 ARM Cortex-M3 Processor Core ...................................................................................... 32
2.1 Block Diagram .......................................................................................................................... 33
2.2 Functional Description ............................................................................................................... 33
2.2.1 Serial Wire and JTAG Debug ..................................................................................................... 33
2.2.2 Embedded Trace Macrocell (ETM) ............................................................................................. 34
2.2.3 Trace Port Interface Unit (TPIU) ................................................................................................. 34
2.2.4 ROM Table ............................................................................................................................... 34
2.2.5 Memory Protection Unit (MPU) ................................................................................................... 34
2.2.6 Nested Vectored Interrupt Controller (NVIC) ................................................................................ 34
3 Memory Map ....................................................................................................................... 38
4 Interrupts ............................................................................................................................ 40
5 JTAG Interface .................................................................................................................... 42
5.1 Block Diagram .......................................................................................................................... 43
5.2 Functional Description ............................................................................................................... 43
5.2.1 JTAG Interface Pins .................................................................................................................. 44
5.2.2 JTAG TAP Controller ................................................................................................................. 45
5.2.3 Shift Registers .......................................................................................................................... 46
5.2.4 Operational Considerations ........................................................................................................ 46
5.3 Initialization and Configuration ................................................................................................... 47
5.4 Register Descriptions ................................................................................................................ 48
5.4.1 Instruction Register (IR) ............................................................................................................. 48
5.4.2 Data Registers .......................................................................................................................... 50
6 System Control ................................................................................................................... 52
6.1 Functional Description ............................................................................................................... 52
6.1.1 Device Identification .................................................................................................................. 52
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6.1.2 Reset Control ............................................................................................................................ 52
6.1.3 Power Control ........................................................................................................................... 55
6.1.4 Clock Control ............................................................................................................................ 55
6.1.5 System Control ......................................................................................................................... 58
6.2 Initialization and Configuration ................................................................................................... 58
6.3 Register Map ............................................................................................................................ 59
6.4 Register Descriptions ................................................................................................................ 60
7 Internal Memory ............................................................................................................... 110
7.1 Block Diagram ........................................................................................................................ 110
7.2 Functional Description ............................................................................................................. 110
7.2.1 SRAM Memory ........................................................................................................................ 110
7.2.2 Flash Memory ......................................................................................................................... 111
7.3 Flash Memory Initialization and Configuration ........................................................................... 113
7.3.1 Changing Flash Protection Bits ................................................................................................ 113
7.3.2 Flash Programming ................................................................................................................. 114
7.4 Register Map .......................................................................................................................... 114
7.5 Flash Register Descriptions (Flash Control Offset) ..................................................................... 115
7.6 Flash Register Descriptions (System Control Offset) .................................................................. 122
8 General-Purpose Input/Outputs (GPIOs) ....................................................................... 126
8.1 Block Diagram ........................................................................................................................ 127
8.2 Functional Description ............................................................................................................. 127
8.2.1 Data Control ........................................................................................................................... 128
8.2.2 Interrupt Control ...................................................................................................................... 129
8.2.3 Mode Control .......................................................................................................................... 130
8.2.4 Pad Control ............................................................................................................................. 130
8.2.5 Identification ........................................................................................................................... 130
8.3 Initialization and Configuration ................................................................................................. 130
8.4 Register Map .......................................................................................................................... 131
8.5 Register Descriptions .............................................................................................................. 133
9 General-Purpose Timers ................................................................................................. 165
9.1 Block Diagram ........................................................................................................................ 165
9.2 Functional Description ............................................................................................................. 166
9.2.1 GPTM Reset Conditions .......................................................................................................... 166
9.2.2 32-Bit Timer Operating Modes .................................................................................................. 167
9.2.3 16-Bit Timer Operating Modes .................................................................................................. 168
9.3 Initialization and Configuration ................................................................................................. 172
9.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 172
9.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 173
9.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 173
9.3.4 16-Bit Input Edge Count Mode ................................................................................................. 174
9.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 174
9.3.6 16-Bit PWM Mode ................................................................................................................... 175
9.4 Register Map .......................................................................................................................... 175
9.5 Register Descriptions .............................................................................................................. 176
10 Watchdog Timer ............................................................................................................... 201
10.1 Block Diagram ........................................................................................................................ 201
10.2 Functional Description ............................................................................................................. 201
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10.3 Initialization and Configuration ................................................................................................. 202
10.4 Register Map .......................................................................................................................... 202
10.5 Register Descriptions .............................................................................................................. 203
11 Analog-to-Digital Converter (ADC) ................................................................................. 224
11.1 Block Diagram ........................................................................................................................ 225
11.2 Functional Description ............................................................................................................. 225
11.2.1 Sample Sequencers ................................................................................................................ 225
11.2.2 Module Control ........................................................................................................................ 226
11.2.3 Hardware Sample Averaging Circuit ......................................................................................... 227
11.2.4 Analog-to-Digital Converter ...................................................................................................... 227
11.2.5 Test Modes ............................................................................................................................. 227
11.2.6 Internal Temperature Sensor .................................................................................................... 227
11.3 Initialization and Configuration ................................................................................................. 228
11.3.1 Module Initialization ................................................................................................................. 228
11.3.2 Sample Sequencer Configuration ............................................................................................. 228
11.4 Register Map .......................................................................................................................... 229
11.5 Register Descriptions .............................................................................................................. 230
12 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 257
12.1 Block Diagram ........................................................................................................................ 258
12.2 Functional Description ............................................................................................................. 258
12.2.1 Transmit/Receive Logic ........................................................................................................... 258
12.2.2 Baud-Rate Generation ............................................................................................................. 259
12.2.3 Data Transmission .................................................................................................................. 260
12.2.4 FIFO Operation ....................................................................................................................... 260
12.2.5 Interrupts ................................................................................................................................ 260
12.2.6 Loopback Operation ................................................................................................................ 261
12.3 Initialization and Configuration ................................................................................................. 261
12.4 Register Map .......................................................................................................................... 262
12.5 Register Descriptions .............................................................................................................. 263
13 Synchronous Serial Interface (SSI) ................................................................................ 295
13.1 Block Diagram ........................................................................................................................ 295
13.2 Functional Description ............................................................................................................. 295
13.2.1 Bit Rate Generation ................................................................................................................. 296
13.2.2 FIFO Operation ....................................................................................................................... 296
13.2.3 Interrupts ................................................................................................................................ 296
13.2.4 Frame Formats ....................................................................................................................... 297
13.3 Initialization and Configuration ................................................................................................. 304
13.4 Register Map .......................................................................................................................... 305
13.5 Register Descriptions .............................................................................................................. 306
14 Analog Comparators ....................................................................................................... 332
14.1 Block Diagram ........................................................................................................................ 332
14.2 Functional Description ............................................................................................................. 332
14.2.1 Internal Reference Programming .............................................................................................. 334
14.3 Initialization and Configuration ................................................................................................. 335
14.4 Register Map .......................................................................................................................... 335
14.5 Register Descriptions .............................................................................................................. 336
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15 Pulse Width Modulator (PWM) ........................................................................................ 344
15.1 Block Diagram ........................................................................................................................ 344
15.2 Functional Description ............................................................................................................. 344
15.2.1 PWM Timer ............................................................................................................................. 344
15.2.2 PWM Comparators .................................................................................................................. 345
15.2.3 PWM Signal Generator ............................................................................................................ 346
15.2.4 Dead-Band Generator ............................................................................................................. 347
15.2.5 Interrupt/ADC-Trigger Selector ................................................................................................. 347
15.2.6 Synchronization Methods ......................................................................................................... 347
15.2.7 Fault Conditions ...................................................................................................................... 348
15.2.8 Output Control Block ............................................................................................................... 348
15.3 Initialization and Configuration ................................................................................................. 348
15.4 Register Map .......................................................................................................................... 349
15.5 Register Descriptions .............................................................................................................. 350
16 Pin Diagram ...................................................................................................................... 379
17 Signal Tables .................................................................................................................... 380
18 Operating Characteristics ............................................................................................... 386
19 Electrical Characteristics ................................................................................................ 387
19.1 DC Characteristics .................................................................................................................. 387
19.1.1 Maximum Ratings ................................................................................................................... 387
19.1.2 Recommended DC Operating Conditions .................................................................................. 387
19.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 388
19.1.4 Power Specifications ............................................................................................................... 388
19.1.5 Flash Memory Characteristics .................................................................................................. 389
19.2 AC Characteristics ................................................................................................................... 389
19.2.1 Load Conditions ...................................................................................................................... 389
19.2.2 Clocks .................................................................................................................................... 389
19.2.3 Analog-to-Digital Converter ...................................................................................................... 390
19.2.4 Analog Comparator ................................................................................................................. 390
19.2.5 Synchronous Serial Interface (SSI) ........................................................................................... 391
19.2.6 JTAG and Boundary Scan ........................................................................................................ 392
19.2.7 General-Purpose I/O ............................................................................................................... 393
19.2.8 Reset ..................................................................................................................................... 394
20 Package Information ........................................................................................................ 397
A Serial Flash Loader .......................................................................................................... 399
A.1 Serial Flash Loader ................................................................................................................. 399
A.2 Interfaces ............................................................................................................................... 399
A.2.1 UART ..................................................................................................................................... 399
A.2.2 SSI ......................................................................................................................................... 399
A.3 Packet Handling ...................................................................................................................... 400
A.3.1 Packet Format ........................................................................................................................ 400
A.3.2 Sending Packets ..................................................................................................................... 400
A.3.3 Receiving Packets ................................................................................................................... 400
A.4 Commands ............................................................................................................................. 401
A.4.1 COMMAND_PING (0X20) ........................................................................................................ 401
A.4.2 COMMAND_GET_STATUS (0x23) ........................................................................................... 401
A.4.3 COMMAND_DOWNLOAD (0x21) ............................................................................................. 401
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A.4.4 COMMAND_SEND_DATA (0x24) ............................................................................................. 402
A.4.5 COMMAND_RUN (0x22) ......................................................................................................... 402
A.4.6 COMMAND_RESET (0x25) ..................................................................................................... 402
B Register Quick Reference ............................................................................................... 404
C Ordering and Contact Information ................................................................................. 417
C.1 Ordering Information ................................................................................................................ 417
C.2 Kits ......................................................................................................................................... 417
C.3 Company Information .............................................................................................................. 417
C.4 Support Information ................................................................................................................. 418
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List of Figures
Figure 1-1. Stellaris®300 Series High-Level Block Diagram ................................................................ 25
Figure 1-2. LM3S301 Controller System-Level Block Diagram ............................................................. 31
Figure 2-1. CPU Block Diagram ......................................................................................................... 33
Figure 2-2. TPIU Block Diagram ........................................................................................................ 34
Figure 5-1. JTAG Module Block Diagram ............................................................................................ 43
Figure 5-2. Test Access Port State Machine ....................................................................................... 46
Figure 5-3. IDCODE Register Format ................................................................................................. 50
Figure 5-4. BYPASS Register Format ................................................................................................ 50
Figure 5-5. Boundary Scan Register Format ....................................................................................... 51
Figure 6-1. External Circuitry to Extend Reset .................................................................................... 53
Figure 6-2. Main Clock Tree .............................................................................................................. 56
Figure 7-1. Flash Block Diagram ...................................................................................................... 110
Figure 8-1. GPIO Module Block Diagram .......................................................................................... 127
Figure 8-2. GPIO Port Block Diagram ............................................................................................... 128
Figure 8-3. GPIODATA Write Example ............................................................................................. 129
Figure 8-4. GPIODATA Read Example ............................................................................................. 129
Figure 9-1. GPTM Module Block Diagram ........................................................................................ 166
Figure 9-2. 16-Bit Input Edge Count Mode Example .......................................................................... 170
Figure 9-3. 16-Bit Input Edge Time Mode Example ........................................................................... 171
Figure 9-4. 16-Bit PWM Mode Example ............................................................................................ 172
Figure 10-1. WDT Module Block Diagram .......................................................................................... 201
Figure 11-1. ADC Module Block Diagram ........................................................................................... 225
Figure 11-2. Internal Temperature Sensor Characteristic ..................................................................... 228
Figure 12-1. UART Module Block Diagram ......................................................................................... 258
Figure 12-2. UART Character Frame ................................................................................................. 259
Figure 13-1. SSI Module Block Diagram ............................................................................................. 295
Figure 13-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 297
Figure 13-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 298
Figure 13-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 299
Figure 13-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 299
Figure 13-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 300
Figure 13-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 301
Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 301
Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 302
Figure 13-10. MICROWIRE Frame Format (Single Frame) .................................................................... 303
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 304
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 304
Figure 14-1. Analog Comparator Module Block Diagram ..................................................................... 332
Figure 14-2. Structure of Comparator Unit .......................................................................................... 333
Figure 14-3. Comparator Internal Reference Structure ........................................................................ 334
Figure 15-1. PWM Module Block Diagram .......................................................................................... 344
Figure 15-2. PWM Count-Down Mode ................................................................................................ 345
Figure 15-3. PWM Count-Up/Down Mode .......................................................................................... 346
Figure 15-4. PWM Generation Example In Count-Up/Down Mode ....................................................... 346
Figure 15-5. PWM Dead-Band Generator ........................................................................................... 347
Figure 16-1. Pin Connection Diagram ................................................................................................ 379
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LM3S301 Microcontroller
Figure 19-1. Load Conditions ............................................................................................................ 389
Figure 19-2. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 391
Figure 19-3. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 391
Figure 19-4. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 392
Figure 19-5. JTAG Test Clock Input Timing ......................................................................................... 393
Figure 19-6. JTAG Test Access Port (TAP) Timing .............................................................................. 393
Figure 19-7. JTAG TRST Timing ........................................................................................................ 393
Figure 19-8. External Reset Timing (RST) .......................................................................................... 394
Figure 19-9. Power-On Reset Timing ................................................................................................. 395
Figure 19-10. Brown-Out Reset Timing ................................................................................................ 395
Figure 19-11. Software Reset Timing ................................................................................................... 395
Figure 19-12. Watchdog Reset Timing ................................................................................................. 396
Figure 19-13. LDO Reset Timing ......................................................................................................... 396
Figure 20-1. 48-Pin LQFP Package ................................................................................................... 397
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Table of Contents
List of Tables
Table 1. Documentation Conventions ............................................................................................ 17
Table 3-1. Memory Map ................................................................................................................... 38
Table 4-1. Exception Types .............................................................................................................. 40
Table 4-2. Interrupts ........................................................................................................................ 41
Table 5-1. JTAG Port Pins Reset State ............................................................................................. 44
Table 5-2. JTAG Instruction Register Commands ............................................................................... 48
Table 6-1. System Control Register Map ........................................................................................... 59
Table 6-2. PLL Mode Control ........................................................................................................... 74
Table 7-1. Flash Protection Policy Combinations ............................................................................. 112
Table 7-2. Flash Register Map ........................................................................................................ 115
Table 8-1. GPIO Pad Configuration Examples ................................................................................. 130
Table 8-2. GPIO Interrupt Configuration Example ............................................................................ 131
Table 8-3. GPIO Register Map ....................................................................................................... 132
Table 9-1. Available CCP Pins ........................................................................................................ 166
Table 9-2. 16-Bit Timer With Prescaler Configurations ..................................................................... 169
Table 9-3. Timers Register Map ...................................................................................................... 175
Table 10-1. Watchdog Timer Register Map ........................................................................................ 202
Table 11-1. Samples and FIFO Depth of Sequencers ........................................................................ 225
Table 11-2. ADC Register Map ......................................................................................................... 229
Table 12-1. UART Register Map ....................................................................................................... 262
Table 13-1. SSI Register Map .......................................................................................................... 305
Table 14-1. Comparator 0 Operating Modes ..................................................................................... 333
Table 14-2. Comparator 1 Operating Modes ...................................................................................... 334
Table 14-3. Internal Reference Voltage and ACREFCTL Field Values ................................................. 334
Table 14-4. Analog Comparators Register Map ................................................................................. 336
Table 15-1. PWM Register Map ........................................................................................................ 349
Table 17-1. Signals by Pin Number ................................................................................................... 380
Table 17-2. Signals by Signal Name ................................................................................................. 382
Table 17-3. Signals by Function, Except for GPIO ............................................................................. 384
Table 17-4. GPIO Pins and Alternate Functions ................................................................................. 385
Table 18-1. Temperature Characteristics ........................................................................................... 386
Table 18-2. Thermal Characteristics ................................................................................................. 386
Table 19-1. Maximum Ratings .......................................................................................................... 387
Table 19-2. Recommended DC Operating Conditions ........................................................................ 387
Table 19-3. LDO Regulator Characteristics ....................................................................................... 388
Table 19-4. Detailed Power Specifications ........................................................................................ 388
Table 19-5. Flash Memory Characteristics ........................................................................................ 389
Table 19-6. Phase Locked Loop (PLL) Characteristics ....................................................................... 389
Table 19-7. Clock Characteristics ..................................................................................................... 389
Table 19-8. ADC Characteristics ....................................................................................................... 390
Table 19-9. Analog Comparator Characteristics ................................................................................. 390
Table 19-10. Analog Comparator Voltage Reference Characteristics .................................................... 390
Table 19-11. SSI Characteristics ........................................................................................................ 391
Table 19-12. JTAG Characteristics ..................................................................................................... 392
Table 19-13. GPIO Characteristics ..................................................................................................... 394
Table 19-14. Reset Characteristics ..................................................................................................... 394
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LM3S301 Microcontroller
Table C-1. Part Ordering Information ............................................................................................... 417
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Table of Contents
List of Registers
System Control .............................................................................................................................. 52
Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 61
Register 2: Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030 .................................... 63
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 64
Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 65
Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 66
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 68
Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 69
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 70
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 75
Register 10: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 76
Register 11: Clock Verification Clear (CLKVCLR), offset 0x150 ............................................................. 77
Register 12: Allow Unregulated LDO to Reset the Part (LDOARST), offset 0x160 ................................... 78
Register 13: Device Identification 1 (DID1), offset 0x004 ....................................................................... 79
Register 14: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 81
Register 15: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 82
Register 16: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 84
Register 17: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 86
Register 18: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 88
Register 19: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 89
Register 20: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 91
Register 21: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 93
Register 22: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 .................................... 95
Register 23: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 .................................. 97
Register 24: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ......................... 99
Register 25: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 101
Register 26: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 103
Register 27: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 105
Register 28: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 107
Register 29: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 108
Register 30: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 109
Internal Memory ........................................................................................................................... 110
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 116
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 117
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 118
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 120
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 121
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 122
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 123
Register 8: Flash Memory Protection Read Enable (FMPRE), offset 0x130 ......................................... 124
Register 9: Flash Memory Protection Program Enable (FMPPE), offset 0x134 .................................... 125
General-Purpose Input/Outputs (GPIOs) ................................................................................... 126
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 134
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 135
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 136
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LM3S301 Microcontroller
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 137
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 138
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 139
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 140
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 141
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 142
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 143
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 145
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 146
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 147
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 148
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 149
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 150
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 151
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 152
Register 19: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 153
Register 20: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 154
Register 21: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 155
Register 22: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 156
Register 23: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 157
Register 24: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 158
Register 25: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 159
Register 26: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 160
Register 27: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 161
Register 28: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 162
Register 29: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 163
Register 30: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 164
General-Purpose Timers ............................................................................................................. 165
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 177
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 178
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 180
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 182
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 185
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 187
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 188
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 189
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 191
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 192
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 193
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 194
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 195
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 196
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 197
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 198
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 199
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 200
Watchdog Timer ........................................................................................................................... 201
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 204
Preliminary
13November 29, 2007
Table of Contents
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 205
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 206
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 207
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 208
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 209
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 210
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 211
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 212
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 213
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 214
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 215
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 216
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 217
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 218
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 219
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 220
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 221
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 222
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 223
Analog-to-Digital Converter (ADC) ............................................................................................. 224
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 231
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 232
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 233
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 234
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 235
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 236
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 239
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 240
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 241
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 242
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 243
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 245
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 248
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 248
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 248
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 248
Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 249
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 249
Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 249
Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 249
Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 250
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 250
Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 251
Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 251
Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 253
Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 254
Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 255
Preliminary
November 29, 200714
LM3S301 Microcontroller
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 257
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 264
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 266
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 268
Register 4: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 270
Register 5: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 271
Register 6: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 272
Register 7: UART Control (UARTCTL), offset 0x030 ......................................................................... 274
Register 8: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 275
Register 9: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 277
Register 10: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 279
Register 11: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 280
Register 12: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 281
Register 13: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 283
Register 14: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 284
Register 15: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 285
Register 16: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 286
Register 17: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 287
Register 18: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 288
Register 19: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 289
Register 20: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 290
Register 21: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 291
Register 22: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 292
Register 23: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 293
Register 24: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 294
Synchronous Serial Interface (SSI) ............................................................................................ 295
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 307
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 309
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 311
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 312
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 314
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 315
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 317
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 318
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 319
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 320
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 321
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 322
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 323
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 324
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 325
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 326
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 327
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 328
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 329
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 330
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 331
Preliminary
15November 29, 2007
Table of Contents
Analog Comparators ................................................................................................................... 332
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 337
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 338
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 339
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 340
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 341
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40 ....................................................... 341
Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 342
Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x44 ....................................................... 342
Pulse Width Modulator (PWM) .................................................................................................... 344
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 351
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 352
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 353
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 354
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 355
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 356
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 357
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 358
Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 359
Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 360
Register 11: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 .................................... 362
Register 12: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 364
Register 13: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 365
Register 14: PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 366
Register 15: PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 367
Register 16: PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 368
Register 17: PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 369
Register 18: PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 370
Register 19: PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 373
Register 20: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 376
Register 21: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 377
Register 22: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 378
Preliminary
November 29, 200716
About This Document
This data sheet provides reference information for the LM3S301 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following documents are referenced by the data sheet, and available on the documentation CD
or from the Luminary Micro web site at www.luminarymicro.com:
■
ARM® Cortex™-M3 Technical Reference Manual
LM3S301 Microcontroller
■
ARM® CoreSight Technical Reference Manual
■
ARM® v7-M Architecture Application Level Reference Manual
The following related documents are also referenced:
■
IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the Luminary Micro web
site for additional documentation, including application notes and white papers.
Documentation Conventions
This document uses the conventions shown in Table 1 on page 17.
Table 1. Documentation Conventions
MeaningNotation
General Register Notation
REGISTER
offset 0xnnn
Register N
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
A single bit in a register.bit
Two or more consecutive and related bits.bit field
A hexadecimal increment to a register's address, relative to that module's base address as specified
in “Memory Map” on page 38.
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
Preliminary
17November 29, 2007
About This Document
reserved
yy:xx
Register Bit/Field
Types
R/W1C
W1C
Reset Value
Pin/Signal Notation
assert a signal
SIGNAL
SIGNAL
Numbers
X
0x
MeaningNotation
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.RC
Software can read this field. Always write the chip reset value.RO
Software can read or write this field.R/W
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
Only a write by software is valid; a read of the register returns no meaningful data.WO
This value in the register bit diagram shows the bit/field value after any reset, unless noted.Register Bit/Field
Bit cleared to 0 on chip reset.0
Bit set to 1 on chip reset.1
Nondeterministic.-
Pin alternate function; a pin defaults to the signal without the brackets.[ ]
Refers to the physical connection on the package.pin
Refers to the electrical signal encoding of a pin.signal
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
Change the value of the signal from the logically True state to the logically False state.deassert a signal
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
Preliminary
November 29, 200718
1 Architectural Overview
The Luminary Micro Stellaris®family of microcontrollers—the first ARM® Cortex™-M3 based
controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller
applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to
legacy 8- and 16-bit devices, all in a package with a small footprint.
The LM3S301 microcontroller is targeted for industrial applications, including test and measurement
equipment, factory automation, HVAC and building control, motion control, medical instrumentation,
fire and security, and power/energy.
In addition, the LM3S301 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S301 microcontroller is code-compatible
to all members of the extensive Stellaris®family; providing flexibility to fit our customers' precise
needs.
Luminary Micro offers a complete solution to get to market quickly, with evaluation and development
boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong
support, sales, and distributor network.
LM3S301 Microcontroller
1.1 Product Features
The LM3S301 microcontroller includes the following product features:
■ 32-Bit RISC Performance
– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
– Thumb®-compatible Thumb-2-only instruction set processor core for high code density
– 20-MHz operation
– Hardware-division and single-cycle-multiplication
– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
– 21 interrupts with eight priority levels
– Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
– Unaligned data access, enabling data to be efficiently packed into memory
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
■ Internal Memory
Preliminary
19November 29, 2007
Architectural Overview
16 KB single-cycle flash–
• User-managed flash block protection on a 2-KB block basis
• User-managed flash data programming
• User-defined and managed flash-protection block
– 2 KB single-cycle SRAM
■ General-Purpose Timers
– Two General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers.
Each GPTM can be configured to operate independently:
• As a single 32-bit timer
• As one 32-bit Real-Time Clock (RTC) to event capture
• For Pulse Width Modulation (PWM)
• To trigger analog-to-digital conversions
– 32-bit Timer modes
• Programmable one-shot timer
• Programmable periodic timer
• Real-Time Clock when using an external 32.768-KHz clock as the input
• User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU
Halt flag during debug
• ADC event trigger
– 16-bit Timer modes
• General-purpose timer function with an 8-bit prescaler
• Programmable one-shot timer
• Programmable periodic timer
• User-enabled stalling when the controller asserts CPU Halt flag during debug
• ADC event trigger
– 16-bit Input Capture modes
• Input edge count capture
• Input edge time capture
– 16-bit PWM mode
• Simple PWM mode with software-programmable output inversion of the PWM signal
November 29, 200720
Preliminary
LM3S301 Microcontroller
■ ARM FiRM-compliant Watchdog Timer
– 32-bit down counter with a programmable load register
– Separate watchdog clock with an enable
– Programmable interrupt generation logic with interrupt masking
– Lock register protection from runaway software
– Reset generation logic with an enable/disable
– User-enabled stalling when the controller asserts the CPU Halt flag during debug
■ Synchronous Serial Interface (SSI)
– Master or slave operation
– Programmable clock bit rate and prescale
– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
– Programmable data frame size from 4 to 16 bits
– Internal loopback test mode for diagnostic/debug testing
■ UART
– Fully programmable 16C550-type UART
– Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service
loading
– Programmable baud-rate generator with fractional divider
– Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
– Standard asynchronous communication bits for start, stop, and parity
– False-start-bit detection
– Line-break generation and detection
■ ADC
– Single- and differential-input configurations
– Three 10-bit channels (inputs) when used as single-ended inputs
– Sample rate of 250 thousand samples/second
Preliminary
21November 29, 2007
Architectural Overview
– Flexible, configurable analog-to-digital conversion
– Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
– Each sequence triggered by software or internal event (timers, analog comparators, PWM
or GPIO)
– On-chip temperature sensor
■ Analog Comparators
– Two independent integrated analog comparators
– Configurable for output to: drive an output pin, generate an interrupt, or initiate an ADC sample
sequence
– Compare external pin input to external pin input or to internal programmable voltage reference
■ PWM
– One PWM generator blocks, each with one 16-bit counter, two comparators, a PWM generator,
and a dead-band generator
– One 16-bit counter
• Runs in Down or Up/Down mode
• Output frequency controlled by a 16-bit load value
• Load value updates can be synchronized
• Produces output signals at zero and load value
– Two PWM comparators
• Comparator value updates can be synchronized
• Produces output signals on match
– PWM generator
• Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals
• Produces two independent PWM signals
– Dead-band generator
• Produces two PWM signals with programmable dead-band delays suitable for driving a
half-H bridge
• Can be bypassed, leaving input PWM signals unmodified
– Flexible output control block with PWM output enable of each PWM signal
Preliminary
November 29, 200722
LM3S301 Microcontroller
• PWM output enable of each PWM signal
• Optional output inversion of each PWM signal (polarity control)
• Optional fault handling for each PWM signal
• Synchronization of timers in the PWM generator blocks
• Synchronization of timer/comparator updates across the PWM generator blocks
• Interrupt status summary of the PWM generator blocks
– Can initiate an ADC sample sequence
■ GPIOs
– 12-33 GPIOs, depending on configuration
– 5-V-tolerant input/outputs
– Programmable interrupt generation as either edge-triggered or level-sensitive
– Bit masking in both read and write operations through address lines
– Can initiate an ADC sample sequence
– Programmable control for GPIO pad configuration:
• Weak pull-up or pull-down resistors
• 2-mA, 4-mA, and 8-mA pad drive
• Slew rate control for the 8-mA drive
• Open drain enables
• Digital input enables
■ Power
– On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
– Low-power options on controller: Sleep and Deep-sleep modes
– Low-power options for peripherals: software controls shutdown of individual peripherals
– User-enabled LDO unregulated voltage detection and automatic reset
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Flexible Reset Sources
– Power-on reset (POR)
– Reset pin assertion
Preliminary
23November 29, 2007
Architectural Overview
– Brown-out (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
– Internal low drop-out (LDO) regulator output goes unregulated
■ Additional Features
– Six reset sources
– Programmable clock source control
– Clock gating to individual peripherals for power savings
– IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
– Debug access via JTAG and Serial Wire interfaces
– Full JTAG boundary scan
■ Industrial-range 48-pin RoHS-compliant LQFP package
1.2 Target Applications
■ Factory automation and control
■ Industrial control power devices
■ Building and home automation
■ Stepper motors
■ Brushless DC motors
■ AC induction motors
1.3 High-Level Block Diagram
Figure 1-1 on page 25 represents the full set of features in the Stellaris®300 series of devices; not
all features may be available on the LM3S301 microcontroller.
Preliminary
November 29, 200724
Figure 1-1. Stellaris®300 Series High-Level Block Diagram
LM3S301 Microcontroller
1.4 Functional Overview
The following sections provide an overview of the features of the LM3S301 microcontroller. The
page number in parenthesis indicates where that feature is discussed in detail. Ordering and support
information can be found in “Ordering and Contact Information” on page 417.
25November 29, 2007
Preliminary
Architectural Overview
1.4.1 ARM Cortex™-M3
1.4.1.1 Processor Core (see page 32)
All members of the Stellaris®product family, including the LM3S301 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
“ARM Cortex-M3 Processor Core” on page 32 provides an overview of the ARM core; the core is
detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.1.2 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
1.4.1.3 Nested Vectored Interrupt Controller (NVIC)
The LM3S301 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the ARM
Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions are
handled in Handler Mode. The processor state is automatically stored to the stack on an exception,
and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The
vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor
supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead
of state saving and restoration. Software can set eight priority levels on 7 exceptions (system
handlers) and 21 interrupts.
“Interrupts” on page 40 provides an overview of the NVIC controller and the interrupt map. Exceptions
and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.2 Motor Control Peripherals
To enhance motor control, the LM3S301 controller features Pulse Width Modulation (PWM) outputs.
1.4.2.1 PWM
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
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Preliminary
On the LM3S301, PWM motion control functionality can be achieved through:
■ Dedicated, flexible motion control hardware using the PWM pins
■ The motion control features of the general-purpose timers using the CCP pins
PWM Pins (see page 344)
The LM3S301 PWM module consists of one PWM generator blocks and a control block. Each PWM
generator block contains one timer (16-bit down or up/down counter), two comparators, a PWM
signal generator, a dead-band generator, and an interrupt/ADC-trigger selector. The control block
determines the polarity of the PWM signals, and which signals are passed through to the pins.
Each PWM generator block produces two PWM signals that can either be independent signals or
a single pair of complementary signals with dead-band delays inserted. The output of the PWM
generation blocks are managed by the output control block before being passed to the device pins.
CCP Pins (see page 171)
The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable
to support a simple PWM mode with a software-programmable output inversion of the PWM signal.
1.4.3 Analog Peripherals
LM3S301 Microcontroller
To handle analog signals, the LM3S301 microcontroller offers an Analog-to-Digital Converter (ADC).
For support of analog signals, the LM3S301 microcontroller offers two analog comparators.
1.4.3.1 ADC (see page 224)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number.
The LM3S301 ADC module features 10-bit conversion resolution and supports three input channels,
plus an internal temperature sensor. Four buffered sample sequences allow rapid sampling of up
to eight analog input sources without controller intervention. Each sample sequence provides flexible
programming with fully configurable input source, trigger events, interrupt generation, and sequence
priority.
1.4.3.2 Analog Comparators (see page 332)
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
The LM3S301 microcontroller provides two independent integrated analog comparators that can
be configured to drive an output or generate an interrupt or ADC event.
A comparator can compare a test voltage against any one of these voltages:
■ An individual external reference voltage
■ A shared single external reference voltage
■ A shared internal reference voltage
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
27November 29, 2007
Preliminary
Architectural Overview
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.
1.4.4 Serial Communications Peripherals
The LM3S301 controller supports both asynchronous and synchronous serial communications with:
■ One fully programmable 16C550-type UART
■ One SSI module
1.4.4.1 UART (see page 257)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S301 controller includes one fully programmable 16C550-type UARTthat supports data
transfer speeds up to 460.8 Kbps. (Although similar in functionality to a 16C550 UART, it is not
register-compatible.)
Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading.
The UART can generate individually masked interrupts from the RX, TX, modem status, and error
conditions. The module provides a single combined interrupt when any of the interrupts are asserted
and are unmasked.
1.4.4.2 SSI (see page 295)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface.
The LM3S301 controller includes one SSI module that provides the functionality for synchronous
serial communications with peripheral devices, and can be configured to use the Freescale SPI,
MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also
configurable, and can be set between 4 and 16 bits, inclusive.
The SSI module performs serial-to-parallel conversion on data received from a peripheral device,
and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths
are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently.
The SSI module can be configured as either a master or slave device. As a slave device, the SSI
module can also be configured to disable its output, which allows a master device to be coupled
with multiple slave devices.
The SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
1.4.5 System Peripherals
1.4.5.1 Programmable GPIOs (see page 126)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections.
The Stellaris®GPIO module is composed of five physical GPIO blocks, each corresponding to an
individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP
for Real-Time Microcontrollers specification) and supports 12-33 programmable input/output pins.
The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page
380 for the signals available to each GPIO pin).
Preliminary
November 29, 200728
The GPIO module features programmable interrupt generation as either edge-triggered or
level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in
both read and write operations through address lines.
1.4.5.2 Two Programmable Timers (see page 165)
Programmable timers can be used to count or time external events that drive the Timer input pins.
The Stellaris®General-Purpose Timer Module (GPTM) contains two GPTM blocks. Each GPTM
block provides two 16-bit timers/counters that can be configured to operate independently as timers
or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
Timers can also be used to trigger analog-to-digital (ADC) conversions.
When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or
periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can
extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event
capture or Pulse Width Modulation (PWM) generation.
1.4.5.3 Watchdog Timer (see page 201)
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or to the failure of an external device to respond in the expected way.
LM3S301 Microcontroller
The Stellaris®Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, and a locking register.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
1.4.6 Memory Peripherals
The LM3S301 controller offers both single-cycle SRAM and single-cycle Flash memory.
1.4.6.1 SRAM (see page 110)
The LM3S301 static random access memory (SRAM) controller supports 2 KB SRAM. The internal
SRAM of the Stellaris®devices is located at offset 0x0000.0000 of the device memory map. To
reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced
bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
1.4.6.2 Flash (see page 111)
The LM3S301 Flash controller supports 16 KB of flash memory. The flash is organized as a set of
1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block
to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually
protected. The blocks can be marked as read-only or execute-only, providing different levels of code
protection. Read-only blocks cannot be erased or programmed, protecting the contents of those
blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only
be read by the controller instruction fetch mechanism, protecting the contents of those blocks from
being read by either the controller or by a debugger.
Preliminary
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Architectural Overview
1.4.7 Additional Features
1.4.7.1 Memory Map (see page 38)
A memory map lists the location of instructions and data in memory. The memory map for the
LM3S301 controller can be found in “Memory Map” on page 38. Register addresses are given as
a hexadecimal increment, relative to the module's base address as shown in the memory map.
The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory
map.
1.4.7.2 JTAG TAP Controller (see page 42)
The Joint Test Action Group (JTAG) port provides a standardized serial interface for controlling the
Test Access Port (TAP) and associated test logic. The TAP, JTAG instruction register, and JTAG
data registers can be used to test the interconnects of assembled printed circuit boards, obtain
manufacturing information on the components, and observe and/or control the inputs and outputs
of the controller during normal operation. The JTAG port provides a high degree of testability and
chip-level access at a low cost.
The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is
transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of
this data is dependent on the current state of the TAP controller. For detailed information on the
operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test
Access Port and Boundary-Scan Architecture.
The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3
core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary
Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has
comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions.
1.4.7.3 System Control and Clocks (see page 52)
System control determines the overall operation of the device. It provides information about the
device, controls the clocking of the device and individual peripherals, and handles reset detection
and reporting.
1.4.8 Hardware Details
Details on the pins and package can be found in the following sections:
■ “Pin Diagram” on page 379
■ “Signal Tables” on page 380
■ “Operating Characteristics” on page 386
■ “Electrical Characteristics” on page 387
■ “Package Information” on page 397
Preliminary
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