TEXAS INSTRUMENTS LM3S2412 Technical data
PRELIMINARY
LM3S2412 Microcontroller
DATA SHEET
Copyright © 2007 Luminary Micro, Inc.DS-LM3S2412-03
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Preliminary
June 26, 20072
LM3S2412 Microcontroller
Table of Contents
About This Document .................................................................................................................... 19
Audience .............................................................................................................................................. 19
About This Manual ................................................................................................................................ 19
Related Documents ............................................................................................................................... 19
Documentation Conventions .................................................................................................................. 19
1 Overview ............................................................................................................................. 21
1.1 Product Features ...................................................................................................................... 21
1.2 Target Applications .................................................................................................................... 26
1.3 High-Level Block Diagram ......................................................................................................... 27
1.4 Functional Overview .................................................................................................................. 28
1.4.1 ARM Cortex™-M3 ..................................................................................................................... 29
1.4.2 Motor Control Peripherals .......................................................................................................... 29
1.4.3 Serial Communications Peripherals ............................................................................................ 30
1.4.4 System Peripherals ................................................................................................................... 31
1.4.5 Memory Peripherals .................................................................................................................. 32
1.4.6 Additional Features ................................................................................................................... 33
1.4.7 Hardware Details ...................................................................................................................... 33
2 Cortex-M3 Core .................................................................................................................. 34
2.1 Block Diagram .......................................................................................................................... 35
2.2 Functional Description ............................................................................................................... 35
2.2.1 Serial Wire and JTAG Debug ..................................................................................................... 35
2.2.2 Embedded Trace Macrocell (ETM) ............................................................................................. 36
2.2.3 Trace Port Interface Unit (TPIU) ................................................................................................. 36
2.2.4 ROM Table ............................................................................................................................... 36
2.2.5 Memory Protection Unit (MPU) ................................................................................................... 36
2.2.6 Nested Vectored Interrupt Controller (NVIC) ................................................................................ 36
3 Memory Map ....................................................................................................................... 40
4 Interrupts ............................................................................................................................ 42
5 JTAG .................................................................................................................................... 44
5.1 Block Diagram .......................................................................................................................... 45
5.2 Functional Description ............................................................................................................... 45
5.2.1 JTAG Interface Pins .................................................................................................................. 46
5.2.2 JTAG TAP Controller ................................................................................................................. 47
5.2.3 Shift Registers .......................................................................................................................... 48
5.2.4 Operational Considerations ........................................................................................................ 48
5.3 Initialization and Configuration ................................................................................................... 51
5.4 Register Descriptions ................................................................................................................ 51
5.4.1 Instruction Register (IR) ............................................................................................................. 51
5.4.2 Data Registers .......................................................................................................................... 53
6 System Control ................................................................................................................... 55
6.1 Functional Description ............................................................................................................... 55
6.1.1 Device Identification .................................................................................................................. 55
6.1.2 Reset Control ............................................................................................................................ 55
6.1.3 Power Control ........................................................................................................................... 58
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Table of Contents
6.1.4 Clock Control ............................................................................................................................ 58
6.1.5 System Control ......................................................................................................................... 60
6.2 Initialization and Configuration ................................................................................................... 60
6.3 Register Map ............................................................................................................................ 61
6.4 Register Descriptions ................................................................................................................ 62
7 Internal Memory ............................................................................................................... 110
7.1 Block Diagram ........................................................................................................................ 110
7.2 Functional Description ............................................................................................................. 110
7.2.1 SRAM Memory ........................................................................................................................ 110
7.2.2 Flash Memory ......................................................................................................................... 111
7.3 Flash Memory Initialization and Configuration ........................................................................... 112
7.3.1 Flash Programming ................................................................................................................. 112
7.3.2 Nonvolatile Register Programming ........................................................................................... 113
7.4 Register Map .......................................................................................................................... 113
7.5 Flash Control Offset ................................................................................................................. 114
7.6 System Control Offset .............................................................................................................. 121
8 GPIO .................................................................................................................................. 134
8.1 Function Description ................................................................................................................ 134
8.1.1 Data Control ........................................................................................................................... 134
8.1.2 Interrupt Control ...................................................................................................................... 135
8.1.3 Mode Control .......................................................................................................................... 136
8.1.4 Commit Control ....................................................................................................................... 136
8.1.5 Pad Control ............................................................................................................................. 136
8.1.6 Identification ........................................................................................................................... 137
8.2 Initialization and Configuration ................................................................................................. 137
8.3 Register Map .......................................................................................................................... 138
8.4 Register Descriptions .............................................................................................................. 140
9 Timers ............................................................................................................................... 175
9.1 Block Diagram ........................................................................................................................ 176
9.2 Functional Description ............................................................................................................. 176
9.2.1 GPTM Reset Conditions .......................................................................................................... 176
9.2.2 32-Bit Timer Operating Modes .................................................................................................. 176
9.2.3 16-Bit Timer Operating Modes .................................................................................................. 178
9.3 Initialization and Configuration ................................................................................................. 182
9.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 182
9.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 183
9.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 183
9.3.4 16-Bit Input Edge Count Mode ................................................................................................. 184
9.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 184
9.3.6 16-Bit PWM Mode ................................................................................................................... 185
9.4 Register Map .......................................................................................................................... 185
9.5 Register Descriptions .............................................................................................................. 186
10 Watchdog Timer ............................................................................................................... 208
10.1 Block Diagram ........................................................................................................................ 208
10.2 Functional Description ............................................................................................................. 208
10.3 Initialization and Configuration ................................................................................................. 209
10.4 Register Map .......................................................................................................................... 209
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LM3S2412 Microcontroller
10.5 Register Descriptions .............................................................................................................. 210
11 ADC ................................................................................................................................... 231
11.1 Block Diagram ........................................................................................................................ 232
11.2 Functional Description ............................................................................................................. 232
11.2.1 Sample Sequencers ................................................................................................................ 232
11.2.2 Module Control ........................................................................................................................ 233
11.2.3 Hardware Sample Averaging Circuit ......................................................................................... 234
11.2.4 Analog-to-Digital Converter ...................................................................................................... 234
11.2.5 Test Modes ............................................................................................................................. 234
11.2.6 Internal Temperature Sensor .................................................................................................... 234
11.3 Initialization and Configuration ................................................................................................. 235
11.3.1 Module Initialization ................................................................................................................. 235
11.3.2 Sample Sequencer Configuration ............................................................................................. 235
11.4 Register Map .......................................................................................................................... 236
11.5 Register Descriptions .............................................................................................................. 237
12 UART ................................................................................................................................. 268
12.1 Block Diagram ........................................................................................................................ 269
12.2 Functional Description ............................................................................................................. 269
12.2.1 Transmit/Receive Logic ........................................................................................................... 269
12.2.2 Baud-Rate Generation ............................................................................................................. 270
12.2.3 Data Transmission .................................................................................................................. 271
12.2.4 Serial IR (SIR) ......................................................................................................................... 271
12.2.5 FIFO Operation ....................................................................................................................... 272
12.2.6 Interrupts ................................................................................................................................ 272
12.2.7 Loopback Operation ................................................................................................................ 273
12.2.8 IrDA SIR block ........................................................................................................................ 273
12.3 Initialization and Configuration ................................................................................................. 273
12.4 Register Map .......................................................................................................................... 274
12.5 Register Descriptions .............................................................................................................. 275
13 SSI ..................................................................................................................................... 308
13.1 Block Diagram ........................................................................................................................ 308
13.2 Functional Description ............................................................................................................. 308
13.2.1 Bit Rate Generation ................................................................................................................. 309
13.2.2 FIFO Operation ....................................................................................................................... 309
13.2.3 Interrupts ................................................................................................................................ 309
13.2.4 Frame Formats ....................................................................................................................... 310
13.3 Initialization and Configuration ................................................................................................. 317
13.4 Register Map .......................................................................................................................... 318
13.5 Register Descriptions .............................................................................................................. 319
14 Inter-Integrated Circuit (I2C) Interface ............................................................................ 342
14.1 Block Diagram ........................................................................................................................ 342
14.2 Functional Description ............................................................................................................. 342
14.2.1 I2C Bus Functional Overview .................................................................................................... 343
14.2.2 Available Speed Modes ........................................................................................................... 345
14.2.3 Interrupts ................................................................................................................................ 346
14.2.4 Loopback Operation ................................................................................................................ 346
14.2.5 Command Sequence Flow Charts ............................................................................................ 346
Preliminary
5June 26, 2007
Table of Contents
14.3 Initialization and Configuration ................................................................................................. 353
14.4 I2C Register Map ..................................................................................................................... 354
14.5 I2C Master .............................................................................................................................. 355
14.6 I2C Slave ................................................................................................................................ 368
15 CAN ................................................................................................................................... 377
15.1 Controller Area Network Overview ............................................................................................ 377
15.2 Controller Area Network Features ............................................................................................ 377
15.3 Controller Area Network Block Diagram .................................................................................... 378
15.4 Controller Area Network Functional Description ......................................................................... 379
15.4.1 Initialization ............................................................................................................................. 379
15.4.2 Operation ............................................................................................................................... 380
15.4.3 Transmitting Message Objects ................................................................................................. 380
15.4.4 Configuring a Transmit Message Object .................................................................................... 380
15.4.5 Updating a Transmit Message Object ....................................................................................... 381
15.4.6 Accepting Received Message Objects ...................................................................................... 381
15.4.7 Receiving a Data Frame .......................................................................................................... 382
15.4.8 Receiving a Remote Frame ...................................................................................................... 382
15.4.9 Receive/Transmit Priority ......................................................................................................... 382
15.4.10 Configuring a Receive Message Object .................................................................................... 382
15.4.11 Handling of Received Message Objects .................................................................................... 383
15.4.12 Handling of Interrupts .............................................................................................................. 383
15.4.13 Bit Timing Configuration Error Considerations ........................................................................... 384
15.4.14 Bit Time and Bit Rate ............................................................................................................... 384
15.4.15 Calculating the Bit Timing Parameters ...................................................................................... 386
15.5 Controller Area Network Register Map ...................................................................................... 388
15.6 Register Descriptions .............................................................................................................. 390
16 Analog Comparators ....................................................................................................... 421
16.1 Block Diagram ........................................................................................................................ 421
16.2 Functional Description ............................................................................................................. 422
16.2.1 Internal Reference Programming .............................................................................................. 423
16.3 Initialization and Configuration ................................................................................................. 424
16.4 Register Map .......................................................................................................................... 424
16.5 Register Descriptions .............................................................................................................. 425
17 PWM .................................................................................................................................. 433
17.1 Block Diagram ........................................................................................................................ 433
17.2 Functional Description ............................................................................................................. 433
17.2.1 PWM Timer ............................................................................................................................. 433
17.2.2 PWM Comparators .................................................................................................................. 434
17.2.3 PWM Signal Generator ............................................................................................................ 435
17.2.4 Dead-Band Generator ............................................................................................................. 436
17.2.5 Interrupt/ADC-Trigger Selector ................................................................................................. 436
17.2.6 Synchronization Methods ......................................................................................................... 436
17.2.7 Fault Conditions ...................................................................................................................... 437
17.2.8 Output Control Block ............................................................................................................... 437
17.3 Initialization and Configuration ................................................................................................. 437
17.4 Register Map .......................................................................................................................... 438
17.5 Register Descriptions .............................................................................................................. 439
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LM3S2412 Microcontroller
18 Pin Diagram ...................................................................................................................... 466
19 Signal Tables .................................................................................................................... 467
20 Operating Characteristics ............................................................................................... 479
21 Electrical Characteristics ................................................................................................ 480
21.1 DC Characteristics .................................................................................................................. 480
21.1.1 Maximum Ratings ................................................................................................................... 480
21.1.2 Recommended DC Operating Conditions .................................................................................. 480
21.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 481
21.1.4 Power Specifications ............................................................................................................... 481
21.1.5 Flash Memory Characteristics .................................................................................................. 482
21.2 AC Characteristics ................................................................................................................... 483
21.2.1 Load Conditions ...................................................................................................................... 483
21.2.2 Clocks .................................................................................................................................... 483
21.2.3 Temperature Sensor ................................................................................................................ 484
21.2.4 Analog-to-Digital Converter ...................................................................................................... 484
21.2.5 Analog Comparator ................................................................................................................. 484
21.2.6 I2C ......................................................................................................................................... 485
21.2.7 Synchronous Serial Interface (SSI) ........................................................................................... 485
21.2.8 JTAG and Boundary Scan ........................................................................................................ 487
21.2.9 General-Purpose I/O ............................................................................................................... 488
21.2.10 Reset ..................................................................................................................................... 489
22 Package Information ........................................................................................................ 491
A Serial Flash Loader .......................................................................................................... 493
A.1 Serial Flash Loader ................................................................................................................. 493
A.2 Interfaces ............................................................................................................................... 493
A.2.1 UART ..................................................................................................................................... 493
A.2.2 SSI ......................................................................................................................................... 493
A.3 Packet Handling ...................................................................................................................... 494
A.3.1 Packet Format ........................................................................................................................ 494
A.3.2 Sending Packets ..................................................................................................................... 494
A.3.3 Receiving Packets ................................................................................................................... 494
A.4 Commands ............................................................................................................................. 495
A.4.1 COMMAND_PING (0X20) ........................................................................................................ 495
A.4.2 COMMAND_GET_STATUS (0x23) ........................................................................................... 495
A.4.3 COMMAND_DOWNLOAD (0x21) ............................................................................................. 495
A.4.4 COMMAND_SEND_DATA (0x24) ............................................................................................. 496
A.4.5 COMMAND_RUN (0x22) ......................................................................................................... 496
A.4.6 COMMAND_RESET (0x25) ..................................................................................................... 496
B Ordering Information ....................................................................................................... 498
B.1 Ordering Information ................................................................................................................ 498
B.2 Company Information .............................................................................................................. 498
B.3 Support Information ................................................................................................................. 498
Preliminary
7June 26, 2007
Table of Contents
List of Figures
Figure 1-1. Stellaris® Fury-class High-Level Block Diagram ................................................................ 28
Figure 2-1. CPU Block Diagram ......................................................................................................... 35
Figure 2-2. TPIU Block Diagram ........................................................................................................ 36
Figure 5-1. JTAG Module Block Diagram ............................................................................................ 45
Figure 5-2. Test Access Port State Machine ....................................................................................... 48
Figure 5-3. IDCODE Register Format ................................................................................................. 53
Figure 5-4. BYPASS Register Format ................................................................................................ 54
Figure 5-5. Boundary Scan Register Format ....................................................................................... 54
Figure 6-1. External Circuitry to Extend Reset .................................................................................... 56
Figure 7-1. Flash Block Diagram ...................................................................................................... 110
Figure 8-1. GPIODATA Write Example ............................................................................................. 135
Figure 8-2. GPIODATA Read Example ............................................................................................. 135
Figure 9-1. GPTM Module Block Diagram ........................................................................................ 176
Figure 9-2. 16-Bit Input Edge Count Mode Example .......................................................................... 180
Figure 9-3. 16-Bit Input Edge Time Mode Example ........................................................................... 181
Figure 9-4. 16-Bit PWM Mode Example ............................................................................................ 182
Figure 10-1. WDT Module Block Diagram .......................................................................................... 208
Figure 11-1. ADC Module Block Diagram ........................................................................................... 232
Figure 11-2. Internal Temperature Sensor Characteristic ..................................................................... 235
Figure 12-1. UART Module Block Diagram ......................................................................................... 269
Figure 12-2. UART Character Frame ................................................................................................. 270
Figure 12-3. IrDA Data Modulation ..................................................................................................... 272
Figure 13-1. SSI Module Block Diagram ............................................................................................. 308
Figure 13-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 311
Figure 13-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 311
Figure 13-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 312
Figure 13-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 312
Figure 13-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 313
Figure 13-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 314
Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 314
Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 315
Figure 13-10. MICROWIRE Frame Format (Single Frame) .................................................................... 316
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 317
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 317
Figure 14-1. I2C Block Diagram ......................................................................................................... 342
Figure 14-2. I2C Bus Configuration .................................................................................................... 343
Figure 14-3. START and STOP Conditions ......................................................................................... 343
Figure 14-4. Complete Data Transfer with a 7-Bit Address ................................................................... 344
Figure 14-5. R/S Bit in First Byte ........................................................................................................ 344
Figure 14-6. Data Validity During Bit Transfer on the I2C Bus ............................................................... 344
Figure 14-7. Master Single SEND ...................................................................................................... 347
Figure 14-8. Master Single RECEIVE ................................................................................................. 348
Figure 14-9. Master Burst SEND ....................................................................................................... 349
Figure 14-10. Master Burst RECEIVE .................................................................................................. 350
Figure 14-11. Master Burst RECEIVE after Burst SEND ........................................................................ 351
Figure 14-12. Master Burst SEND after Burst RECEIVE ........................................................................ 352
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LM3S2412 Microcontroller
Figure 14-13. Slave Command Sequence ............................................................................................ 353
Figure 15-1. CAN Module Block Diagram ........................................................................................... 378
Figure 15-2. CAN Bit Time ................................................................................................................ 385
Figure 16-1. Analog Comparator Module Block Diagram ..................................................................... 421
Figure 16-2. Structure of Comparator Unit .......................................................................................... 422
Figure 16-3. Comparator Internal Reference Structure ........................................................................ 423
Figure 17-1. PWM Module Block Diagram .......................................................................................... 433
Figure 17-2. PWM Count-Down Mode ................................................................................................ 434
Figure 17-3. PWM Count-Up/Down Mode .......................................................................................... 435
Figure 17-4. PWM Generation Example In Count-Up/Down Mode ....................................................... 435
Figure 17-5. PWM Dead-Band Generator ........................................................................................... 436
Figure 18-1. Pin Connection Diagram ................................................................................................ 466
Figure 21-1. Load Conditions ............................................................................................................ 483
Figure 21-2. I2C Timing ..................................................................................................................... 485
Figure 21-3. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 486
Figure 21-4. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 486
Figure 21-5. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 487
Figure 21-6. JTAG Test Clock Input Timing ......................................................................................... 488
Figure 21-7. JTAG Test Access Port (TAP) Timing .............................................................................. 488
Figure 21-8. JTAG TRST Timing ........................................................................................................ 488
Figure 21-9. External Reset Timing (RST) .......................................................................................... 489
Figure 21-10. Power-On Reset Timing ................................................................................................. 490
Figure 21-11. Brown-Out Reset Timing ................................................................................................ 490
Figure 21-12. Software Reset Timing ................................................................................................... 490
Figure 21-13. Watchdog Reset Timing ................................................................................................. 490
Figure 22-1. 100-Pin LQFP Package .................................................................................................. 491
Preliminary
9June 26, 2007
Table of Contents
List of Tables
Table 1. Documentation Conventions ............................................................................................ 19
Table 3-1. Memory Map ................................................................................................................... 40
Table 4-1. Exception Types .............................................................................................................. 42
Table 4-2. Interrupts ........................................................................................................................ 43
Table 5-1. JTAG Port Pins Reset State ............................................................................................. 46
Table 5-2. JTAG Instruction Register Commands ............................................................................... 51
Table 6-1. System Control Register Map ........................................................................................... 61
Table 6-2. VADJ to VOUT ................................................................................................................ 66
Table 6-3. Default Crystal Field Values and PLL Programming ........................................................... 74
Table 7-1. Flash Protection Policy Combinations ............................................................................. 112
Table 7-2. Flash Resident Registers ............................................................................................... 113
Table 7-3. Internal Memory Register Map ........................................................................................ 113
Table 8-1. GPIO Pad Configuration Examples ................................................................................. 137
Table 8-2. GPIO Interrupt Configuration Example ............................................................................ 137
Table 8-3. GPIO Register Map ....................................................................................................... 139
Table 9-1. 16-Bit Timer With Prescaler Configurations ..................................................................... 179
Table 9-2. Timers Register Map ...................................................................................................... 185
Table 10-1. Watchdog Timer Register Map ........................................................................................ 209
Table 11-1. Samples and FIFO Depth of Sequencers ........................................................................ 232
Table 11-2. ADC Register Map ......................................................................................................... 236
Table 12-1. UART Register Map ....................................................................................................... 274
Table 13-1. SSI Register Map .......................................................................................................... 318
Table 14-1. Examples of I2C Master Timer Period versus Speed Mode ............................................... 345
Table 14-2. Inter-Integrated Circuit (I2C) Interface Register Map ......................................................... 354
Table 14-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 359
Table 15-1. Transmit Message Object Bit Settings ............................................................................. 381
Table 15-2. Receive Message Object Bit Settings .............................................................................. 383
Table 15-3. CAN Protocol Ranges .................................................................................................... 385
Table 15-4. CAN Register Map ......................................................................................................... 388
Table 16-1. Comparator 0 Operating Modes ...................................................................................... 422
Table 16-2. Comparator 1 Operating Modes ..................................................................................... 423
Table 16-3. Internal Reference Voltage and ACREFCTL Field Values ................................................. 423
Table 16-4. Analog Comparators Register Map ................................................................................. 425
Table 17-1. PWM Register Map ........................................................................................................ 438
Table 17-2. PWM Generator Action Encodings .................................................................................. 460
Table 19-1. Signals by Pin Number ................................................................................................... 467
Table 19-2. Signals by Signal Name ................................................................................................. 471
Table 19-3. Signals by Function, Except for GPIO ............................................................................. 475
Table 19-4. GPIO Pins and Alternate Functions ................................................................................. 477
Table 20-1. Temperature Characteristics ........................................................................................... 479
Table 20-2. Thermal Characteristics ................................................................................................. 479
Table 21-1. Maximum Ratings .......................................................................................................... 480
Table 21-2. Recommended DC Operating Conditions ........................................................................ 480
Table 21-3. LDO Regulator Characteristics ....................................................................................... 481
Table 21-4. Detailed Power Specifications ........................................................................................ 482
Table 21-5. Flash Memory Characteristics ........................................................................................ 482
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LM3S2412 Microcontroller
Table 21-6. Phase Locked Loop (PLL) Characteristics ....................................................................... 483
Table 21-7. Clock Characteristics ..................................................................................................... 483
Table 21-8. Crystal Characteristics ................................................................................................... 483
Table 21-9. Temperature Sensor Characteristics ............................................................................... 484
Table 21-10. ADC Characteristics ....................................................................................................... 484
Table 21-11. Analog Comparator Characteristics ................................................................................. 484
Table 21-12. Analog Comparator Voltage Reference Characteristics .................................................... 485
Table 21-13. I2C Characteristics ......................................................................................................... 485
Table 21-14. SSI Characteristics ........................................................................................................ 485
Table 21-15. JTAG Characteristics ..................................................................................................... 487
Table 21-16. GPIO Characteristics ..................................................................................................... 489
Table 21-17. Reset Characteristics ..................................................................................................... 489
Table B-1. Part Ordering Information ............................................................................................... 498
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Table of Contents
List of Registers
System Control .............................................................................................................................. 55
Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 63
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 65
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 66
Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 67
Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 68
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 69
Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 70
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 71
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 75
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 76
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 78
Register 12: Device Identification 1 (DID1), offset 0x004 ....................................................................... 79
Register 13: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 81
Register 14: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 82
Register 15: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 84
Register 16: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 86
Register 17: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 88
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 89
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 91
Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 93
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 .................................... 95
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 .................................. 97
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ......................... 99
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 101
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 103
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 105
Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 107
Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 108
Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 109
Internal Memory ........................................................................................................................... 110
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 115
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 116
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 117
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 119
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 120
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 121
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 122
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 123
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 124
Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 125
Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 126
Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 127
Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 128
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 129
Preliminary
June 26, 200712
LM3S2412 Microcontroller
Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 130
Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 131
Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 132
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 133
GPIO .............................................................................................................................................. 134
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 141
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 142
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 143
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 144
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 145
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 146
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 147
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 148
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 149
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 150
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 152
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 153
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 154
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 155
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 156
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 157
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 158
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 159
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 160
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 161
Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 163
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 164
Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 165
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 166
Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 167
Register 26: GPIO Peripheral Identification 1(GPIOPeriphID1), offset 0xFE4 ........................................ 168
Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 169
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 170
Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 171
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 172
Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 173
Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 174
Timers ........................................................................................................................................... 175
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 187
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 188
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 189
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 190
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 192
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 194
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 195
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 196
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 198
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 199
Preliminary
13June 26, 2007
Table of Contents
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 200
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 201
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 202
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 203
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 204
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 205
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 206
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 207
Watchdog Timer ........................................................................................................................... 208
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 211
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 212
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 213
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 214
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 215
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 216
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 217
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 218
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 219
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 220
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 221
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 222
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 223
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 224
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 225
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 226
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 227
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 228
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 229
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 230
ADC ............................................................................................................................................... 231
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 238
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 239
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 240
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 241
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 242
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 243
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 245
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 246
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 247
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 248
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 249
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 251
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 254
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 254
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 254
Register 16: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 255
Register 17: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 255
Register 18: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................. 255
Preliminary
June 26, 200714
LM3S2412 Microcontroller
Register 19: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 256
Register 20: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 257
Register 21: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 259
Register 22: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 260
Register 23: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 262
Register 24: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 263
Register 25: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 264
Register 26: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 265
Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 266
UART ............................................................................................................................................. 268
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 276
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 278
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 280
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 282
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 283
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 284
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 285
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 287
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 289
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 290
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 292
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 293
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 294
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 296
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 297
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 298
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 299
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 300
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 301
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 302
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 303
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 304
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 305
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 306
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 307
SSI ................................................................................................................................................. 308
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 320
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 322
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 323
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 324
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 325
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 326
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 327
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 328
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 329
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 330
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 331
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 332
Preliminary
15June 26, 2007
Table of Contents
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 333
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 334
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 335
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 336
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 337
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 338
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 339
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 340
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 341
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 342
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 356
Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 357
Register 3: I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 361
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 362
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 363
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 364
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 365
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 366
Register 9: I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 367
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 369
Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 370
Register 12: I2C Slave Data (I2CSDR), offset 0x008 ........................................................................... 372
Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 373
Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 374
Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 375
Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 376
CAN ............................................................................................................................................... 377
Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................. 391
Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................... 393
Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................... 396
Register 4: CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 397
Register 5: CAN Interrupt (CANINT), offset 0x010 ............................................................................. 399
Register 6: CAN Test (CANTST), offset 0x014 .................................................................................. 400
Register 7: CAN Baud Rate Prescalar Extension (CANBRPE), offset 0x018 ....................................... 402
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 403
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 403
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 404
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 404
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 407
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 407
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 408
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 408
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 409
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 409
Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 410
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 410
Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 411
Preliminary
June 26, 200716
LM3S2412 Microcontroller
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 411
Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ................................................................. 413
Register 23: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ................................................................. 413
Register 24: CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................. 414
Register 25: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ................................................................. 414
Register 26: CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................. 415
Register 27: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ................................................................. 415
Register 28: CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................. 416
Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ................................................................. 416
Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100 ................................................ 417
Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104 ................................................ 417
Register 32: CAN New Data 1 (CANNWDA1), offset 0x120 ................................................................. 418
Register 33: CAN New Data 2 (CANNWDA2), offset 0x124 ................................................................. 418
Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ..................................... 419
Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ..................................... 419
Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ....................................................... 420
Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ....................................................... 420
Analog Comparators ................................................................................................................... 421
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 426
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 427
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 428
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 429
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 430
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40 ....................................................... 430
Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 431
Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x44 ....................................................... 431
PWM .............................................................................................................................................. 433
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 440
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 441
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 442
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 443
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 444
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 445
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 446
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 447
Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 448
Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 449
Register 11: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 .................................... 451
Register 12: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 453
Register 13: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 454
Register 14: PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 455
Register 15: PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 456
Register 16: PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 457
Register 17: PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 458
Register 18: PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 459
Register 19: PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 461
Register 20: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 463
Register 21: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 464
Preliminary
17June 26, 2007
Table of Contents
Register 22: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 465
Preliminary
June 26, 200718
About This Document
This data sheet provides reference information for the LM3S2412 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following documents are referenced by the data sheet, and available on the documentation CD
or from the Luminary Micro web site at www.luminarymicro.com:
■
ARM® Cortex™-M3 Technical Reference Manual
LM3S2412 Microcontroller
■
ARM® CoreSight Technical Reference Manual
■
ARM® v7-M Architecture Application Level Reference Manual
The following related documents are also referenced:
■
IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the Luminary Micro web
site for additional documentation, including application notes and white papers.
Documentation Conventions
This document uses the conventions shown in Table 1 on page 19.
Table 1. Documentation Conventions
MeaningNotation
General Register Notation
REGISTER
offset 0xnnn
Register N
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
A single bit in a register.bit
Two or more consecutive and related bits.bit field
A hexadecimal increment to a register's address, relative to that module's base address as specified
in “Memory Map” on page 40.
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
Preliminary
19June 26, 2007
About This Document
reserved
yy:xx
Register Bit/Field
Types
R/W1C
W1C
Reset Value
Pin/Signal Notation
assert a signal
SIGNAL
SIGNAL
Numbers
X
0x
MeaningNotation
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31
in that register.
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.RC
Software can read this field. Always write the chip reset value.RO
Software can read or write this field.R/W
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain
unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
Only a write by software is valid; a read of the register returns no meaningful data.WO
This value in the register bit diagram shows the bit/field value after any reset, unless noted.Register Bit/Field
Bit cleared to 0 on chip reset.0
Bit set to 1 on chip reset.1
Nondeterministic.-
Pin alternate function; a pin defaults to the signal without the brackets.[ ]
Refers to the physical connection on the package.pin
Refers to the electrical signal encoding of a pin.signal
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and
SIGNAL below).
Change the value of the signal from the logically True state to the logically False state.deassert a signal
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates
that it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1,
and so on.
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
Binary numbers are indicated with a b suffix, for example, 1011b. Decimal numbers are written
without a prefix or suffix.
Preliminary
June 26, 200720
1 Architectural Overview
The Luminary Micro Stellaris®family of microcontrollers—the first ARM® Cortex™-M3 based
controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller
applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to
legacy 8- and 16-bit devices, all in a package with a small footprint.
The Stellaris®family offers efficient performance and extensive integration, favorably positioning
the device into cost-conscious applications requiring significant control-processing and connectivity
capabilities. The Stellaris®LM3S2000 series, designed for Controller Area Network (CAN)
applications, extends the Stellaris family with Bosch CAN networking technology, the golden standard
in short-haul industrial networks. The Stellaris®LM3S2000 series also marks the first integration of
CAN capabilities with the revolutionary Cortex-M3 core. The Stellaris®LM3S6000 series combines
both a 10/100 Ethernet Media Access Control (MAC) and Physical (PHY) layer, marking the first
time that integrated connectivity is available with an ARM Cortex-M3 MCU and the only integrated
10/100 Ethernet MAC and PHY available in an ARM architecture MCU.
The LM3S2412 microcontroller is targeted for industrial applications, including remote monitoring,
electronic point-of-sale machines, test and measurement equipment, network appliances and
switches, factory automation, HVAC and building control, gaming equipment, motion control, medical
instrumentation, and fire and security.
LM3S2412 Microcontroller
In addition, the LM3S2412 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S2412 microcontroller is code-compatible
to all members of the extensive Stellaris®family; providing flexibility to fit our customers' precise
needs.
Luminary Micro offers a complete solution to get to market quickly, with evaluation and development
boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong
support, sales, and distributor network.
1.1 Product Features
The LM3S2412 microcontroller includes the following product features:
■ 32-Bit RISC Performance
– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
– Thumb®-compatible Thumb-2-only instruction set processor core for high code density
– 25-MHz operation
– Hardware-division and single-cycle-multiplication
– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
– 30 interrupts with eight priority levels
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Architectural Overview
– Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
– Unaligned data access, enabling data to be efficiently packed into memory
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
■ Internal Memory
– 96 KB single-cycle flash
• User-managed flash block protection on a 2-KB block basis
• User-managed flash data programming
• User-defined and managed flash-protection block
– 32 KB single-cycle SRAM
■ General-Purpose Timers
– Three General-Purpose Timer Modules (GPTM), each of which provides two 16-bit
timer/counters. Each GPTM can be configured to operate independently as timers or event
counters (eight total): as a single 32-bit timer (four total), as one 32-bit Real-Time Clock (RTC)
to event capture, for Pulse Width Modulation (PWM), or to trigger analog-to-digital conversions
– 32-bit Timer modes
• Programmable one-shot timer
• Programmable periodic timer
• Real-Time Clock when using an external 32.768-KHz clock as the input
• User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU
Halt flag during debug
• ADC event trigger
– 16-bit Timer modes
• General-purpose timer function with an 8-bit prescaler
• Programmable one-shot timer
• Programmable periodic timer
• User-enabled stalling when the controller asserts CPU Halt flag during debug
• ADC event trigger
– 16-bit Input Capture modes
• Input edge count capture
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June 26, 200722
LM3S2412 Microcontroller
• Input edge time capture
– 16-bit PWM mode
• Simple PWM mode with software-programmable output inversion of the PWM signal
■ ARM FiRM-compliant Watchdog Timer
– 32-bit down counter with a programmable load register
– Separate watchdog clock with an enable
– Programmable interrupt generation logic with interrupt masking
– Lock register protection from runaway software
– Reset generation logic with an enable/disable
– User-enabled stalling when the controller asserts the CPU Halt flag during debug
■ Controller Area Network (CAN)
– Supports CAN protocol version 2.0 part A/B
– Bit rates up to 1Mb/s
– 32 message objects, each with its own identifier mask
– Maskable interrupt
– Disable automatic retransmission mode for TTCAN
– Programmable loop-back mode for self-test operation
■ Synchronous Serial Interface (SSI)
– Master or slave operation
– Programmable clock bit rate and prescale
– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
– Programmable data frame size from 4 to 16 bits
– Internal loopback test mode for diagnostic/debug testing
■ UART
– Two fully programmable 16C550-type UARTs with IrDA support
– Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service
loading
– Programmable baud-rate generator with fractional divider
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23June 26, 2007
Architectural Overview
– Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
– FIFO trigger levels of 1/8, ¼, ½, ¾, and 7/8
– Standard asynchronous communication bits for start, stop, and parity
– False-start-bit detection
– Line-break generation and detection
■ ADC
– Single- and differential-input configurations
– Three 10-bit channels (inputs) when used as single-ended inputs
– Sample rate of 250 thousand samples/second
– Flexible, configurable analog-to-digital conversion
– Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
– Each sequence triggered by software or internal event (timers, analog comparators, PWM
or GPIO)
– On-chip temperature sensor
■ Analog Comparators
– Two independent integrated analog comparators
– Configurable for output to: drive an output pin, generate an interrupt, or initiate an ADC sample
sequence
– Compare external pin input to external pin input or to internal programmable voltage reference
■ I2C
– Master and slave receive and transmit operation with transmission speed up to 100 Kbps in
Standard mode and 400 Kbps in Fast mode
– Interrupt generation
– Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
■ PWM
– One PWM generator blocks, each with one 16-bit counter, two comparators, a PWM generator,
and a dead-band generator
– One 16-bit counter
• Runs in Down or Up/Down mode
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Preliminary
LM3S2412 Microcontroller
• Output frequency controlled by a 16-bit load value
• Load value updates can be synchronized
• Produces output signals at zero and load value
– Two PWM comparators
• Comparator value updates can be synchronized
• Produces output signals on match
– PWM generator
• Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals
• Produces two independent PWM signals
– Dead-band generator
• Produces two PWM signals with programmable dead-band delays suitable for driving a
half-H bridge
• Can be bypassed, leaving input PWM signals unmodified
– Flexible output control block with PWM output enable of each PWM signal
• PWM output enable of each PWM signal
• Optional output inversion of each PWM signal (polarity control)
• Optional fault handling for each PWM signal
• Synchronization of timers in the PWM generator blocks
• Synchronization of timer/comparator updates across the PWM generator blocks
• Interrupt status summary of the PWM generator blocks
– Can initiate an ADC sample sequence
■ GPIOs
– 19-49 GPIOs, depending on configuration
– 5-V-tolerant input/outputs
– Programmable interrupt generation as either edge-triggered or level-sensitive
– Bit masking in both read and write operations through address lines
– Can initiate an ADC sample sequence
– Programmable control for GPIO pad configuration:
• Weak pull-up or pull-down resistors
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Architectural Overview
• 2-mA, 4-mA, and 8-mA pad drive
• Slew rate control for the 8-mA drive
• Open drain enables
• Digital input enables
■ Power
– On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
– Low-power options on controller: Sleep and Deep-sleep modes
– Low-power options for peripherals: software controls shutdown of individual peripherals
– User-enabled LDO unregulated voltage detection and automatic reset
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Flexible Reset Sources
– Power-on reset (POR)
– Reset pin assertion
– Brown-out (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
– Internal low drop-out (LDO) regulator output goes unregulated
■ Additional Features
– Six reset sources
– Programmable clock source control
– Clock gating to individual peripherals for power savings
– IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
– Debug access via JTAG and Serial Wire interfaces
– Full JTAG boundary scan
■ Industrial-range 100-pin RoHS-compliant LQFP package
1.2 Target Applications
■ Remote monitoring
■ Electronic point-of-sale (POS) machines
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Preliminary
■ Test and measurement equipment
■ Network appliances and switches
■ Factory automation
■ HVAC and building control
■ Gaming equipment
■ Motion control
■ Medical instrumentation
■ Fire and security
■ Power and energy
■ Transportation
1.3 High-Level Block Diagram
LM3S2412 Microcontroller
Figure 1-1 on page 28 shows the features on the Stellaris® Fury-class family of devices.
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27June 26, 2007
LDO Voltage
Regulator
3 Analog
Comparators
ANALOG
10-bit ADC
8 channel
1 Msps
Temp Sensor
Clocks, Reset
System Control
4 Timer/PWM/CCP
Each 32-bit or 2x16-bit
Watchdog Timer
GPIOs
SYSTEM
Battery-Backed
Hibernate
R
T
C
Systick Timer
64 KB SRAM
256 KB Flash
2 Quadrature
Encoder Inputs
6 PWM Outputs
MOTION CONTROL
Dead-Band
Generator
Comparators
PWM
Generator
PWM
Interrupt
Timer
3 UARTs
2 SSI/SPI
10/100 Ethernet
MAC + PHY
2 CAN
2 I2C
SERIAL INTERFACES
ARM
®
Cortex™-M3
50 MHz
JTAG
NVIC
SWD
32
32
Architectural Overview
Figure 1-1. Stellaris® Fury-class High-Level Block Diagram
1.4 Functional Overview
The following sections provide an overview of the features of the LM3S2412 microcontroller. The
page number in parenthesis indicates where that feature is discussed in detail. Ordering and support
information can be found in Appendix B, Ordering and Contact Information on page 498.
Preliminary
June 26, 200728
1.4.1 ARM Cortex™-M3
1.4.1.1 Processor Core (see page 34)
All members of the Stellaris®product family, including the LM3S2412 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
“ARM Cortex-M3 Processor Core” on page 34 provides an overview of the ARM core; the core is
detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.1.2 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
LM3S2412 Microcontroller
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
1.4.1.3 Nested Vectored Interrupt Controller (NVIC)
The LM3S2412 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the
ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions
are handled in Handler Mode. The processor state is automatically stored to the stack on an
exception, and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed without
the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions
(system handlers) and 30 interrupts.
“Interrupts” on page 42 provides an overview of the NVIC controller and the interrupt map. Exceptions
and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.2 Motor Control Peripherals
To enhance motor control, the LM3S2412 controller features Pulse Width Modulation (PWM) outputs.
1.4.2.1 PWM (see page 181)
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
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Preliminary
Architectural Overview
On the LM3S2412, PWM motion control functionality can be achieved through dedicated, flexible
motion control hardware (the PWM pins) or through the motion control features of the general-purpose
timers (using the CCP pins).
PWM Pins (see page 433)
The LM3S2412 PWM module consists of one PWM generator blocks and a control block. Each
PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a
PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector. The control
block determines the polarity of the PWM signals, and which signals are passed through to the pins.
Each PWM generator block produces two PWM signals that can either be independent signals or
a single pair of complementary signals with dead-band delays inserted. The output of the PWM
generation blocks are managed by the output control block before being passed to the device pins.
CCP Pins (see page 181)
The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable
to support a simple PWM mode with a software-programmable output inversion of the PWM signal.
1.4.3 Serial Communications Peripherals
The LM3S2412 controller supports both asynchronous and synchronous serial communications
with:
■ Two fully programmable 16C550-type UARTs
■ One SSI module
■ One I2C module
■ One CAN unit
1.4.3.1 UART (see page 268)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S2412 controller includes two fully programmable 16C550-type UARTs that support data
transfer speeds up to 460.8 Kbps. In addition, each UART is capable of supporting IrDA. (Although
similar in functionality to a 16C550 UART, it is not register-compatible.)
Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading.
The UART can generate individually masked interrupts from the RX, TX, modem status, and error
conditions. The module provides a single combined interrupt when any of the interrupts are asserted
and are unmasked.
1.4.3.2 SSI (see page 308)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface.
The LM3S2412 controller includes one SSI module that provides the functionality for synchronous
serial communications with peripheral devices, and can be configured to use the Freescale SPI,
MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also
configurable, and can be set between 4 and 16 bits, inclusive.
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