TEXAS INSTRUMENTS LM3S102 Technical data

PRELIMINARY

LM3S102 Microcontroller

DATA SHEET
Copyright © 2007 Luminary Micro, Inc.DS-LM3S102-1972
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LM3S102 Microcontroller

Table of Contents

About This Document .................................................................................................................... 14
Audience .............................................................................................................................................. 14
About This Manual ................................................................................................................................ 14
Related Documents ............................................................................................................................... 14
Documentation Conventions .................................................................................................................. 14
1 Architectural Overview ...................................................................................................... 16
1.1 Product Features ...................................................................................................................... 16
1.2 Target Applications .................................................................................................................... 20
1.3 High-Level Block Diagram ......................................................................................................... 20
1.4 Functional Overview .................................................................................................................. 21
1.4.1 ARM Cortex™-M3 ..................................................................................................................... 21
1.4.2 Motor Control Peripherals .......................................................................................................... 22
1.4.3 Analog Peripherals .................................................................................................................... 22
1.4.4 Serial Communications Peripherals ............................................................................................ 23
1.4.5 System Peripherals ................................................................................................................... 24
1.4.6 Memory Peripherals .................................................................................................................. 25
1.4.7 Additional Features ................................................................................................................... 25
1.4.8 Hardware Details ...................................................................................................................... 26
1.4.9 System Block Diagram .............................................................................................................. 27
2 ARM Cortex-M3 Processor Core ...................................................................................... 28
2.1 Block Diagram .......................................................................................................................... 29
2.2 Functional Description ............................................................................................................... 29
2.2.1 Serial Wire and JTAG Debug ..................................................................................................... 29
2.2.2 Embedded Trace Macrocell (ETM) ............................................................................................. 29
2.2.3 Trace Port Interface Unit (TPIU) ................................................................................................. 30
2.2.4 ROM Table ............................................................................................................................... 30
2.2.5 Memory Protection Unit (MPU) ................................................................................................... 30
2.2.6 Nested Vectored Interrupt Controller (NVIC) ................................................................................ 30
3 Memory Map ....................................................................................................................... 34
4 Interrupts ............................................................................................................................ 36
5 JTAG Interface .................................................................................................................... 38
5.1 Block Diagram .......................................................................................................................... 39
5.2 Functional Description ............................................................................................................... 39
5.2.1 JTAG Interface Pins .................................................................................................................. 40
5.2.2 JTAG TAP Controller ................................................................................................................. 41
5.2.3 Shift Registers .......................................................................................................................... 42
5.2.4 Operational Considerations ........................................................................................................ 42
5.3 Initialization and Configuration ................................................................................................... 43
5.4 Register Descriptions ................................................................................................................ 44
5.4.1 Instruction Register (IR) ............................................................................................................. 44
5.4.2 Data Registers .......................................................................................................................... 46
6 System Control ................................................................................................................... 48
6.1 Functional Description ............................................................................................................... 48
6.1.1 Device Identification .................................................................................................................. 48
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6.1.2 Reset Control ............................................................................................................................ 48
6.1.3 Power Control ........................................................................................................................... 51
6.1.4 Clock Control ............................................................................................................................ 51
6.1.5 System Control ......................................................................................................................... 54
6.2 Initialization and Configuration ................................................................................................... 54
6.3 Register Map ............................................................................................................................ 55
6.4 Register Descriptions ................................................................................................................ 56
7 Internal Memory ................................................................................................................. 98
7.1 Block Diagram .......................................................................................................................... 98
7.2 Functional Description ............................................................................................................... 98
7.2.1 SRAM Memory ......................................................................................................................... 98
7.2.2 Flash Memory ........................................................................................................................... 99
7.3 Flash Memory Initialization and Configuration ........................................................................... 101
7.3.1 Changing Flash Protection Bits ................................................................................................ 101
7.3.2 Flash Programming ................................................................................................................. 102
7.4 Register Map .......................................................................................................................... 102
7.5 Flash Register Descriptions (Flash Control Offset) ..................................................................... 103
7.6 Flash Register Descriptions (System Control Offset) .................................................................. 110
8 General-Purpose Input/Outputs (GPIOs) ....................................................................... 114
8.1 Block Diagram ........................................................................................................................ 115
8.2 Functional Description ............................................................................................................. 115
8.2.1 Data Control ........................................................................................................................... 116
8.2.2 Interrupt Control ...................................................................................................................... 117
8.2.3 Mode Control .......................................................................................................................... 118
8.2.4 Pad Control ............................................................................................................................. 118
8.2.5 Identification ........................................................................................................................... 118
8.3 Initialization and Configuration ................................................................................................. 118
8.4 Register Map .......................................................................................................................... 119
8.5 Register Descriptions .............................................................................................................. 121
9 General-Purpose Timers ................................................................................................. 153
9.1 Block Diagram ........................................................................................................................ 153
9.2 Functional Description ............................................................................................................. 154
9.2.1 GPTM Reset Conditions .......................................................................................................... 154
9.2.2 32-Bit Timer Operating Modes .................................................................................................. 155
9.2.3 16-Bit Timer Operating Modes .................................................................................................. 156
9.3 Initialization and Configuration ................................................................................................. 160
9.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 160
9.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 161
9.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 161
9.3.4 16-Bit Input Edge Count Mode ................................................................................................. 162
9.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 162
9.3.6 16-Bit PWM Mode ................................................................................................................... 163
9.4 Register Map .......................................................................................................................... 163
9.5 Register Descriptions .............................................................................................................. 164
10 Watchdog Timer ............................................................................................................... 189
10.1 Block Diagram ........................................................................................................................ 189
10.2 Functional Description ............................................................................................................. 189
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10.3 Initialization and Configuration ................................................................................................. 190
10.4 Register Map .......................................................................................................................... 190
10.5 Register Descriptions .............................................................................................................. 191
11 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 212
11.1 Block Diagram ........................................................................................................................ 213
11.2 Functional Description ............................................................................................................. 213
11.2.1 Transmit/Receive Logic ........................................................................................................... 213
11.2.2 Baud-Rate Generation ............................................................................................................. 214
11.2.3 Data Transmission .................................................................................................................. 215
11.2.4 FIFO Operation ....................................................................................................................... 215
11.2.5 Interrupts ................................................................................................................................ 215
11.2.6 Loopback Operation ................................................................................................................ 216
11.3 Initialization and Configuration ................................................................................................. 216
11.4 Register Map .......................................................................................................................... 217
11.5 Register Descriptions .............................................................................................................. 218
12 Synchronous Serial Interface (SSI) ................................................................................ 250
12.1 Block Diagram ........................................................................................................................ 250
12.2 Functional Description ............................................................................................................. 250
12.2.1 Bit Rate Generation ................................................................................................................. 251
12.2.2 FIFO Operation ....................................................................................................................... 251
12.2.3 Interrupts ................................................................................................................................ 251
12.2.4 Frame Formats ....................................................................................................................... 252
12.3 Initialization and Configuration ................................................................................................. 259
12.4 Register Map .......................................................................................................................... 260
12.5 Register Descriptions .............................................................................................................. 261
13 Inter-Integrated Circuit (I2C) Interface ............................................................................ 287
13.1 Block Diagram ........................................................................................................................ 287
13.2 Functional Description ............................................................................................................. 287
13.2.1 I2C Bus Functional Overview .................................................................................................... 288
13.2.2 Available Speed Modes ........................................................................................................... 290
13.2.3 Interrupts ................................................................................................................................ 290
13.2.4 Loopback Operation ................................................................................................................ 291
13.2.5 Command Sequence Flow Charts ............................................................................................ 291
13.3 Initialization and Configuration ................................................................................................. 298
13.4 I2C Register Map ..................................................................................................................... 299
13.5 Register Descriptions (I2C Master) ........................................................................................... 300
13.6 Register Descriptions (I2C Slave) ............................................................................................. 313
14 Analog Comparator ......................................................................................................... 322
14.1 Block Diagram ........................................................................................................................ 322
14.2 Functional Description ............................................................................................................. 322
14.2.1 Internal Reference Programming .............................................................................................. 323
14.3 Initialization and Configuration ................................................................................................. 324
14.4 Register Map .......................................................................................................................... 325
14.5 Register Descriptions .............................................................................................................. 325
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15 Pin Diagram ...................................................................................................................... 333
16 Signal Tables .................................................................................................................... 334
17 Operating Characteristics ............................................................................................... 339
18 Electrical Characteristics ................................................................................................ 340
18.1 DC Characteristics .................................................................................................................. 340
18.1.1 Maximum Ratings ................................................................................................................... 340
18.1.2 Recommended DC Operating Conditions .................................................................................. 340
18.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 341
18.1.4 Power Specifications ............................................................................................................... 341
18.1.5 Flash Memory Characteristics .................................................................................................. 342
18.2 AC Characteristics ................................................................................................................... 342
18.2.1 Load Conditions ...................................................................................................................... 342
18.2.2 Clocks .................................................................................................................................... 342
18.2.3 Analog Comparator ................................................................................................................. 343
18.2.4 I2C ......................................................................................................................................... 343
18.2.5 Synchronous Serial Interface (SSI) ........................................................................................... 344
18.2.6 JTAG and Boundary Scan ........................................................................................................ 345
18.2.7 General-Purpose I/O ............................................................................................................... 347
18.2.8 Reset ..................................................................................................................................... 347
19 Package Information ........................................................................................................ 350
A Serial Flash Loader .......................................................................................................... 352
A.1 Serial Flash Loader ................................................................................................................. 352
A.2 Interfaces ............................................................................................................................... 352
A.2.1 UART ..................................................................................................................................... 352
A.2.2 SSI ......................................................................................................................................... 352
A.3 Packet Handling ...................................................................................................................... 353
A.3.1 Packet Format ........................................................................................................................ 353
A.3.2 Sending Packets ..................................................................................................................... 353
A.3.3 Receiving Packets ................................................................................................................... 353
A.4 Commands ............................................................................................................................. 354
A.4.1 COMMAND_PING (0X20) ........................................................................................................ 354
A.4.2 COMMAND_GET_STATUS (0x23) ........................................................................................... 354
A.4.3 COMMAND_DOWNLOAD (0x21) ............................................................................................. 354
A.4.4 COMMAND_SEND_DATA (0x24) ............................................................................................. 355
A.4.5 COMMAND_RUN (0x22) ......................................................................................................... 355
A.4.6 COMMAND_RESET (0x25) ..................................................................................................... 355
B Register Quick Reference ............................................................................................... 357
C Ordering and Contact Information ................................................................................. 368
C.1 Ordering Information ................................................................................................................ 368
C.2 Kits ......................................................................................................................................... 368
C.3 Company Information .............................................................................................................. 368
C.4 Support Information ................................................................................................................. 369
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LM3S102 Microcontroller

List of Figures

Figure 1-1. Stellaris®100 Series High-Level Block Diagram ................................................................ 21
Figure 1-2. LM3S102 Controller System-Level Block Diagram ............................................................. 27
Figure 2-1. CPU Block Diagram ......................................................................................................... 29
Figure 2-2. TPIU Block Diagram ........................................................................................................ 30
Figure 5-1. JTAG Module Block Diagram ............................................................................................ 39
Figure 5-2. Test Access Port State Machine ....................................................................................... 42
Figure 5-3. IDCODE Register Format ................................................................................................. 46
Figure 5-4. BYPASS Register Format ................................................................................................ 46
Figure 5-5. Boundary Scan Register Format ....................................................................................... 47
Figure 6-1. External Circuitry to Extend Reset .................................................................................... 49
Figure 6-2. Main Clock Tree .............................................................................................................. 52
Figure 7-1. Flash Block Diagram ........................................................................................................ 98
Figure 8-1. GPIO Module Block Diagram .......................................................................................... 115
Figure 8-2. GPIO Port Block Diagram ............................................................................................... 116
Figure 8-3. GPIODATA Write Example ............................................................................................. 117
Figure 8-4. GPIODATA Read Example ............................................................................................. 117
Figure 9-1. GPTM Module Block Diagram ........................................................................................ 154
Figure 9-2. 16-Bit Input Edge Count Mode Example .......................................................................... 158
Figure 9-3. 16-Bit Input Edge Time Mode Example ........................................................................... 159
Figure 9-4. 16-Bit PWM Mode Example ............................................................................................ 160
Figure 10-1. WDT Module Block Diagram .......................................................................................... 189
Figure 11-1. UART Module Block Diagram ......................................................................................... 213
Figure 11-2. UART Character Frame ................................................................................................. 214
Figure 12-1. SSI Module Block Diagram ............................................................................................. 250
Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 252
Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 253
Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 254
Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 254
Figure 12-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 255
Figure 12-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 256
Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 256
Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 257
Figure 12-10. MICROWIRE Frame Format (Single Frame) .................................................................... 258
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 259
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 259
Figure 13-1. I2C Block Diagram ......................................................................................................... 287
Figure 13-2. I2C Bus Configuration .................................................................................................... 288
Figure 13-3. START and STOP Conditions ......................................................................................... 288
Figure 13-4. Complete Data Transfer with a 7-Bit Address ................................................................... 289
Figure 13-5. R/S Bit in First Byte ........................................................................................................ 289
Figure 13-6. Data Validity During Bit Transfer on the I2C Bus ............................................................... 289
Figure 13-7. Master Single SEND ...................................................................................................... 292
Figure 13-8. Master Single RECEIVE ................................................................................................. 293
Figure 13-9. Master Burst SEND ....................................................................................................... 294
Figure 13-10. Master Burst RECEIVE .................................................................................................. 295
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Figure 13-11. Master Burst RECEIVE after Burst SEND ........................................................................ 296
Figure 13-12. Master Burst SEND after Burst RECEIVE ........................................................................ 297
Figure 13-13. Slave Command Sequence ............................................................................................ 298
Figure 14-1. Analog Comparator Module Block Diagram ..................................................................... 322
Figure 14-2. Structure of Comparator Unit .......................................................................................... 323
Figure 14-3. Comparator Internal Reference Structure ........................................................................ 324
Figure 15-1. Pin Connection Diagram ................................................................................................ 333
Figure 18-1. Load Conditions ............................................................................................................ 342
Figure 18-2. I2C Timing ..................................................................................................................... 344
Figure 18-3. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 344
Figure 18-4. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 345
Figure 18-5. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 345
Figure 18-6. JTAG Test Clock Input Timing ......................................................................................... 346
Figure 18-7. JTAG Test Access Port (TAP) Timing .............................................................................. 347
Figure 18-8. JTAG TRST Timing ........................................................................................................ 347
Figure 18-9. External Reset Timing (RST) .......................................................................................... 348
Figure 18-10. Power-On Reset Timing ................................................................................................. 348
Figure 18-11. Brown-Out Reset Timing ................................................................................................ 349
Figure 18-12. Software Reset Timing ................................................................................................... 349
Figure 18-13. Watchdog Reset Timing ................................................................................................. 349
Figure 18-14. LDO Reset Timing ......................................................................................................... 349
Figure 19-1. 28-Pin SOIC Package .................................................................................................... 350
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List of Tables

Table 1. Documentation Conventions ............................................................................................ 14
Table 3-1. Memory Map ................................................................................................................... 34
Table 4-1. Exception Types .............................................................................................................. 36
Table 4-2. Interrupts ........................................................................................................................ 37
Table 5-1. JTAG Port Pins Reset State ............................................................................................. 40
Table 5-2. JTAG Instruction Register Commands ............................................................................... 44
Table 6-1. System Control Register Map ........................................................................................... 55
Table 6-2. PLL Mode Control ........................................................................................................... 69
Table 7-1. Flash Protection Policy Combinations ............................................................................. 100
Table 7-2. Flash Register Map ........................................................................................................ 103
Table 8-1. GPIO Pad Configuration Examples ................................................................................. 118
Table 8-2. GPIO Interrupt Configuration Example ............................................................................ 119
Table 8-3. GPIO Register Map ....................................................................................................... 120
Table 9-1. Available CCP Pins ........................................................................................................ 154
Table 9-2. 16-Bit Timer With Prescaler Configurations ..................................................................... 157
Table 9-3. Timers Register Map ...................................................................................................... 163
Table 10-1. Watchdog Timer Register Map ........................................................................................ 190
Table 11-1. UART Register Map ....................................................................................................... 217
Table 12-1. SSI Register Map .......................................................................................................... 260
Table 13-1. Examples of I2C Master Timer Period versus Speed Mode ............................................... 290
Table 13-2. Inter-Integrated Circuit (I2C) Interface Register Map ......................................................... 299
Table 13-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 304
Table 14-1. Comparator 0 Operating Modes ..................................................................................... 323
Table 14-2. Internal Reference Voltage and ACREFCTL Field Values ................................................. 324
Table 14-3. Analog Comparators Register Map ................................................................................. 325
Table 16-1. Signals by Pin Number ................................................................................................... 334
Table 16-2. Signals by Signal Name ................................................................................................. 335
Table 16-3. Signals by Function, Except for GPIO ............................................................................. 336
Table 16-4. GPIO Pins and Alternate Functions ................................................................................. 337
Table 17-1. Temperature Characteristics ........................................................................................... 339
Table 17-2. Thermal Characteristics ................................................................................................. 339
Table 18-1. Maximum Ratings .......................................................................................................... 340
Table 18-2. Recommended DC Operating Conditions ........................................................................ 340
Table 18-3. LDO Regulator Characteristics ....................................................................................... 341
Table 18-4. Detailed Power Specifications ........................................................................................ 341
Table 18-5. Flash Memory Characteristics ........................................................................................ 342
Table 18-6. Phase Locked Loop (PLL) Characteristics ....................................................................... 342
Table 18-7. Clock Characteristics ..................................................................................................... 342
Table 18-8. Analog Comparator Characteristics ................................................................................. 343
Table 18-9. Analog Comparator Voltage Reference Characteristics .................................................... 343
Table 18-10. I2C Characteristics ......................................................................................................... 343
Table 18-11. SSI Characteristics ........................................................................................................ 344
Table 18-12. JTAG Characteristics ..................................................................................................... 345
Table 18-13. GPIO Characteristics ..................................................................................................... 347
Table 18-14. Reset Characteristics ..................................................................................................... 347
Table C-1. Part Ordering Information ............................................................................................... 368
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List of Registers

System Control .............................................................................................................................. 48
Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 57
Register 2: Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030 .................................... 59
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 60
Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 61
Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 62
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 64
Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 65
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 66
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 70
Register 10: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 71
Register 11: Clock Verification Clear (CLKVCLR), offset 0x150 ............................................................. 72
Register 12: Allow Unregulated LDO to Reset the Part (LDOARST), offset 0x160 ................................... 73
Register 13: Device Identification 1 (DID1), offset 0x004 ....................................................................... 74
Register 14: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 76
Register 15: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 77
Register 16: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 79
Register 17: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 81
Register 18: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 82
Register 19: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 83
Register 20: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 84
Register 21: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 85
Register 22: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 .................................... 86
Register 23: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 .................................. 88
Register 24: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ......................... 90
Register 25: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 .................................... 92
Register 26: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 .................................. 93
Register 27: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ......................... 94
Register 28: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................... 95
Register 29: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................... 96
Register 30: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................... 97
Internal Memory ............................................................................................................................. 98
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 104
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 105
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 106
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 108
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 109
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 110
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 111
Register 8: Flash Memory Protection Read Enable (FMPRE), offset 0x130 ......................................... 112
Register 9: Flash Memory Protection Program Enable (FMPPE), offset 0x134 .................................... 113
General-Purpose Input/Outputs (GPIOs) ................................................................................... 114
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 122
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 123
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 124
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LM3S102 Microcontroller
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 125
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 126
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 127
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 128
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 129
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 130
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 131
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 133
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 134
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 135
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 136
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 137
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 138
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 139
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 140
Register 19: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 141
Register 20: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 142
Register 21: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 143
Register 22: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 144
Register 23: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 145
Register 24: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 146
Register 25: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 147
Register 26: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 148
Register 27: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 149
Register 28: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 150
Register 29: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 151
Register 30: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 152
General-Purpose Timers ............................................................................................................. 153
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 165
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 166
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 168
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 170
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 173
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 175
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 176
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 177
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 179
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 180
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 181
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 182
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 183
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 184
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 185
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 186
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 187
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 188
Watchdog Timer ........................................................................................................................... 189
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 192
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11November 29, 2007
Table of Contents
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 193
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 194
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 195
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 196
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 197
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 198
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 199
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 200
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 201
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 202
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 203
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 204
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 205
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 206
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 207
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 208
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 209
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 210
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 211
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 212
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 219
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 221
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 223
Register 4: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 225
Register 5: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 226
Register 6: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 227
Register 7: UART Control (UARTCTL), offset 0x030 ......................................................................... 229
Register 8: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 230
Register 9: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 232
Register 10: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 234
Register 11: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 235
Register 12: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 236
Register 13: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 238
Register 14: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 239
Register 15: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 240
Register 16: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 241
Register 17: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 242
Register 18: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 243
Register 19: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 244
Register 20: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 245
Register 21: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 246
Register 22: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 247
Register 23: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 248
Register 24: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 249
Synchronous Serial Interface (SSI) ............................................................................................ 250
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 262
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 264
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 266
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November 29, 200712
LM3S102 Microcontroller
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 267
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 269
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 270
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 272
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 273
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 274
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 275
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 276
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 277
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 278
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 279
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 280
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 281
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 282
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 283
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 284
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 285
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 286
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 287
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 301
Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 302
Register 3: I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 306
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 307
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 308
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 309
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 310
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 311
Register 9: I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 312
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 314
Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 315
Register 12: I2C Slave Data (I2CSDR), offset 0x008 ........................................................................... 317
Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 318
Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 319
Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 320
Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 321
Analog Comparator ..................................................................................................................... 322
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 326
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 327
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 328
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 329
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 330
Register 6: Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 331
13November 29, 2007
Preliminary

About This Document

About This Document
This data sheet provides reference information for the LM3S102 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3 core.

Audience

This manual is intended for system software developers, hardware designers, and application developers.

About This Manual

This document is organized into sections that correspond to each major feature.

Related Documents

The following documents are referenced by the data sheet, and available on the documentation CD or from the Luminary Micro web site at www.luminarymicro.com:
ARM® Cortex™-M3 Technical Reference Manual
ARM® CoreSight Technical Reference Manual
ARM® v7-M Architecture Application Level Reference Manual
The following related documents are also referenced:
IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the Luminary Micro web site for additional documentation, including application notes and white papers.

Documentation Conventions

This document uses the conventions shown in Table 1 on page 14.
Table 1. Documentation Conventions
MeaningNotation
General Register Notation
REGISTER
offset 0xnnn
Register N
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more than one register. For example, SRCRn represents any (or all) of the three Software Reset Control registers: SRCR0, SRCR1 , and SRCR2.
A single bit in a register.bit
Two or more consecutive and related bits.bit field
A hexadecimal increment to a register's address, relative to that module's base address as specified in “Memory Map” on page 34.
Registers are numbered consecutively throughout the document to aid in referencing them. The register number has no meaning to software.
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November 29, 200714
reserved
yy:xx
Register Bit/Field Types
R/W1C
W1C
Reset Value
Pin/Signal Notation
assert a signal
SIGNAL
SIGNAL
Numbers
X
0x
LM3S102 Microcontroller
MeaningNotation
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to 0; however, user software should not rely on the value of a reserved bit. To provide software compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in that register.
This value in the register bit diagram indicates whether software running on the controller can change the value of the bit field.
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.RC
Software can read this field. Always write the chip reset value.RO
Software can read or write this field.R/W
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation provides the interrupt status and the write of the read value clears only the interrupts being reported at the time the register was read.
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
Only a write by software is valid; a read of the register returns no meaningful data.WO
This value in the register bit diagram shows the bit/field value after any reset, unless noted.Register Bit/Field
Bit cleared to 0 on chip reset.0
Bit set to 1 on chip reset.1
Nondeterministic.-
Pin alternate function; a pin defaults to the signal without the brackets.[ ]
Refers to the physical connection on the package.pin
Refers to the electrical signal encoding of a pin.signal
Change the value of the signal from the logically False state to the logically True state. For active High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL below).
Change the value of the signal from the logically True state to the logically False state.deassert a signal
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and so on.
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information, binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written without a prefix or suffix.
Preliminary
15November 29, 2007

Architectural Overview

1 Architectural Overview
The Luminary Micro Stellaris®family of microcontrollers—the first ARM® Cortex™-M3 based controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint.
The LM3S102 microcontroller is targeted for industrial applications, including test and measurement equipment, factory automation, HVAC and building control, motion control, medical instrumentation, fire and security, and power/energy.
In addition, the LM3S102 microcontroller offers the advantages of ARM's widely available development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community. Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost. Finally, the LM3S102 microcontroller is code-compatible to all members of the extensive Stellaris®family; providing flexibility to fit our customers' precise needs.
Luminary Micro offers a complete solution to get to market quickly, with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and distributor network.

1.1 Product Features

The LM3S102 microcontroller includes the following product features:
32-Bit RISC Performance
32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
Thumb®-compatible Thumb-2-only instruction set processor core for high code density
20-MHz operation
Hardware-division and single-cycle-multiplication
Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
14 interrupts with eight priority levels
Unaligned data access, enabling data to be efficiently packed into memory
Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
Internal Memory
8 KB single-cycle flash
User-managed flash block protection on a 2-KB block basis
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LM3S102 Microcontroller
User-managed flash data programming
User-defined and managed flash-protection block
2 KB single-cycle SRAM
General-Purpose Timers
Two General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers.
Each GPTM can be configured to operate independently:
As a single 32-bit timer
As one 32-bit Real-Time Clock (RTC) to event capture
For Pulse Width Modulation (PWM)
32-bit Timer modes
Programmable one-shot timer
Programmable periodic timer
Real-Time Clock when using an external 32.768-KHz clock as the input
User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU Halt flag during debug
16-bit Timer modes
General-purpose timer function with an 8-bit prescaler
Programmable one-shot timer
Programmable periodic timer
User-enabled stalling when the controller asserts CPU Halt flag during debug
16-bit Input Capture modes
Input edge count capture
Input edge time capture
16-bit PWM mode
Simple PWM mode with software-programmable output inversion of the PWM signal
ARM FiRM-compliant Watchdog Timer
32-bit down counter with a programmable load register
Separate watchdog clock with an enable
Programmable interrupt generation logic with interrupt masking
Lock register protection from runaway software
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Architectural Overview
Reset generation logic with an enable/disable
User-enabled stalling when the controller asserts the CPU Halt flag during debug
Synchronous Serial Interface (SSI)
Master or slave operation
Programmable clock bit rate and prescale
Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
Programmable data frame size from 4 to 16 bits
Internal loopback test mode for diagnostic/debug testing
UART
Fully programmable 16C550-type UART
Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service
loading
Programmable baud-rate generator with fractional divider
Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
Standard asynchronous communication bits for start, stop, and parity
False-start-bit detection
Line-break generation and detection
Analog Comparators
One integrated analog comparator
Configurable for output to: drive an output pin or generate an interrupt
Compare external pin input to external pin input or to internal programmable voltage reference
I2C
Master and slave receive and transmit operation with transmission speed up to 100 Kbps in
Standard mode and 400 Kbps in Fast mode
Interrupt generation
Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
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Preliminary
LM3S102 Microcontroller
GPIOs
0-18 GPIOs, depending on configuration
5-V-tolerant input/outputs
Programmable interrupt generation as either edge-triggered or level-sensitive
Bit masking in both read and write operations through address lines
Programmable control for GPIO pad configuration:
Weak pull-up or pull-down resistors
2-mA, 4-mA, and 8-mA pad drive
Slew rate control for the 8-mA drive
Open drain enables
Digital input enables
Power
On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
Low-power options on controller: Sleep and Deep-sleep modes
Low-power options for peripherals: software controls shutdown of individual peripherals
User-enabled LDO unregulated voltage detection and automatic reset
3.3-V supply brown-out detection and reporting via interrupt or reset
Flexible Reset Sources
Power-on reset (POR)
Reset pin assertion
Brown-out (BOR) detector alerts to system power drops
Software reset
Watchdog timer reset
Internal low drop-out (LDO) regulator output goes unregulated
Additional Features
Six reset sources
Programmable clock source control
Clock gating to individual peripherals for power savings
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19November 29, 2007
Architectural Overview
IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
Debug access via JTAG and Serial Wire interfaces
Full JTAG boundary scan
Industrial-range 28-pin RoHS-compliant SOIC package

1.2 Target Applications

Factory automation and control
Industrial control power devices
Building and home automation
Stepper motors
Brushless DC motors
AC induction motors

1.3 High-Level Block Diagram

Figure 1-1 on page 21 represents the full set of features in the Stellaris®100 series of devices; not all features may be available on the LM3S102 microcontroller.
Preliminary
November 29, 200720
Figure 1-1. Stellaris®100 Series High-Level Block Diagram
LM3S102 Microcontroller

1.4 Functional Overview

The following sections provide an overview of the features of the LM3S102 microcontroller. The page number in parenthesis indicates where that feature is discussed in detail. Ordering and support information can be found in “Ordering and Contact Information” on page 368.

1.4.1 ARM Cortex™-M3

1.4.1.1 Processor Core (see page 28)
All members of the Stellaris®product family, including the LM3S102 microcontroller, are designed around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low-power consumption, while delivering outstanding computational performance and exceptional system response to interrupts.
“ARM Cortex-M3 Processor Core” on page 28 provides an overview of the ARM core; the core is detailed in the ARM® Cortex™-M3 Technical Reference Manual.
21November 29, 2007
Preliminary
Architectural Overview
1.4.1.2 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example:
An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
A high-speed alarm timer using the system clock.
A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
A simple counter. Software can use this to measure time to completion and time used.
An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop.
1.4.1.3 Nested Vectored Interrupt Controller (NVIC)
The LM3S102 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions are handled in Handler Mode. The processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions (system handlers) and 14 interrupts.
“Interrupts” on page 36 provides an overview of the NVIC controller and the interrupt map. Exceptions and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual.

1.4.2 Motor Control Peripherals

To enhance motor control, the LM3S102 controller features Pulse Width Modulation (PWM) outputs.
1.4.2.1 PWM
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels. High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control.
On the LM3S102, PWM motion control functionality can be achieved through:
The motion control features of the general-purpose timers using the CCP pins
CCP Pins (see page 159)
The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable to support a simple PWM mode with a software-programmable output inversion of the PWM signal.

1.4.3 Analog Peripherals

For support of analog signals, the LM3S102 microcontroller offers one analog comparator.
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Preliminary
1.4.3.1 Analog Comparators (see page 322)
An analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result.
A comparator can compare a test voltage against any one of these voltages:
An individual external reference voltage
A shared single external reference voltage
A shared internal reference voltage
The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts to cause it to start capturing a sample sequence.

1.4.4 Serial Communications Peripherals

The LM3S102 controller supports both asynchronous and synchronous serial communications with:
One fully programmable 16C550-type UART
LM3S102 Microcontroller
One SSI module
One I2C module
1.4.4.1 UART (see page 212)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately.
The LM3S102 controller includes one fully programmable 16C550-type UARTthat supports data transfer speeds up to 460.8 Kbps. (Although similar in functionality to a 16C550 UART, it is not register-compatible.)
Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading. The UART can generate individually masked interrupts from the RX, TX, modem status, and error conditions. The module provides a single combined interrupt when any of the interrupts are asserted and are unmasked.
1.4.4.2 SSI (see page 250)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface.
The LM3S102 controller includes one SSI module that provides the functionality for synchronous serial communications with peripheral devices, and can be configured to use the Freescale SPI, MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also configurable, and can be set between 4 and 16 bits, inclusive.
The SSI module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently.
The SSI module can be configured as either a master or slave device. As a slave device, the SSI module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices.
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23November 29, 2007
Architectural Overview
The SSI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the SSI module's input clock. Bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral.
1.4.4.3 I2C (see page 287)
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL).
The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture.
The LM3S102 controller includes one I2C module that provides the ability to communicate to other IC devices over an I2C bus. The I2C bus supports devices that can both transmit and receive (write and read) data.
Devices on the I2C bus can be designated as either a master or a slave. The I2C module supports both sending and receiving data as either a master or a slave, and also supports the simultaneous operation as both a master and a slave. The four I2C modes are: Master Transmit, Master Receive, Slave Transmit, and Slave Receive.
A Stellaris®I2C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps).
Both the I2C master and slave can generate interrupts. The I2C master generates interrupts when a transmit or receive operation completes (or aborts due to an error). The I2C slave generates interrupts when data has been sent or requested by a master.

1.4.5 System Peripherals

1.4.5.1 Programmable GPIOs (see page 114)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections.
The Stellaris®GPIO module is composed of three physical GPIO blocks, each corresponding to an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time Microcontrollers specification) and supports 0-18 programmable input/output pins. The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page 334 for the signals available to each GPIO pin).
The GPIO module features programmable interrupt generation as either edge-triggered or level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in both read and write operations through address lines.
1.4.5.2 Two Programmable Timers (see page 153)
Programmable timers can be used to count or time external events that drive the Timer input pins.
The Stellaris®General-Purpose Timer Module (GPTM) contains two GPTM blocks. Each GPTM block provides two 16-bit timers/counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event capture or Pulse Width Modulation (PWM) generation.
November 29, 200724
Preliminary
1.4.5.3 Watchdog Timer (see page 189)
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way.
The Stellaris®Watchdog Timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, and a locking register.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered.

1.4.6 Memory Peripherals

The LM3S102 controller offers both single-cycle SRAM and single-cycle Flash memory.
1.4.6.1 SRAM (see page 98)
The LM3S102 static random access memory (SRAM) controller supports 2 KB SRAM. The internal SRAM of the Stellaris®devices is located at offset 0x0000.0000 of the device memory map. To reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation.
LM3S102 Microcontroller
1.4.6.2 Flash (see page 99)
The LM3S102 Flash controller supports 8 KB of flash memory. The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually protected. The blocks can be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger.

1.4.7 Additional Features

1.4.7.1 Memory Map (see page 34)
A memory map lists the location of instructions and data in memory. The memory map for the LM3S102 controller can be found in “Memory Map” on page 34. Register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map.
The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory map.
1.4.7.2 JTAG TAP Controller (see page 38)
The Joint Test Action Group (JTAG) port provides a standardized serial interface for controlling the Test Access Port (TAP) and associated test logic. The TAP, JTAG instruction register, and JTAG data registers can be used to test the interconnects of assembled printed circuit boards, obtain manufacturing information on the components, and observe and/or control the inputs and outputs of the controller during normal operation. The JTAG port provides a high degree of testability and chip-level access at a low cost.
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Architectural Overview
The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture.
The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions.
1.4.7.3 System Control and Clocks (see page 48)
System control determines the overall operation of the device. It provides information about the device, controls the clocking of the device and individual peripherals, and handles reset detection and reporting.

1.4.8 Hardware Details

Details on the pins and package can be found in the following sections:
“Pin Diagram” on page 333
“Signal Tables” on page 334
“Operating Characteristics” on page 339
“Electrical Characteristics” on page 340
“Package Information” on page 350
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1.4.9 System Block Diagram

Flash
SRAM
APB Bridge
ICode
DCode
GND
VDD_3.3V
LDO VDD_2.5V
LDO
System
Control
& Clocks
OSC0
OSC1
RST
PLL
Watchdog
Timer
POR
BOR
IOSC
Debug
ARM Cortex-M3
NVIC
CM3Core
Bus
Peripheral Bus
UART0
GPIO Port B
PA1/U0Tx PA0/U0Rx
GPIO Port A
SSI
PA3/SSIFss
PA2/SSIClk
PA5/SSITx PA4/SSIRx
GPIO Port C
JTAG
SWD/SWO
PC1/TMS/SWDIO
PC0/TCK/SWCLK
PC3/TDO/SWO
PC2/TDI
PB1/32KHz
PB0/CCP0
PB3/I2CSDA PB2/I2CSCL
PB5/C0o PB4/C0-
PB6/CCP1/C0+
GP Timer1
GP Timer0
PB7/TRST
Analog
Comparator
I2C
Master
Slave
(2 KB)
(8 KB)
(20 MHz)
LM3S102
Figure 1-2. LM3S102 Controller System-Level Block Diagram
LM3S102 Microcontroller
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ARM Cortex-M3 Processor Core

2 ARM Cortex-M3 Processor Core
The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Features include:
Compact core.
Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory
size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications.
Rapid application execution through Harvard architecture characterized by separate buses for
instruction and data.
Exceptional interrupt handling, by implementing the register manipulations required for handling
an interrupt in hardware.
Migration from the ARM7™ processor family for better performance and power efficiency.
Full-featured debug solution with a:
Serial Wire JTAG Debug Port (SWJ-DP)
Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
Instrumentation Trace Macrocell (ITM) for support of printf style debugging
Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
The Stellaris®family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motors.
For more information on the ARM Cortex-M3 processor core, see the ARM® Cortex™-M3 Technical
Reference Manual. For information on SWJ-DP, see the ARM® CoreSight Technical Reference Manual.
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2.1 Block Diagram

Private Peripheral
Bus
(internal)
Data
Watchpoint
and Trace
Interrupts
Debug
Sleep
Instrumentation
Trace Macrocell
Trace
Port
Interface
Unit
CM3 Core
Instructions Data
Flash
Patch and
Breakpoint
Adv. High-
Perf. Bus
Access Port
Nested
Vectored
Interrupt
Controller
Serial Wire JTAG
Debug Port
Bus
Matrix
Adv. Peripheral
Bus
I-code bus D-code bus System bus
ROM
Table
Private
Peripheral
Bus
(external)
Serial
Wire
Output
Trace
Port
(SWO)
ARM
Cortex-M3
Figure 2-1. CPU Block Diagram
LM3S102 Microcontroller

2.2 Functional Description

Important:
Luminary Micro has implemented the ARM Cortex-M3 core as shown in Figure 2-1 on page 29. As noted in the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3 components are flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the MPU, and the Nested Vectored Interrupt Controller (NVIC). Each of these is addressed in the sections that follow.

2.2.1 Serial Wire and JTAG Debug

Luminary Micro has replaced the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant Serial Wire JTAG Debug Port (SWJ-DP) interface. This means Chapter 12, “Debug Port,” of the ARM® Cortex™-M3 Technical Reference Manual does not apply to Stellaris®devices.
The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP.

2.2.2 Embedded Trace Macrocell (ETM)

ETM was not implemented in the Stellaris®devices. This means Chapters 15 and 16 of the ARM® Cortex™-M3 Technical Reference Manual can be ignored.
The ARM® Cortex™-M3 Technical Reference Manual describes all the features of an ARM Cortex-M3 in detail. However, these features differ based on the implementation. This section describes the Stellaris®implementation.
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ATB
Interface
Asynchronous FIFO
APB
Interface
Trace Out
(serializer)
Debug
ATB
Slave
Port
APB
Slave
Port
Serial Wire
Trace Port
(SWO)
ARM Cortex-M3 Processor Core

2.2.3 Trace Port Interface Unit (TPIU)

The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace Port Analyzer. The Stellaris®devices have implemented TPIU as shown in Figure 2-2 on page 30. This is similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference Manual, however, SWJ-DP only provides SWV output for the TPIU.
Figure 2-2. TPIU Block Diagram

2.2.4 ROM Table

The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical Reference Manual.

2.2.5 Memory Protection Unit (MPU)

The LM3S102 controller does not include the memory protection unit (MPU) of the ARM Cortex-M3.

2.2.6 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC):
Facilitates low-latency exception and interrupt handling
Controls power management
Implements system control registers
The NVIC supports up to 240 dynamically reprioritizable interrupts each with up to 256 levels of priority. The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of the stacked (nested) interrupts to enable tail-chaining of interrupts.
You can only fully access the NVIC from privileged mode, but you can pend interrupts in user-mode if you enable the Configuration Control Register (see the ARM® Cortex™-M3 Technical Reference Manual). Any other user-mode access causes a bus fault.
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