TEXAS INSTRUMENTS LM3S101 Technical data
PRELIMINARY
LM3S101 Microcontroller
DATA SHEET
Copyright © 2007 Luminary Micro, Inc.DS-LM3S101-1972
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Preliminary
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LM3S101 Microcontroller
Table of Contents
About This Document .................................................................................................................... 14
Audience .............................................................................................................................................. 14
About This Manual ................................................................................................................................ 14
Related Documents ............................................................................................................................... 14
Documentation Conventions .................................................................................................................. 14
1 Architectural Overview ...................................................................................................... 16
1.1 Product Features ...................................................................................................................... 16
1.2 Target Applications .................................................................................................................... 20
1.3 High-Level Block Diagram ......................................................................................................... 20
1.4 Functional Overview .................................................................................................................. 21
1.4.1 ARM Cortex™-M3 ..................................................................................................................... 21
1.4.2 Motor Control Peripherals .......................................................................................................... 21
1.4.3 Analog Peripherals .................................................................................................................... 22
1.4.4 Serial Communications Peripherals ............................................................................................ 22
1.4.5 System Peripherals ................................................................................................................... 23
1.4.6 Memory Peripherals .................................................................................................................. 24
1.4.7 Additional Features ................................................................................................................... 24
1.4.8 Hardware Details ...................................................................................................................... 25
1.4.9 System Block Diagram .............................................................................................................. 26
2 ARM Cortex-M3 Processor Core ...................................................................................... 27
2.1 Block Diagram .......................................................................................................................... 28
2.2 Functional Description ............................................................................................................... 28
2.2.1 Serial Wire and JTAG Debug ..................................................................................................... 28
2.2.2 Embedded Trace Macrocell (ETM) ............................................................................................. 28
2.2.3 Trace Port Interface Unit (TPIU) ................................................................................................. 29
2.2.4 ROM Table ............................................................................................................................... 29
2.2.5 Memory Protection Unit (MPU) ................................................................................................... 29
2.2.6 Nested Vectored Interrupt Controller (NVIC) ................................................................................ 29
3 Memory Map ....................................................................................................................... 33
4 Interrupts ............................................................................................................................ 35
5 JTAG Interface .................................................................................................................... 37
5.1 Block Diagram .......................................................................................................................... 38
5.2 Functional Description ............................................................................................................... 38
5.2.1 JTAG Interface Pins .................................................................................................................. 39
5.2.2 JTAG TAP Controller ................................................................................................................. 40
5.2.3 Shift Registers .......................................................................................................................... 41
5.2.4 Operational Considerations ........................................................................................................ 41
5.3 Initialization and Configuration ................................................................................................... 42
5.4 Register Descriptions ................................................................................................................ 43
5.4.1 Instruction Register (IR) ............................................................................................................. 43
5.4.2 Data Registers .......................................................................................................................... 45
6 System Control ................................................................................................................... 47
6.1 Functional Description ............................................................................................................... 47
6.1.1 Device Identification .................................................................................................................. 47
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6.1.2 Reset Control ............................................................................................................................ 47
6.1.3 Power Control ........................................................................................................................... 50
6.1.4 Clock Control ............................................................................................................................ 50
6.1.5 System Control ......................................................................................................................... 53
6.2 Initialization and Configuration ................................................................................................... 53
6.3 Register Map ............................................................................................................................ 54
6.4 Register Descriptions ................................................................................................................ 55
7 Internal Memory ................................................................................................................. 97
7.1 Block Diagram .......................................................................................................................... 97
7.2 Functional Description ............................................................................................................... 97
7.2.1 SRAM Memory ......................................................................................................................... 97
7.2.2 Flash Memory ........................................................................................................................... 98
7.3 Flash Memory Initialization and Configuration ........................................................................... 100
7.3.1 Changing Flash Protection Bits ................................................................................................ 100
7.3.2 Flash Programming ................................................................................................................. 101
7.4 Register Map .......................................................................................................................... 101
7.5 Flash Register Descriptions (Flash Control Offset) ..................................................................... 102
7.6 Flash Register Descriptions (System Control Offset) .................................................................. 109
8 General-Purpose Input/Outputs (GPIOs) ....................................................................... 113
8.1 Block Diagram ........................................................................................................................ 114
8.2 Functional Description ............................................................................................................. 114
8.2.1 Data Control ........................................................................................................................... 115
8.2.2 Interrupt Control ...................................................................................................................... 116
8.2.3 Mode Control .......................................................................................................................... 117
8.2.4 Pad Control ............................................................................................................................. 117
8.2.5 Identification ........................................................................................................................... 117
8.3 Initialization and Configuration ................................................................................................. 117
8.4 Register Map .......................................................................................................................... 118
8.5 Register Descriptions .............................................................................................................. 120
9 General-Purpose Timers ................................................................................................. 152
9.1 Block Diagram ........................................................................................................................ 152
9.2 Functional Description ............................................................................................................. 153
9.2.1 GPTM Reset Conditions .......................................................................................................... 153
9.2.2 32-Bit Timer Operating Modes .................................................................................................. 154
9.2.3 16-Bit Timer Operating Modes .................................................................................................. 155
9.3 Initialization and Configuration ................................................................................................. 159
9.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 159
9.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 160
9.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 160
9.3.4 16-Bit Input Edge Count Mode ................................................................................................. 161
9.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 161
9.3.6 16-Bit PWM Mode ................................................................................................................... 162
9.4 Register Map .......................................................................................................................... 162
9.5 Register Descriptions .............................................................................................................. 163
10 Watchdog Timer ............................................................................................................... 188
10.1 Block Diagram ........................................................................................................................ 188
10.2 Functional Description ............................................................................................................. 188
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10.3 Initialization and Configuration ................................................................................................. 189
10.4 Register Map .......................................................................................................................... 189
10.5 Register Descriptions .............................................................................................................. 190
11 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 211
11.1 Block Diagram ........................................................................................................................ 212
11.2 Functional Description ............................................................................................................. 212
11.2.1 Transmit/Receive Logic ........................................................................................................... 212
11.2.2 Baud-Rate Generation ............................................................................................................. 213
11.2.3 Data Transmission .................................................................................................................. 214
11.2.4 FIFO Operation ....................................................................................................................... 214
11.2.5 Interrupts ................................................................................................................................ 214
11.2.6 Loopback Operation ................................................................................................................ 215
11.3 Initialization and Configuration ................................................................................................. 215
11.4 Register Map .......................................................................................................................... 216
11.5 Register Descriptions .............................................................................................................. 217
12 Synchronous Serial Interface (SSI) ................................................................................ 249
12.1 Block Diagram ........................................................................................................................ 249
12.2 Functional Description ............................................................................................................. 249
12.2.1 Bit Rate Generation ................................................................................................................. 250
12.2.2 FIFO Operation ....................................................................................................................... 250
12.2.3 Interrupts ................................................................................................................................ 250
12.2.4 Frame Formats ....................................................................................................................... 251
12.3 Initialization and Configuration ................................................................................................. 258
12.4 Register Map .......................................................................................................................... 259
12.5 Register Descriptions .............................................................................................................. 260
13 Analog Comparators ....................................................................................................... 286
13.1 Block Diagram ........................................................................................................................ 286
13.2 Functional Description ............................................................................................................. 286
13.2.1 Internal Reference Programming .............................................................................................. 288
13.3 Initialization and Configuration ................................................................................................. 289
13.4 Register Map .......................................................................................................................... 289
13.5 Register Descriptions .............................................................................................................. 290
14 Pin Diagram ...................................................................................................................... 298
15 Signal Tables .................................................................................................................... 299
16 Operating Characteristics ............................................................................................... 304
17 Electrical Characteristics ................................................................................................ 305
17.1 DC Characteristics .................................................................................................................. 305
17.1.1 Maximum Ratings ................................................................................................................... 305
17.1.2 Recommended DC Operating Conditions .................................................................................. 305
17.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 306
17.1.4 Power Specifications ............................................................................................................... 306
17.1.5 Flash Memory Characteristics .................................................................................................. 307
17.2 AC Characteristics ................................................................................................................... 307
17.2.1 Load Conditions ...................................................................................................................... 307
17.2.2 Clocks .................................................................................................................................... 307
17.2.3 Analog Comparator ................................................................................................................. 308
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17.2.4 Synchronous Serial Interface (SSI) ........................................................................................... 308
17.2.5 JTAG and Boundary Scan ........................................................................................................ 310
17.2.6 General-Purpose I/O ............................................................................................................... 311
17.2.7 Reset ..................................................................................................................................... 312
18 Package Information ........................................................................................................ 315
A Serial Flash Loader .......................................................................................................... 317
A.1 Serial Flash Loader ................................................................................................................. 317
A.2 Interfaces ............................................................................................................................... 317
A.2.1 UART ..................................................................................................................................... 317
A.2.2 SSI ......................................................................................................................................... 317
A.3 Packet Handling ...................................................................................................................... 318
A.3.1 Packet Format ........................................................................................................................ 318
A.3.2 Sending Packets ..................................................................................................................... 318
A.3.3 Receiving Packets ................................................................................................................... 318
A.4 Commands ............................................................................................................................. 319
A.4.1 COMMAND_PING (0X20) ........................................................................................................ 319
A.4.2 COMMAND_GET_STATUS (0x23) ........................................................................................... 319
A.4.3 COMMAND_DOWNLOAD (0x21) ............................................................................................. 319
A.4.4 COMMAND_SEND_DATA (0x24) ............................................................................................. 320
A.4.5 COMMAND_RUN (0x22) ......................................................................................................... 320
A.4.6 COMMAND_RESET (0x25) ..................................................................................................... 320
B Register Quick Reference ............................................................................................... 322
C Ordering and Contact Information ................................................................................. 332
C.1 Ordering Information ................................................................................................................ 332
C.2 Kits ......................................................................................................................................... 332
C.3 Company Information .............................................................................................................. 332
C.4 Support Information ................................................................................................................. 333
Preliminary
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LM3S101 Microcontroller
List of Figures
Figure 1-1. Stellaris®100 Series High-Level Block Diagram ................................................................ 20
Figure 1-2. LM3S101 Controller System-Level Block Diagram ............................................................. 26
Figure 2-1. CPU Block Diagram ......................................................................................................... 28
Figure 2-2. TPIU Block Diagram ........................................................................................................ 29
Figure 5-1. JTAG Module Block Diagram ............................................................................................ 38
Figure 5-2. Test Access Port State Machine ....................................................................................... 41
Figure 5-3. IDCODE Register Format ................................................................................................. 45
Figure 5-4. BYPASS Register Format ................................................................................................ 45
Figure 5-5. Boundary Scan Register Format ....................................................................................... 46
Figure 6-1. External Circuitry to Extend Reset .................................................................................... 48
Figure 6-2. Main Clock Tree .............................................................................................................. 51
Figure 7-1. Flash Block Diagram ........................................................................................................ 97
Figure 8-1. GPIO Module Block Diagram .......................................................................................... 114
Figure 8-2. GPIO Port Block Diagram ............................................................................................... 115
Figure 8-3. GPIODATA Write Example ............................................................................................. 116
Figure 8-4. GPIODATA Read Example ............................................................................................. 116
Figure 9-1. GPTM Module Block Diagram ........................................................................................ 153
Figure 9-2. 16-Bit Input Edge Count Mode Example .......................................................................... 157
Figure 9-3. 16-Bit Input Edge Time Mode Example ........................................................................... 158
Figure 9-4. 16-Bit PWM Mode Example ............................................................................................ 159
Figure 10-1. WDT Module Block Diagram .......................................................................................... 188
Figure 11-1. UART Module Block Diagram ......................................................................................... 212
Figure 11-2. UART Character Frame ................................................................................................. 213
Figure 12-1. SSI Module Block Diagram ............................................................................................. 249
Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 251
Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 252
Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 253
Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 253
Figure 12-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 254
Figure 12-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 255
Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 255
Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 256
Figure 12-10. MICROWIRE Frame Format (Single Frame) .................................................................... 257
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 258
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 258
Figure 13-1. Analog Comparator Module Block Diagram ..................................................................... 286
Figure 13-2. Structure of Comparator Unit .......................................................................................... 287
Figure 13-3. Comparator Internal Reference Structure ........................................................................ 288
Figure 14-1. Pin Connection Diagram ................................................................................................ 298
Figure 17-1. Load Conditions ............................................................................................................ 307
Figure 17-2. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 309
Figure 17-3. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 309
Figure 17-4. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 310
Figure 17-5. JTAG Test Clock Input Timing ......................................................................................... 311
Figure 17-6. JTAG Test Access Port (TAP) Timing .............................................................................. 311
Figure 17-7. JTAG TRST Timing ........................................................................................................ 311
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Figure 17-8. External Reset Timing (RST) .......................................................................................... 312
Figure 17-9. Power-On Reset Timing ................................................................................................. 313
Figure 17-10. Brown-Out Reset Timing ................................................................................................ 313
Figure 17-11. Software Reset Timing ................................................................................................... 313
Figure 17-12. Watchdog Reset Timing ................................................................................................. 314
Figure 17-13. LDO Reset Timing ......................................................................................................... 314
Figure 18-1. 28-Pin SOIC Package .................................................................................................... 315
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LM3S101 Microcontroller
List of Tables
Table 1. Documentation Conventions ............................................................................................ 14
Table 3-1. Memory Map ................................................................................................................... 33
Table 4-1. Exception Types .............................................................................................................. 35
Table 4-2. Interrupts ........................................................................................................................ 36
Table 5-1. JTAG Port Pins Reset State ............................................................................................. 39
Table 5-2. JTAG Instruction Register Commands ............................................................................... 43
Table 6-1. System Control Register Map ........................................................................................... 54
Table 6-2. PLL Mode Control ........................................................................................................... 68
Table 7-1. Flash Protection Policy Combinations ............................................................................... 99
Table 7-2. Flash Register Map ........................................................................................................ 102
Table 8-1. GPIO Pad Configuration Examples ................................................................................. 117
Table 8-2. GPIO Interrupt Configuration Example ............................................................................ 118
Table 8-3. GPIO Register Map ....................................................................................................... 119
Table 9-1. Available CCP Pins ........................................................................................................ 153
Table 9-2. 16-Bit Timer With Prescaler Configurations ..................................................................... 156
Table 9-3. Timers Register Map ...................................................................................................... 162
Table 10-1. Watchdog Timer Register Map ........................................................................................ 189
Table 11-1. UART Register Map ....................................................................................................... 216
Table 12-1. SSI Register Map .......................................................................................................... 259
Table 13-1. Comparator 0 Operating Modes ..................................................................................... 287
Table 13-2. Comparator 1 Operating Modes ..................................................................................... 288
Table 13-3. Internal Reference Voltage and ACREFCTL Field Values ................................................. 288
Table 13-4. Analog Comparators Register Map ................................................................................. 290
Table 15-1. Signals by Pin Number ................................................................................................... 299
Table 15-2. Signals by Signal Name ................................................................................................. 300
Table 15-3. Signals by Function, Except for GPIO ............................................................................. 301
Table 15-4. GPIO Pins and Alternate Functions ................................................................................. 302
Table 16-1. Temperature Characteristics ........................................................................................... 304
Table 16-2. Thermal Characteristics ................................................................................................. 304
Table 17-1. Maximum Ratings .......................................................................................................... 305
Table 17-2. Recommended DC Operating Conditions ........................................................................ 305
Table 17-3. LDO Regulator Characteristics ....................................................................................... 306
Table 17-4. Detailed Power Specifications ........................................................................................ 306
Table 17-5. Flash Memory Characteristics ........................................................................................ 307
Table 17-6. Phase Locked Loop (PLL) Characteristics ....................................................................... 307
Table 17-7. Clock Characteristics ..................................................................................................... 307
Table 17-8. Analog Comparator Characteristics ................................................................................. 308
Table 17-9. Analog Comparator Voltage Reference Characteristics .................................................... 308
Table 17-10. SSI Characteristics ........................................................................................................ 308
Table 17-11. JTAG Characteristics ..................................................................................................... 310
Table 17-12. GPIO Characteristics ..................................................................................................... 312
Table 17-13. Reset Characteristics ..................................................................................................... 312
Table C-1. Part Ordering Information ............................................................................................... 332
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List of Registers
System Control .............................................................................................................................. 47
Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 56
Register 2: Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030 .................................... 58
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 59
Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 60
Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 61
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 63
Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 64
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 65
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 69
Register 10: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 70
Register 11: Clock Verification Clear (CLKVCLR), offset 0x150 ............................................................. 71
Register 12: Allow Unregulated LDO to Reset the Part (LDOARST), offset 0x160 ................................... 72
Register 13: Device Identification 1 (DID1), offset 0x004 ....................................................................... 73
Register 14: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 75
Register 15: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 76
Register 16: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 78
Register 17: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 80
Register 18: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 81
Register 19: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 82
Register 20: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 83
Register 21: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 84
Register 22: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 .................................... 85
Register 23: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 .................................. 87
Register 24: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ......................... 89
Register 25: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 .................................... 91
Register 26: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 .................................. 92
Register 27: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ......................... 93
Register 28: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................... 94
Register 29: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................... 95
Register 30: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................... 96
Internal Memory ............................................................................................................................. 97
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 103
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 104
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 105
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 107
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 108
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 109
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 110
Register 8: Flash Memory Protection Read Enable (FMPRE), offset 0x130 ......................................... 111
Register 9: Flash Memory Protection Program Enable (FMPPE), offset 0x134 .................................... 112
General-Purpose Input/Outputs (GPIOs) ................................................................................... 113
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 121
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 122
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 123
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LM3S101 Microcontroller
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 124
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 125
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 126
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 127
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 128
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 129
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 130
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 132
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 133
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 134
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 135
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 136
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 137
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 138
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 139
Register 19: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 140
Register 20: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 141
Register 21: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 142
Register 22: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 143
Register 23: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 144
Register 24: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 145
Register 25: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 146
Register 26: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 147
Register 27: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 148
Register 28: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 149
Register 29: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 150
Register 30: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 151
General-Purpose Timers ............................................................................................................. 152
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 164
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 165
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 167
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 169
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 172
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 174
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 175
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 176
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 178
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 179
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 180
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 181
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 182
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 183
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 184
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 185
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 186
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 187
Watchdog Timer ........................................................................................................................... 188
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 191
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Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 192
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 193
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 194
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 195
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 196
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 197
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 198
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 199
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 200
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 201
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 202
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 203
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 204
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 205
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 206
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 207
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 208
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 209
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 210
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 211
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 218
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 220
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 222
Register 4: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 224
Register 5: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 225
Register 6: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 226
Register 7: UART Control (UARTCTL), offset 0x030 ......................................................................... 228
Register 8: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 229
Register 9: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 231
Register 10: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 233
Register 11: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 234
Register 12: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 235
Register 13: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 237
Register 14: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 238
Register 15: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 239
Register 16: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 240
Register 17: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 241
Register 18: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 242
Register 19: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 243
Register 20: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 244
Register 21: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 245
Register 22: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 246
Register 23: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 247
Register 24: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 248
Synchronous Serial Interface (SSI) ............................................................................................ 249
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 261
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 263
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 265
Preliminary
November 29, 200712
LM3S101 Microcontroller
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 266
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 268
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 269
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 271
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 272
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 273
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 274
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 275
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 276
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 277
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 278
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 279
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 280
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 281
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 282
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 283
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 284
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 285
Analog Comparators ................................................................................................................... 286
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 291
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 292
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 293
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 294
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 295
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40 ....................................................... 295
Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 296
Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x44 ....................................................... 296
Preliminary
13November 29, 2007
About This Document
About This Document
This data sheet provides reference information for the LM3S101 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following documents are referenced by the data sheet, and available on the documentation CD
or from the Luminary Micro web site at www.luminarymicro.com:
■
ARM® Cortex™-M3 Technical Reference Manual
■
ARM® CoreSight Technical Reference Manual
■
ARM® v7-M Architecture Application Level Reference Manual
The following related documents are also referenced:
■
IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the Luminary Micro web
site for additional documentation, including application notes and white papers.
Documentation Conventions
This document uses the conventions shown in Table 1 on page 14.
Table 1. Documentation Conventions
MeaningNotation
General Register Notation
REGISTER
offset 0xnnn
Register N
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
A single bit in a register.bit
Two or more consecutive and related bits.bit field
A hexadecimal increment to a register's address, relative to that module's base address as specified
in “Memory Map” on page 33.
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
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November 29, 200714
reserved
yy:xx
Register Bit/Field
Types
R/W1C
W1C
Reset Value
Pin/Signal Notation
assert a signal
SIGNAL
SIGNAL
Numbers
X
0x
LM3S101 Microcontroller
MeaningNotation
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.RC
Software can read this field. Always write the chip reset value.RO
Software can read or write this field.R/W
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
Only a write by software is valid; a read of the register returns no meaningful data.WO
This value in the register bit diagram shows the bit/field value after any reset, unless noted.Register Bit/Field
Bit cleared to 0 on chip reset.0
Bit set to 1 on chip reset.1
Nondeterministic.-
Pin alternate function; a pin defaults to the signal without the brackets.[ ]
Refers to the physical connection on the package.pin
Refers to the electrical signal encoding of a pin.signal
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
Change the value of the signal from the logically True state to the logically False state.deassert a signal
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
Preliminary
15November 29, 2007
Architectural Overview
1 Architectural Overview
The Luminary Micro Stellaris®family of microcontrollers—the first ARM® Cortex™-M3 based
controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller
applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to
legacy 8- and 16-bit devices, all in a package with a small footprint.
The LM3S101 microcontroller is targeted for industrial applications, including test and measurement
equipment, factory automation, HVAC and building control, motion control, medical instrumentation,
fire and security, and power/energy.
In addition, the LM3S101 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S101 microcontroller is code-compatible
to all members of the extensive Stellaris®family; providing flexibility to fit our customers' precise
needs.
Luminary Micro offers a complete solution to get to market quickly, with evaluation and development
boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong
support, sales, and distributor network.
1.1 Product Features
The LM3S101 microcontroller includes the following product features:
■ 32-Bit RISC Performance
– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
– Thumb®-compatible Thumb-2-only instruction set processor core for high code density
– 20-MHz operation
– Hardware-division and single-cycle-multiplication
– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
– 14 interrupts with eight priority levels
– Unaligned data access, enabling data to be efficiently packed into memory
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
■ Internal Memory
– 8 KB single-cycle flash
• User-managed flash block protection on a 2-KB block basis
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November 29, 200716
LM3S101 Microcontroller
• User-managed flash data programming
• User-defined and managed flash-protection block
– 2 KB single-cycle SRAM
■ General-Purpose Timers
– Two General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers.
Each GPTM can be configured to operate independently:
• As a single 32-bit timer
• As one 32-bit Real-Time Clock (RTC) to event capture
• For Pulse Width Modulation (PWM)
– 32-bit Timer modes
• Programmable one-shot timer
• Programmable periodic timer
• Real-Time Clock when using an external 32.768-KHz clock as the input
• User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU
Halt flag during debug
– 16-bit Timer modes
• General-purpose timer function with an 8-bit prescaler
• Programmable one-shot timer
• Programmable periodic timer
• User-enabled stalling when the controller asserts CPU Halt flag during debug
– 16-bit Input Capture modes
• Input edge count capture
• Input edge time capture
– 16-bit PWM mode
• Simple PWM mode with software-programmable output inversion of the PWM signal
■ ARM FiRM-compliant Watchdog Timer
– 32-bit down counter with a programmable load register
– Separate watchdog clock with an enable
– Programmable interrupt generation logic with interrupt masking
– Lock register protection from runaway software
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17November 29, 2007
Architectural Overview
– Reset generation logic with an enable/disable
– User-enabled stalling when the controller asserts the CPU Halt flag during debug
■ Synchronous Serial Interface (SSI)
– Master or slave operation
– Programmable clock bit rate and prescale
– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
– Programmable data frame size from 4 to 16 bits
– Internal loopback test mode for diagnostic/debug testing
■ UART
– Fully programmable 16C550-type UART
– Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service
loading
– Programmable baud-rate generator with fractional divider
– Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
– Standard asynchronous communication bits for start, stop, and parity
– False-start-bit detection
– Line-break generation and detection
■ Analog Comparators
– Two independent integrated analog comparators
– Configurable for output to: drive an output pin or generate an interrupt
– Compare external pin input to external pin input or to internal programmable voltage reference
■ GPIOs
– 2-18 GPIOs, depending on configuration
– 5-V-tolerant input/outputs
– Programmable interrupt generation as either edge-triggered or level-sensitive
– Bit masking in both read and write operations through address lines
November 29, 200718
Preliminary
LM3S101 Microcontroller
– Programmable control for GPIO pad configuration:
• Weak pull-up or pull-down resistors
• 2-mA, 4-mA, and 8-mA pad drive
• Slew rate control for the 8-mA drive
• Open drain enables
• Digital input enables
■ Power
– On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
– Low-power options on controller: Sleep and Deep-sleep modes
– Low-power options for peripherals: software controls shutdown of individual peripherals
– User-enabled LDO unregulated voltage detection and automatic reset
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Flexible Reset Sources
– Power-on reset (POR)
– Reset pin assertion
– Brown-out (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
– Internal low drop-out (LDO) regulator output goes unregulated
■ Additional Features
– Six reset sources
– Programmable clock source control
– Clock gating to individual peripherals for power savings
– IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
– Debug access via JTAG and Serial Wire interfaces
– Full JTAG boundary scan
■ Industrial-range 28-pin RoHS-compliant SOIC package
Preliminary
19November 29, 2007
Architectural Overview
1.2 Target Applications
■ Factory automation and control
■ Industrial control power devices
■ Building and home automation
■ Stepper motors
■ Brushless DC motors
■ AC induction motors
1.3 High-Level Block Diagram
Figure 1-1 on page 20 represents the full set of features in the Stellaris®100 series of devices; not
all features may be available on the LM3S101 microcontroller.
Figure 1-1. Stellaris®100 Series High-Level Block Diagram
Preliminary
November 29, 200720
1.4 Functional Overview
The following sections provide an overview of the features of the LM3S101 microcontroller. The
page number in parenthesis indicates where that feature is discussed in detail. Ordering and support
information can be found in “Ordering and Contact Information” on page 332.
1.4.1 ARM Cortex™-M3
1.4.1.1 Processor Core (see page 27)
All members of the Stellaris®product family, including the LM3S101 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
“ARM Cortex-M3 Processor Core” on page 27 provides an overview of the ARM core; the core is
detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.1.2 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
LM3S101 Microcontroller
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
1.4.1.3 Nested Vectored Interrupt Controller (NVIC)
The LM3S101 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the ARM
Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions are
handled in Handler Mode. The processor state is automatically stored to the stack on an exception,
and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The
vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor
supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead
of state saving and restoration. Software can set eight priority levels on 7 exceptions (system
handlers) and 14 interrupts.
“Interrupts” on page 35 provides an overview of the NVIC controller and the interrupt map. Exceptions
and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.2 Motor Control Peripherals
To enhance motor control, the LM3S101 controller features Pulse Width Modulation (PWM) outputs.
21November 29, 2007
Preliminary
Architectural Overview
1.4.2.1 PWM
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
On the LM3S101, PWM motion control functionality can be achieved through:
■ The motion control features of the general-purpose timers using the CCP pins
CCP Pins (see page 158)
The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable
to support a simple PWM mode with a software-programmable output inversion of the PWM signal.
1.4.3 Analog Peripherals
For support of analog signals, the LM3S101 microcontroller offers two analog comparators.
1.4.3.1 Analog Comparators (see page 286)
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
The LM3S101 microcontroller provides two independent integrated analog comparators that can
be configured to drive an output or generate an interrupt .
A comparator can compare a test voltage against any one of these voltages:
■ An individual external reference voltage
■ A shared single external reference voltage
■ A shared internal reference voltage
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts to cause it to start
capturing a sample sequence.
1.4.4 Serial Communications Peripherals
The LM3S101 controller supports both asynchronous and synchronous serial communications with:
■ One fully programmable 16C550-type UART
■ One SSI module
1.4.4.1 UART (see page 211)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S101 controller includes one fully programmable 16C550-type UARTthat supports data
transfer speeds up to 460.8 Kbps. (Although similar in functionality to a 16C550 UART, it is not
register-compatible.)
November 29, 200722
Preliminary
Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading.
The UART can generate individually masked interrupts from the RX, TX, modem status, and error
conditions. The module provides a single combined interrupt when any of the interrupts are asserted
and are unmasked.
1.4.4.2 SSI (see page 249)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface.
The LM3S101 controller includes one SSI module that provides the functionality for synchronous
serial communications with peripheral devices, and can be configured to use the Freescale SPI,
MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also
configurable, and can be set between 4 and 16 bits, inclusive.
The SSI module performs serial-to-parallel conversion on data received from a peripheral device,
and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths
are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently.
The SSI module can be configured as either a master or slave device. As a slave device, the SSI
module can also be configured to disable its output, which allows a master device to be coupled
with multiple slave devices.
The SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
LM3S101 Microcontroller
1.4.5 System Peripherals
1.4.5.1 Programmable GPIOs (see page 113)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections.
The Stellaris®GPIO module is composed of three physical GPIO blocks, each corresponding to an
individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP
for Real-Time Microcontrollers specification) and supports 2-18 programmable input/output pins.
The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page
299 for the signals available to each GPIO pin).
The GPIO module features programmable interrupt generation as either edge-triggered or
level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in
both read and write operations through address lines.
1.4.5.2 Two Programmable Timers (see page 152)
Programmable timers can be used to count or time external events that drive the Timer input pins.
The Stellaris®General-Purpose Timer Module (GPTM) contains two GPTM blocks. Each GPTM
block provides two 16-bit timers/counters that can be configured to operate independently as timers
or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or
periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can
extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event
capture or Pulse Width Modulation (PWM) generation.
Preliminary
23November 29, 2007
Architectural Overview
1.4.5.3 Watchdog Timer (see page 188)
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or to the failure of an external device to respond in the expected way.
The Stellaris®Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, and a locking register.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
1.4.6 Memory Peripherals
The LM3S101 controller offers both single-cycle SRAM and single-cycle Flash memory.
1.4.6.1 SRAM (see page 97)
The LM3S101 static random access memory (SRAM) controller supports 2 KB SRAM. The internal
SRAM of the Stellaris®devices is located at offset 0x0000.0000 of the device memory map. To
reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced
bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
1.4.6.2 Flash (see page 98)
The LM3S101 Flash controller supports 8 KB of flash memory. The flash is organized as a set of
1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block
to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually
protected. The blocks can be marked as read-only or execute-only, providing different levels of code
protection. Read-only blocks cannot be erased or programmed, protecting the contents of those
blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only
be read by the controller instruction fetch mechanism, protecting the contents of those blocks from
being read by either the controller or by a debugger.
1.4.7 Additional Features
1.4.7.1 Memory Map (see page 33)
A memory map lists the location of instructions and data in memory. The memory map for the
LM3S101 controller can be found in “Memory Map” on page 33. Register addresses are given as
a hexadecimal increment, relative to the module's base address as shown in the memory map.
The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory
map.
1.4.7.2 JTAG TAP Controller (see page 37)
The Joint Test Action Group (JTAG) port provides a standardized serial interface for controlling the
Test Access Port (TAP) and associated test logic. The TAP, JTAG instruction register, and JTAG
data registers can be used to test the interconnects of assembled printed circuit boards, obtain
manufacturing information on the components, and observe and/or control the inputs and outputs
of the controller during normal operation. The JTAG port provides a high degree of testability and
chip-level access at a low cost.
Preliminary
November 29, 200724
The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is
transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of
this data is dependent on the current state of the TAP controller. For detailed information on the
operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test
Access Port and Boundary-Scan Architecture.
The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3
core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary
Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has
comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions.
1.4.7.3 System Control and Clocks (see page 47)
System control determines the overall operation of the device. It provides information about the
device, controls the clocking of the device and individual peripherals, and handles reset detection
and reporting.
1.4.8 Hardware Details
Details on the pins and package can be found in the following sections:
LM3S101 Microcontroller
■ “Pin Diagram” on page 298
■ “Signal Tables” on page 299
■ “Operating Characteristics” on page 304
■ “Electrical Characteristics” on page 305
■ “Package Information” on page 315
Preliminary
25November 29, 2007
Flash
SRAM
APB Bridge
ICode
DCode
GND
VDD_3.3V
LDO VDD_2.5V
LDO
System
Control
& Clocks
OSC0
OSC1
RST
PLL
Watchdog
Timer
POR
BOR
IOSC
Debug
ARM Cortex-M3
NVIC
CM3Core
Bus
Peripheral Bus
UART0
GPIO Port B
PA1/U0Tx
PA0/U0Rx
GPIO Port A
SSI
PA3/SSIFss
PA2/SSIClk
PA5/SSITx
PA4/SSIRx
GPIO Port C
JTAG
SWD/SWO
PC1/TMS/SWDIO
PC0/TCK/SWCLK
PC3/TDO/SWO
PC2/TDI
PB1/32KHz
PB0/CCP0
PB3
PB2
PB5/C0o/C1PB4/C0-
PB6/C0+
GPTimer1
GPTimer0
PB7/TRST
Analog
Comparators
(2 KB)
(8 KB)
(20 MHz)
LM3S101LM3S101
Architectural Overview
1.4.9 System Block Diagram
Figure 1-2. LM3S101 Controller System-Level Block Diagram
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Preliminary
2 ARM Cortex-M3 Processor Core
The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that
meets the needs of minimal memory implementation, reduced pin count, and low power consumption,
while delivering outstanding computational performance and exceptional system response to
interrupts. Features include:
■ Compact core.
■ Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory
size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of
memory for microcontroller class applications.
■ Rapid application execution through Harvard architecture characterized by separate buses for
instruction and data.
■ Exceptional interrupt handling, by implementing the register manipulations required for handling
an interrupt in hardware.
■ Migration from the ARM7™ processor family for better performance and power efficiency.
LM3S101 Microcontroller
■ Full-featured debug solution with a:
– Serial Wire JTAG Debug Port (SWJ-DP)
– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
– Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
– Instrumentation Trace Macrocell (ITM) for support of printf style debugging
– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
The Stellaris®family of microcontrollers builds on this core to bring high-performance 32-bit computing
to cost-sensitive embedded microcontroller applications, such as factory automation and control,
industrial control power devices, building and home automation, and stepper motors.
For more information on the ARM Cortex-M3 processor core, see the ARM® Cortex™-M3 Technical
Reference Manual. For information on SWJ-DP, see the ARM® CoreSight Technical Reference
Manual.
Preliminary
27November 29, 2007
Private Peripheral
Bus
(internal)
Data
Watchpoint
and Trace
Interrupts
Debug
Sleep
Instrumentation
Trace Macrocell
Trace
Port
Interface
Unit
CM3 Core
Instructions Data
Flash
Patch and
Breakpoint
Adv. High-
Perf. Bus
Access Port
Nested
Vectored
Interrupt
Controller
Serial Wire JTAG
Debug Port
Bus
Matrix
Adv. Peripheral
Bus
I-code bus
D-code bus
System bus
ROM
Table
Private
Peripheral
Bus
(external)
Serial
Wire
Output
Trace
Port
(SWO)
ARM
Cortex-M3
ARM Cortex-M3 Processor Core
2.1 Block Diagram
Figure 2-1. CPU Block Diagram
2.2 Functional Description
Important:
Luminary Micro has implemented the ARM Cortex-M3 core as shown in Figure 2-1 on page 28. As
noted in the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3 components are
flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the MPU, and the Nested
Vectored Interrupt Controller (NVIC). Each of these is addressed in the sections that follow.
2.2.1 Serial Wire and JTAG Debug
Luminary Micro has replaced the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant
Serial Wire JTAG Debug Port (SWJ-DP) interface. This means Chapter 12, “Debug Port,” of the
ARM® Cortex™-M3 Technical Reference Manual does not apply to Stellaris®devices.
The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the
CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP.
2.2.2 Embedded Trace Macrocell (ETM)
ETM was not implemented in the Stellaris®devices. This means Chapters 15 and 16 of the ARM®
Cortex™-M3 Technical Reference Manual can be ignored.
The ARM® Cortex™-M3 Technical Reference Manual describes all the features of an
ARM Cortex-M3 in detail. However, these features differ based on the implementation.
This section describes the Stellaris®implementation.
Preliminary
November 29, 200728
2.2.3 Trace Port Interface Unit (TPIU)
ATB
Interface
Asynchronous FIFO
APB
Interface
Trace Out
(serializer)
Debug
ATB
Slave
Port
APB
Slave
Port
Serial Wire
Trace Port
(SWO)
The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace
Port Analyzer. The Stellaris®devices have implemented TPIU as shown in Figure 2-2 on page 29.
This is similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference
Manual, however, SWJ-DP only provides SWV output for the TPIU.
Figure 2-2. TPIU Block Diagram
LM3S101 Microcontroller
2.2.4 ROM Table
The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical
Reference Manual.
2.2.5 Memory Protection Unit (MPU)
The LM3S101 controller does not include the memory protection unit (MPU) of the ARM Cortex-M3.
2.2.6 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC):
■ Facilitates low-latency exception and interrupt handling
■ Controls power management
■ Implements system control registers
The NVIC supports up to 240 dynamically reprioritizable interrupts each with up to 256 levels of
priority. The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge
of the stacked (nested) interrupts to enable tail-chaining of interrupts.
You can only fully access the NVIC from privileged mode, but you can pend interrupts in user-mode
if you enable the Configuration Control Register (see the ARM® Cortex™-M3 Technical Reference
Manual). Any other user-mode access causes a bus fault.
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Preliminary
ARM Cortex-M3 Processor Core
All NVIC registers are accessible using byte, halfword, and word unless otherwise stated.
All NVIC registers and system debug registers are little endian regardless of the endianness state
of the processor.
2.2.6.1 Interrupts
The ARM® Cortex™-M3 Technical Reference Manual describes the maximum number of interrupts
and interrupt priorities. The LM3S101 microcontroller supports 14 interrupts with eight priority levels.
2.2.6.2 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
Functional Description
The timer consists of three registers:
■ A control and status counter to configure its clock, enable the counter, enable the SysTick
interrupt, and determine counter status.
■ The reload value for the counter, used to provide the counter's wrap value.
■ The current value of the counter.
A fourth register, the SysTick Calibration Value Register, is not implemented in the Stellaris®devices.
When enabled, the timer counts down from the reload value to zero, reloads (wraps) to the value
in the SysTick Reload Value register on the next clock edge, then decrements on subsequent clocks.
Writing a value of zero to the Reload Value register disables the counter on the next wrap. When
the counter reaches zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
Writing to the Current Value register clears the register and the COUNTFLAG status bit. The write
does not trigger the SysTick exception logic. On a read, the current value is the value of the register
at the time the register is accessed.
If the core is in debug state (halted), the counter will not decrement. The timer is clocked with respect
to a reference clock. The reference clock can be the core clock or an external clock source.
November 29, 200730
Preliminary
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