TEXAS INSTRUMENTS LM20125 Technical data

LM20125,LM26480,LM3743,LM3880,LMZ10504,
LMZ14203

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Literature Number: ZHCA410

POWER designer

Expert tips, tricks, and techniques for powerful designs

No. 121

national.com/powerdesigner

Power Supply Design Considerations for
Modern FPGAs

— By Dennis Hudgins, Low Voltage Applications Manages, Tucson Design Center

Introduction

Today’s FPGAs tend to operate at lower voltages and higher currents than their predecessors. Consequently,
power supply requirements may be more demanding, requiring special attention to features deemed less
important in past generations. Failure to consider the output voltage, sequencing, power-on, and soft-start
requirements can result in unreliable power-up or potential damage to FPGAs.

Output Voltage Requirements

 e fi rst criteria to consider when designing power supplies for FPGAs are the voltage requirements for the
diff erent supply rails. Most FPGAs have specifi cations for the CORE and IO voltage rails and many require
additional auxiliary rails that may power internal clocks, phase-lock loops or transceivers. Table 1 provides
the voltage levels and tolerances for some of the newest FPGAs.

FPGA Core Core Tolerance Auxiliary Power Auxiliary Tolerance IO Voltage* IO Tolerance*

Spartan-6 1.2 5% 2.5 or 3.3 5% 1.2 to 3.3 1.1 to 3.45

Spartan-6 (-1L) 1.0 5% 2.5 or 3.3 5% 1.2 to 3.3 1.1 to 3.45

Virtex-6 1.0 5% 2.5 5% 1.2 to 2.5 1.14 to 2.625

Virtex-6 (-1L) 0.9 30 mV 2.5 5% 1.2 to 2.5 1.14 to 2.625

Stratix-IV (GX and E) 0.9 30 mV 2.5 (VCCA_PLL) 5% 1.2 to 3.0 5%

Stratix-IV (GT) 0.95 30 mV 2.5 (VCCA_PLL) 5% 1.2 to 3.0 5%

Cyclone-IV (GX) 1.2 40 mV 2.5 5% 1.2 to 3.3 5%

Cyclone-IV (E) 1.0 * 2.5 5% 1.2 to 3.3 5%

Arria-II 0.9 30 mV 2.5 (VCCA_PLL) 5% 1.2 to 3.3 5%

Table 1. Voltage Requirements for Common Modern FPGAs

0.90 (VCCD_PLL) 30 mV

0.95 (VCCD_PLL) 30 mV

0.90 (VCCD_PLL) 30 mV

* Some values may differ slightly from those listed. Please consult your FPGA’s associated documentation for details.

POWER designer

Power Supply Design Considerations for Modern FPGAs

Since FPGAs generally specify several permissible
voltage levels for the IO, the voltage selected is dictated
by the external digital circuitry. To provide fl exibility,
FPGAs will generally provide multiple IO banks that
can be powered separately, allowing FPGAs to
interface with various logic families. For simplicity,
the solutions illustrated in this article will assume all
IO banks are powered off of a single power supply rail.
 e core voltage supplies the internal logic
confi guration blocks of FPGAs and is where many of
the internal digital path processes occur. As such, the
current demanded by the core will vary greatly
depending on the percent utilization of FPGAs.
Vendors of the FPGAs described herein provide design
tools that estimate core current requirements based on
the internal blocks utilized.

Over time, the voltages used to power the core have
steadily dropped. Modern cores utilize 65 nm, 45 nm
or even 40 nm geometry silicon processes and may
operate from voltages as low as 0.9V.  ese lower
voltages are valuable to reduce power dissipation in
FPGAs.  e trade off , however, is that keeping within
the voltage tolerance requirements becomes more
challenging for the power supply designer.

Output Capacitance and Transient Considerations

A good power supply design will keep the core
voltage within tolerance at all times. Most of the
power supply transient concerns can be managed by
properly selecting the bypass and bulk capacitances for
the power supply. In general, every core ball or pin
connection should be bypassed directly under FPGAs
with high-quality X5R or X7R ceramic capacitors.
 e values recommended for each of these capacitors
range from 1 μF to 10 μF and will generally be
specifi ed by FPGA manufacturers.  ese capacitors
provide a charge when FPGAs need to rapidly draw
large spikes of current during high speed operations.
Likewise, the bulk capacitance should be selected to
provide charge during large steps of current, which
tend to occur during power-on, application-start,
or a change in application state. Before increasing
the amount of output capacitance to solve transient
droop issues, changes to the power supply should be
made that do not involve an increase in PCB area or
component count.

 e response to a load transient is dictated by the
large signal response time that consists of ramping the
inductor current to the correct operating level and the
small signal response of the control loop.

Transient Response Optimizations

To optimize the transient response, ensure the supply
is switching at the highest possible frequency.  is
will allow use of a small inductor and reduce the large
signal response time. Typical high performance power
supply solutions can be designed to have crossover
frequencies as high as one-tenth to one-fi fth the
switching frequency. Pushing the crossover frequency
too high may result in ringing at the output during
a load transient indicating poor phase margin. Any
ringing in the output should be avoided as this may
result in instability with external component variation
or when operating at temperature extremes.

AUX Voltage Considerations

Many FPGAs require a third power supply commonly
referred to as the auxiliary rail or AUX. Since the AUX
rail may power internal clocks, phase-lock loops, or
transceivers, the amount of output voltage ripple on
this rail should be minimized. In some cases, additional
ferrite beads and capacitors fi ltering may be needed to
meet the application or FPGA noise requirements. In
applications where noise is extremely important, a low
noise, high PSRR LDO, like the LP3878, should be
considered instead of a switching converter.

Sequencing Requirements

 e sequencing requirements vary depending on
the particular FPGA being used and many newer
FPGAs specify that no sequencing is required. While
this is technically true for the FPGA, it is not the
optimal way to design a power solution. National
Semiconductor off ers several devices to address
sequencing requirements.  e LM3880 is designed to
address sequential sequencing of multiple supply rails.
 is device is available in a small SOT-23 package and
can sequence up to three supply rails. Many options
are available to control the up and down, three-fl ag
outputs sequencing timing. National also provides
devices to support customized fl ag order and timing.

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