Texas Instruments DS16EV5110 Operator's Manual

DVI / HDMI

Source

text

DS16EV5110

DeS / Display

Controller

DVI / HDMI Sink

20m 28 AWG DVI / HDMI Cable

DS16EV5110

www.ti.com

DS16EV5110 Video Equalizer (3D+C) for DVI, HDMI Sink-Side Applications

Check for Samples: DS16EV5110

1

FEATURES

2

• 8 Levels of Equalization Settable by 3 Pins or
Through the SMBus Interface

• DC-Coupled Inputs and Outputs

• Optimized for Operation From 250 Mbps to

2.25 Gbps in Support of UXGA, 480 I/P, 720 I/P, DESCRIPTION 1080 I, and 1080 P With 8, 10, and 12-Bit Color Depth Resolutions

• Two DS16EV5110 Devices Support DVI/HDMI
Dual Link

• DVI 1.0, and HDMI 1.3a Compatible TMDS
Interface

• Clock Channel Signal Detect (LOS)

• Enable for Power Savings Standby Mode

• System Management Bus (SMBus) Provides
Control of Boost, Output Amplitude, Enable,
and Clock Channel Signal Detect Threshold

• Low Power Consumption: 475mW (Typical)

• 0.13 UI Total Jitter at 1.65 Gbps Including
Cable

• Single 3.3V Power Supply

• Small 7mm x 7mm, 48-Pin Leadless WQFN
Package

• -40°C to +85°C Operating Temperature Range

• Extends TMDS Cable Reach Over:

1. > 40 Meters 24 AWG DVI Cable (1.65Gbps)

2. > 20 Meters 28 AWG DVI Cable (1.65Gbps)

3. > 20 Meters Cat5/Cat5e/Cat6 Cables
(1.65Gbps)

4. > 20 Meters 28 AWG HDMI Cables
(2.25Gbps)

APPLICATIONS

• Sink-Side Video Applications

• Projectors

• High Definition Displays

The DS16EV5110 is a multi-channel equalizer
optimized for video cable extension sink-side
applications. It operates between 250Mbps and

2.25Gbps with common applications at 1.65Gbps and

2.25Gbps (per data channel). It contains three
Transition-Minimized Differential Signaling (TMDS)
data channels and one clock channel as commonly
found in DVI and HDMI cables. It provides
compensation for skin-effect and dielectric losses, a
common phenomenon when transmitting video on
commercially available high definition video cables.

The inputs conform to DVI and HDMI requirements
and features programmable levels of input
equalization. The programmable levels of
equalization provide optimal signal boost and reduces
inter-symbol interference. Eight levels of boost are
selectable via a pin interface or by the optional
System Management Bus.

The clock channel is optimized for clock rates of up to
225 MHz and features a signal detect circuit. To
maximize noise immunity, the DS16EV5110 features
a signal detector with programmable thresholds. The
threshold is adjustable through a System
Management Bus (SMBus) interface.

The DS16EV5110 also provides support for system
power management via output enable controls.
Additional controls are provided via the SMBus
enabling customization and optimization for specific
applications requirements. These controls include
programmable features such as output amplitude and
boost controls as well as system level diagnostics.

SNLS249M –FEBRUARY 2007–REVISED APRIL 2013

Typical Application

1

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 2007–2013, Texas Instruments Incorporated

DS16EV5110

SNLS249M –FEBRUARY 2007–REVISED APRIL 2013

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PIN DESCRIPTIONS

Pin Name Pin Number I/O

HIGH SPEED DIFFERENTIAL I/O

C_IN− 1 I, CML Inverting and non-inverting TMDS Clock inputs to the equalizer. An on-chip 50Ω terminating
C_IN+ 2 resistor connects C_IN+ to VDD and C_IN- to VDD.

D_IN0− 4 I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50Ω terminating
D_IN0+ 5 resistor connects D_IN0+ to VDD and D_IN0- to VDD.

D_IN1− 8 I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50Ω terminating
D_IN1+ 9 resistor connects D_IN1+ to VDD and D_IN1- to VDD.

D_IN2− 11 I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50Ω terminating
D_IN2+ 12 resistor connects D_IN2+ to VDD and D_IN2- to VDD.

C_OUT- 36 O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
C_OUT+ 35

D_OUT0− 33 O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
D_OUT0+ 32

D_OUT1– 29 O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
D_OUT1+ 28

D_OUT2− 26 O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
D_OUT2+ 25

Equalization Control

BST_0 23 I, LVCMOS BST_0, BST_1, and BST_2 select the equalizer boost level for EQ channels. BST_0, BST_1,
BST_1 14 and BST_2 are internally pulled Low. See Table 2.
BST_2 37

Device Control

EN 44 I, LVCMOS Enable Equalizer input. When held High, normal operation is selected. When held Low,

FEB 21 I, LVCMOS Force External Boost. When held High, the equalizer boost setting is controlled by the

SD 45 O, LVCMOS Equalizer Clock Channel Signal Detect Output. Produces a High when signal is detected.

POWER

V

DD

GND 22, 24, GND Ground reference. GND should be tied to a solid ground plane through a low impedance

Exposed Pad DAP GND The exposed pad at the center of the package must be connected to the ground plane.

System Management Bus (SMBus) Interface Control Pins

SDA 18 IO, LVCMOS SMBus Data Input / Output. Internally pulled High to 3.3V with High-Z pull up.
SDC 17 I, LVCMOS SMBus Clock Input. Internally pulled High to 3.3V with High-Z pull up.
CS 16 I, LVCMOS SMBus Chip select. When held High, the equalizer SMBus register is enabled. When held

Other

Reserv 19, 20, 38, Reserved. Do not connect.

(1) Note: I = Input,O = Output, IO =Input/Output,

3, 6, 7, Power VDDpins should be tied to the VDDplane through a low inductance path. A 0.1µF bypass
10, 13, capacitor should be connected between each VDDpin to the GND planes.

15, 46

27, 30, path.

31, 34

39, 40,41,

42, 43, 47,

48

(1)

, Type Description

standby mode is selected. EN is internally pulled High. Signal is global to all Data and Clock
channels.

BST_[0:2] pins. When held Low, the equalizer boost level is controlled through the SMBus
(see Table 1) control pins. FEB is internally pulled High.

Low, the equalizer SMBus register is disabled. CS is internally pulled Low. CS is internally
gated with SDC.

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DAP = GND

DS16EV5110SQ

(Top View)

1
2
3
4
5
6
7
8

9
10
11
12

13

14

15

16

17

18

19

20

21

22

23

24

36
35
34
33
32
31
30
29
28
27
26
25

48

47

46

45

44

43

42

41

40

39

38

37

D_IN2+

D_IN2-

D_IN1+

D_IN1-

D_IN0+

D_IN0-

C_IN+

C_IN-

D_OUT2+

D_OUT2-

D_OUT1+

D_OUT1-

D_OUT0+

D_OUT0-

C_OUT+

C_OUT-

VDD

VDD
VDD

VDD GND

GND

GND

GND

VDD

VDD

GND

GND

BST_1

BST_0

CS

SDC

SDA

Reserv

VDD

SD

EN

Reserv

Reserv

Reserv

Reserv

Reserv

Reserv

Reserv

BST_2

Reserv

FEB

Reserv

DS16EV5110

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Connection Diagram

SNLS249M –FEBRUARY 2007–REVISED APRIL 2013

TOP VIEW — Not to Scale

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings

(1)(2)

Supply Voltage (VDD) -0.5V to +4.0V
LVCMOS Input Voltage -0.5V + 4.0V
LVCMOS Output Voltage -0.5V to 4.0V
CML Input/Output Voltage -0.5V to 4.0V
Junction Temperature +150°C
Storage Temperature -65°C to +150°C
Lead Temperature (Soldering, 5 sec.) +260°C

ESD Rating

HBM, 1.5 kΩ, 100 pF >8 kV
CML Inputs >10 kV

Thermal Resistance θJA, No Airflow 30°C/W

(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of

device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute
Maximum Numbers are ensured for a junction temperature range of –40°C to +125°C. Models are validated to Maximum Operating
Voltages only.

(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

Recommended Operating Conditions

(1)(2)

Min Typ Max Units

Supply Voltage (VDDto GND) 3.0 3.3 3.6 V
Ambient Temperature -40 25 +85 °C

(1) Typical values represent most likely parametric norms at VDD= 3.3V, TA= 25°C, and at the Recommended Operation Conditions at the

time of product characterization and are not ensured.

(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes.

Electrical Characteristics

Over recommended operating supply and temperature ranges unless other specified.

Symbol Parameter Conditions Min Typ Max Units

LVCMOS DC SPECIFICATIONS

I

IH-PU

I

IH-PD

I

IL-PU

I

IL-PD

V

IH

V

IL

V

OH

V

OL

POWER

PD Power Dissipation EN = High, Device Enabled 475 700 mW

(1) Typical values represent most likely parametric norms at VDD= 3.3V, TA= 25°C, and at the Recommended Operation Conditions at the

time of product characterization and are not ensured.

(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes.

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High Level Input Leakage Current LVCMOS pins with internal pull-up

resistors

High Level Input Leakage Current LVCMOS pins with internal pull-

down resistors

Low Level Input Leakage Current LVCMOS pins with internal pull-up

resistors

Low Level Input Leakage Current LVCMOS pins with internal pull-

down resistors
High Level Input Voltage 2.0 VDD V
Low Level Input Voltage 0 0.8 V
High Level Output Voltage SD Pin, IOH= -3mA 2.4 V
Low Level Output Voltage SD Pin, IOL= 3mA 0.4 V

EN = Low, Power Down Mode 70 mW

Product Folder Links: DS16EV5110

(1)(2)

-10 +10 μA

80 105 μA

-20 -10 μA

-10 +10 μA

DS16EV5110

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SNLS249M –FEBRUARY 2007–REVISED APRIL 2013

Electrical Characteristics (continued)

Over recommended operating supply and temperature ranges unless other specified.

Symbol Parameter Conditions Min Typ Max Units

N Supply Noise Tolerance

CML INPUTS

V

TX

V

ICMDC

V

IN

R

LI

R

IN

Input Voltage Swing (Launch Measured differentially at TPA
Amplitude) (Figure 2)

Input Common-Mode Voltage DC-Coupled Requirement

Input Voltage Swing Measured differentially at TPB

Differential Input Return Loss 100 MHz– 825 MHz, with fixture's

Input Resistance IN+ to VDD and IN− to VDD 45 50 55 Ω

CML OUTPUTS

V

O

V

OCM

tR, t

t

CCSK

t

D

F

Output Voltage Swing Measured differentially with OUT+

Output common-mode Voltage Measured Single-ended VDD-0.3 VDD-0.2 V
Transition Time 20% to 80% of differential output

Inter Pair Channel-to-Channel Difference in 50% crossing
Skew (all 4 Channels) between shortest and longest 25 ps

Latency 350 ps

OUTPUT JITTER

TJ1 Total Jitter at 1.65 Gbps 20m 28 AWG STP DVI Cable

TJ2 Total Jitter at 2.25 Gbps 20m 28 AWG STP DVI Cable

TJ3 Total Jitter at 165 MHz Clock Paths

TJ4 Total Jitter at 225 MHz Clock Paths

RJ Random Jitter See

BIT RATE

F

CLK

Clock Frequency Clock Path

BR Bit Rate Data Path

(3) Allowed supply noise (mV
(4) Specification is ensured by characterization and is not tested in production.

P-P

(5) Deterministic jitter is measured at the differential outputs (TPC of Figure 2), minus the deterministic jitter before the test channel (TPA of

Figure 2). Random jitter is removed through the use of averaging or similar means.

(6) Total Jitter is defined as peak-to-peak deterministic jitter from()+ 14.2 times random jitter in ps
(7) Random jitter contributed by the equalizer is defined as sq rt (J

TPC of Figure 2; JINis the random jitter at the input of the equalizer in ps

(3)

DC to 50MHz 100 mV

Measured at TPA (Figure 2)

(Figure 2)

effect de-embedded

and OUT− terminated by 50Ω to 800 1200 mV
VDD

voltage, measured within 1" from 75 240 ps
output pins.

channels

Data Paths 0.13 0.17 UI
EQ Setting 0x04 PRBS7

Data Paths 0.2 UI
EQ Setting 0x04 PRBS7

Clock Pattern

Clock Pattern

(6) (7)

(4)

(4)

sine wave) under typical conditions.

(4) (5) (6)

(4) (5) (6)

2

OUT

(4) (5) (6)

(4) (5) (6)

2

− J

). J

IN

OUT

, see TPA of Figure 2.

rms

is the random jitter at equalizer outputs in ps

(1)(2)

800 1200 mV

VDD-0.3 VDD-0.2 V

120 mV

10 dB

0.165 UI

0.165 UI
3 ps

25 225 MHz

0.25 2.25 Gbps

.

rms

rms

, see

P-P

P-P

P-P

P-P

P-P

P-P

P-P

P-P

rms

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SNLS249M –FEBRUARY 2007–REVISED APRIL 2013

Electrical Characteristics — System Management Bus Interface

(1)(2)

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Over recommended operating supply and temperature ranges unless other specified.

Symbol Parameter Conditions Min Typ Max Units

System Bus Interface — DC Specifications

V

IL

V

IH

I

PULLUP

V

DD

I

LEAK-Bus

I

LEAK-Pin

C

I

R

TERM

System Bus Interface Timing Specification

FSMB Bus Operating Frequency See
TBUF Bus Free Time Between Stop and Start

THD:STA Hold Time After (Repeated) Start Condition. At I

TSU:STA Repeated Start Condition Setup Time 4.7 µs
TSU:STO Stop Condition Setup Time 4.0 µs
THD:DAT Data Hold Time 300 ns
TSU:DAT Data Setup Time 250 ns
T

TIMEOUT

T

LOW

T

HIGH

T

:SEXT Cumulative Clock Low Extend Time (Slave See

LOW

t

F

t

R

t

POR

Data, Clock Input Low Voltage 0.8 V
Data, Clock Input High Voltage 2.8 V
Current through pull-up resistor or current VOL = 0.4V

source

10 mA

DD

Nominal Bus Voltage 3.0 3.6 V
Input Leakage per bus segment See

(3)

—200 +200 µA

Input Leakage per device pin —15 µA

DD3.3

PULLUP

(3) (4)

(3) (4) (5)

(6)

(6)

, Max

10 pF

1000 Ω

10 100 kHz

4.7 µs

4.0 µs

25 35 ms

Capacitance for SDA and SDC See
Termination Resistance V

Condition

First CLK generated after this period.

Detect Clock Low Timeout See
Clock Low Period 4.7 µs
Clock High Period See

Device)
Clock/Data Fall Time See
Clock/Data Rise Time See
Time in which a device must be operational See

after power-on reset

(6)
(6)

(6)
(6)

(6)

4.0 50 µs
2 ms

300 ns

1000 ns

500 ms

V

(1) Typical values represent most likely parametric norms at VDD= 3.3V, TA= 25°C, and at the Recommended Operation Conditions at the

time of product characterization and are not ensured.

(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes.
(3) Recommended value. Parameter not tested in production.
(4) Recommended maximum capacitance load per bus segment is 400pF.
(5) Maximum termination voltage should be identical to the device supply voltage.
(6) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1

SMBus common AC specifications for details.

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Pattern Generator

100 mV

PP

Differential

SMA to HDMI Adapter

DS

16

EV

5110

SMA to HDMI Adapter

Jitter Test Instrument

Coax

SMA

Coax

SMA

Coax

SMA

Coax

SMA

Coax

SMA

Coax

SMA

Coax

SMA

VDD

RLoadRLoad

VDD

RLoadRLoad

VDD

RLoadRLoad

RLoadRLoad

Coax

SMA

VDD

RLoadRLoad

VDD

RLoadRLoad

VDD

RLoadRLoad

VDD

RLoadRLoad

28 AWG

DVI/HDMI

Cable

VDD

TPCTPBTPA

SMA

SMA

SMA

SMA

SMA

SMA

SMA

SMA

Coax

Coax

Coax

Coax

Coax

Coax

Coax

Coax

Clk­Clk+

Data0­Data0+

Data1­Data1+

Data2­Data2+

SP

t

BUF

t

HD:STA

t

LOW

t

R

t

HD:DAT

t

HIGH

t

F

t

SU:DAT

t

SU:STA

ST

SP

t

SU:STO

SDC

SDA

CS

t

SU:CS

ST

DS16EV5110

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SNLS249M –FEBRUARY 2007–REVISED APRIL 2013

TIMING DIAGRAMS

Figure 1. SMBus Timing Diagram

Figure 2. Test Setup Diagram for Jitter Measurement

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SYSTEM MANAGEMENT BUS (SMBUS) AND CONFIGURATION REGISTERS

The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. The use of the
Chip Select signal is required. Holding the CS pin High enables the SMBus port allowing access to the
configuration registers. Holding the CS pin Low disables the device's SMBus allowing communication from the
host to other slave devices on the bus. In the STANDBY state, the System Management Bus remains active.
When communication to other devices on the SMBus is active, the CS signal for the DS16EV5110s must be
driven Low.

The address byte for all DS16EV5110s is AC'h. Based on the SMBus 2.0 specification, the DS16EV5110 has a
7-bit slave address of 1010110'b. The LSB is set to 0'b (for a WRITE), thus the 8-bit value is 1010 1100 'b or
AC'h.

The SDC and SDA pins are 3.3V LVCMOS signaling and include high-Z internal pull up resistors. External low
impedance pull up resistors maybe required depending upon SMBus loading and speed. Note, these pins are not
5V tolerant.

Transfer of Data via the SMBus

During normal operation the data on SDA must be stable during the time when SDC is High.
There are three unique states for the SMBus:

START: A High-to-Low transition on SDA while SDC is High indicates a message START condition.
STOP: A Low-to-High transition on SDA while SDC is High indicates a message STOP condition.
IDLE: If SDC and SDA are both High for a time exceeding t

are High for a total exceeding the maximum specification for t

SMBus Transactions

The device supports WRITE and READ transactions. See Register Description table for register address, type
(Read/Write, Read Only), default value and function information.

Writing a Register

To write a register, the following protocol is used (see SMBus 2.0 specification).

1. The Host (Master) selects the device by driving its SMBus Chip Select (CS) signal High.

2. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.

3. The Device (Slave) drives the ACK bit (“0”).

4. The Host drives the 8-bit Register Address.

5. The Device drives an ACK bit (“0”).

6. The Host drive the 8-bit data byte.

7. The Device drives an ACK bit (“0”).

8. The Host drives a STOP condition.

9. The Host de-selects the device by driving its SMBus CS signal Low.

The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may
now occur.

Reading a Register

To read a register, the following protocol is used (see SMBus 2.0 specification).

1. The Host (Master) selects the device by driving its SMBus Chip Select (CS) signal High.

2. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.

3. The Device (Slave) drives the ACK bit (“0”).

4. The Host drives the 8-bit Register Address.

5. The Device drives an ACK bit (“0”).

6. The Host drives a START condition.

7. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.

8. The Device drives an ACK bit “0”.

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from the last detected STOP condition or if they

BUF

then the bus will transfer to the IDLE state.

HIGH