Texas Instruments DEM-DAI3052A User Manual

DEM-DAI3052A

User's Guide

September 2006 DAP

SLEU079

DEM-DAI3052A

User's Guide

Literature Number: SLEU079

September 2006

Contents

1 Description ................................................................................................................ 5

1.1 Block Diagram ....................................................................................................... 6

1.2 Basic Connection and Operation ................................................................................. 7

1.2.1 Basic Connections and Configurations ................................................................. 7

1.2.2 Configuration Controls .................................................................................... 8

1.2.3 DEM-DAI3052A EVM Operation ....................................................................... 11

1.3 Typical Performance and Measurement Example ............................................................ 12

2 Schematics and Printed Circuit Boards ....................................................................... 19

2.1 DEM-DAI3052A Schematics ..................................................................................... 20

2.2 DEM-DAI3052A Bill of Materials (BOM) ........................................................................ 24

2.3 DEM-DAI3052A Printed Circuit Boards ........................................................................ 27

SLEU079 – September 2006 Contents 3

Submit Documentation Feedback

List of Figures

1-1 DEM-DAI3052A Block Diagram ............................................................................................ 6

2-1 DEM-DAI3052A Power and Interface Section .......................................................................... 20

2-2 DEM-DAI3052A Digital Section (Digital Audio Interface) ............................................................. 21

2-3 DEM-DAI3052A Analog Section .......................................................................................... 22

2-4 DEM-DAI3052A DUT Section ............................................................................................ 23

2-5 DEM-DAI3052A Top Silkscreen .......................................................................................... 27

2-6 DEM-DAI3052A Top Copper ............................................................................................. 28

2-7 DEM-DAI3052A Bottom Copper .......................................................................................... 29

2-8 DEM-DAI3052A Form, Dimension, and Drill ............................................................................ 30

List of Tables

1-1 CN057: 3.3-V Power Source Selection ................................................................................... 8

1-2 SW001: SPDIF Input Selection ............................................................................................ 8

1-3 SW051: SPDIF Output Selection .......................................................................................... 8

1-4 SW052: SPDIF Output Source Signal Selection ........................................................................ 8

1-5 SW004: DIR1703 Clock Source Selection ............................................................................... 8

1-6 SW003: DIR1703 System Clock Selection ............................................................................... 8

1-7 SW005: DIT4096 Master Clock Selection ................................................................................ 8

1-8 JP001: DIR1703 Crystal Selection for Crystal Mode System Clock and Default Sampling Frequency .......... 9

1-9 SW003: DIR1703 Format Selection ....................................................................................... 9

1-10 SW005: DIT4096 Format Selection ....................................................................................... 9

1-11 SW006: DIT4096 Channel Status Information Control ................................................................. 9

1-12 SW053: Mode Control ....................................................................................................... 9

1-13 JP051: DOUTS or MDO Setting for Mode Control ..................................................................... 10

1-14 JP109: DUT (PCM3052A) V

1-15 JP110: MIC Input Configuration .......................................................................................... 10

1-16 JP101-104: Lineout LPF Selection ....................................................................................... 10

1-17 JP105, JP106: ADC Input Level Selection .............................................................................. 10

1-18 JP107: Bridge for PCM Audio Interface ................................................................................. 10

1-19 JP108: Bridge for Mode Control Interface .............................................................................. 10

Supply Voltage Selection ............................................................ 10

4 List of Figures SLEU079 – September 2006

Submit Documentation Feedback

SLEU079 – September 2006

Description

The DEM-DAI3052A is an evaluation board for the PCM3052A, a 96-kHz, 24-bit stereo audio coder/decoder (codec), with digital audio interface receiver/transmitter, optical and coaxial interface, onboard clock generator, –6-dB amplifier with LPF for ADC and 4-dB amplifier with LPF for DAC, switches or jumpers for mode or clock control, and interface connector with PC for serial mode control.

The DEM-DAI3052A operates under 5-V and ± 15-V analog power supplies, with 1-Vrms or 2-Vrms unbalanced analog signal input and 2-Vrms unbalanced analog signal output.

Topic .................................................................................................. Page

1.1 Block Diagram ............................................................................ 6

1.2 Basic Connection and Operation .................................................. 7

1.3 Typical Performance and Measurement Example .......................... 12

Chapter 1

SLEU079 – September 2006 Description 5

Submit Documentation Feedback

www.ti.com

SW003

System Clock

Data Format

SW004

Clock Mode

JP001

X’tal Frequency

System Clock

DIR1703

24.576MHz

PCM3052A

(Slave Only)

LPF

2 Vrms

LPF

R-ch

LPF

JP107

JP105

JP106

DIT4096

SW005

System Clock

Data Format

SW006

74HCT244

OPT. IN

COAX. IN

S/PDIF Input

SW001

SW051

1/2 Vrms

S/PDIF Output

R-ch

OPT. OUT

COAX. OUT

DAC Output

ADC Input

MIC Input

Channel Status

L-ch

10/20 mVrms

L-ch

Block Diagram

1.1 Block Diagram

Figure 1-1. DEM-DAI3052A Block Diagram

Description 6 SLEU079 – September 2006

Submit Documentation Feedback

www.ti.com

1.2 Basic Connection and Operation

1.2.1 Basic Connections and Configurations

• Install REGTEST_I2C and other programs attached to the EVM into the appropriate folder of the PC that is used to control this EVM.

• Confirm EVM settings. SW053 must be all OFF (High). JP051 SCL, SDA, MDO, and DOUTS must be OFF, OFF, OFF, and ON, respectively.

• Connect the 5-V and ± 15-V power supplies to V

3.3 V is used on CN056, jumper CN057 must be removed. The ± 15-V power supplies are required for 2-Vrms input and 2-Vrms output.

• Connect the SPDIF input to CN059 (coaxial) or U053 (optical) and output to CN058 (coaxial) or U052 (optical), and select coaxial or optical for SPDIF input and output using SW001 and SW051. Also, select the SPDIF output source from the analog-to-digital converter (ADC) output or the digital-to-analog converter (DAC) input using SW052.

• Select the system clock source from x’tal or SPDIF input recover clock using SW004, select the system clock using SW003 SCF1/0 for DIR1703 and using SW005 CLK1/0 for DIT4096, and select the system clock frequency for x’tal mode using JP001 setting.

• Set the interface format (24-bit I2S) using SW003 FMT1/0 for DIR1703 and using SW005 FMT1/0 for DIT4096.

• Set the channel status for DIT4096 using SW006 if required. (It is not required for PCM3052A evaluation.)

• Select the analog input/output configuration according to application interface, specifically, select the DUT PCM3052A V differential using JP110, the ADC input full scale from 2 Vrms or 1 Vrms using JP105/6, and the DAC output LPF band width from 20 kHz or 40 kHz using JP101-104.

Basic Connection and Operation

, ± AV

from 5 V or 4.5 V using JP109, the Mic input configuration of single ended or

, and GND on CN051–CN055. If external

SLEU079 – September 2006 Description 7

Submit Documentation Feedback

www.ti.com

Basic Connection and Operation

1.2.2 Configuration Controls

Table 1-1. CN057: 3.3-V Power Source Selection

CN057 DESCRIPTION

OFF 3.3 V must be supplied on CN056.

ON 3.3 V must be supplied by on board regulator, U051 (default).

Table 1-2. SW001: SPDIF Input Selection

SW001 DESCRIPTION

COAX Select coaxial connector as SPDIF input (default)

OPT Select optical connector as SPDIF input

Table 1-3. SW051: SPDIF Output Selection

SW051 DESCRIPTION

COAX Select coaxial connector as SPDIF output

OPT Select optical connector as SPDIF output (default)

Table 1-4. SW052: SPDIF Output Source Signal Selection

SW052 DESCRIPTION

REC Select DOUTS of PCM3052A, DAC input

DIT Select DIT4096 output, ADC output (default)

Table 1-5. SW004: DIR1703 Clock Source Selection

SW004 DESCRIPTION

X’tal SCKO (system clock out) is generated from crystal clock.

PLL SCKO is generated from SPDIF recovery clock.

AUTO Source clock of SCKO is automatically selected according to PLL lock state (default).

Table 1-6. SW003: DIR1703 System Clock Selection

SW003

SCF1 SCF0

OFF (L) OFF (L) 128 f OFF (L) ON (H) 256 fS(Default)

ON (H) OFF (L) 384 f ON (H) ON (H) 512 f

S S

DESCRIPTION

Table 1-7. SW005: DIT4096 Master Clock Selection

SW005

CLK1 CLK0

OFF (H) OFF (H) 512 f OFF (H) ON (L) 384 f

ON (L) OFF (H) 256 fS(default) ON (L) ON (L) Unused

S S

DESCRIPTION

Description 8 SLEU079 – September 2006

Submit Documentation Feedback

www.ti.com

Basic Connection and Operation

Table 1-8. JP001: DIR1703 Crystal Selection for Crystal Mode System Clock and Default Sampling

Frequency

JP001 DESCRIPTION

OPEN 6.144/12.288/18.432/24.576 MHz for 128 fS/256 fS/384 fS/512 fS, 48 kHz CSBIT 12.288/24.576/36.864/49.152 MHz for 128 fS/256 fS/384 fS/512 fS, 96 kHz (default) URBIT 11.2896/22.5792/33.8688/45.158 MHz for 128 fS/256 fS/384 fS/512 fS, 88.2 kHz

EMFLG 5.6448/11.2896/16.9344/22.5792 MHz for 128 fS/256 fS/384 fS/512 fS, 44.1 kHz

BFRAME 4.096/8.192/12.288/16.384 MHz for 128 fS/256 fS/384 fS/512 fS, 32 kHz

Table 1-9. SW003: DIR1703 Format Selection

SW003

FMT1 FMT0

OFF (L) OFF (L) 16 bits MSB first, right justified OFF (L) ON (H) 24 bits MSB first, right justified

ON (H) OFF (L) 24 bits MSB first, left justified ON (H) ON (H) 24 bits MSB first, I2S format (default)

DESCRIPTION

Table 1-10. SW005: DIT4096 Format Selection

SW005

FMT1 FMT0

OFF (H) OFF (H) 16-bit right justified OFF (H) ON (L) 24-bit right justified

ON (L) OFF (H) 24-bit I2S (default) ON (L) ON (L) 24-bit left justified

DESCRIPTION

Table 1-11. SW006: DIT4096 Channel Status Information Control

SW006 DESCRIPTION

CSS Channel status data mode input (default: on)

COPY-C Copy protect or channel status data input (default: on)

U User data input (default: on) V Validity data input (default: on)

L Generation status input (default: on)

/AUDIO Audio data valid control input (default: on)

/EMPH Pre-emphasis status input (default: off)

BLSM Block start mode control input (default: off)

BLS Block start I/O (default: off)

(1)

Control of these switches is not required for PCM3052A function and performance evaluation.

Table 1-12. SW053: Mode Control

SW053 DESCRIPTION

RESET Function control that is defined on RESET (default: off)

MDI Function control that is defined on MDI (default: off)

MC Function control that is defined on MC (default: off) ML Function control that is defined on ML (default: off)

(1)

SLEU079 – September 2006 Description 9

Submit Documentation Feedback

www.ti.com

Basic Connection and Operation

Table 1-13. JP051: DOUTS or MDO Setting for Mode Control

JP051 DESCRIPTION

1/4 Change SCL configuration to MC configuration (default: off) 2/4 Change SCA configuration to MD configuration (default: off) 3/4 Enable MDO (default: off) 4/4 Enable DOUTS (default: on)

Table 1-14. JP109: DUT (PCM3052A) V

JP109 DESCRIPTION

LEFT DUT V

RIFHT DUT V

is supplied from external 5 V (default).

is supplied from onboard 4.5-V regulator

Table 1-15. JP110: MIC Input Configuration

JP110 DESCRIPTION

LEFT Single-ended microphone input

RIFHT Differential microphone input (default)

Table 1-16. JP101-104: Lineout LPF Selection

JP101,102,103,104 DESCRIPTION

OFF 40-kHz BW

ON 20-kHz BW (default)

Table 1-17. JP105, JP106: ADC Input Level Selection

JP105,106 DESCRIPTION

1 Vrms 1.06-Vrms full-scale voltage on ADC inputs (default) 2 Vrms 2.12-Vrms full-scale voltage on ADC inputs

Supply Voltage Selection

Table 1-18. JP107: Bridge for PCM Audio Interface

JP107 DESCRIPTION

ON All straps must be mounted for interfacing onboard SPDIF receiver/transmitter.

OFF

Table 1-19. JP108: Bridge for Mode Control Interface

JP108 DESCRIPTION

ON All straps must be mounted for interfacing with PC via CN060.

OFF

Description 10 SLEU079 – September 2006

All straps must be removed and connecting external audio interface signals on JP107 (signal) – JP111 (GND) for interfacing with external equipment.

All straps must be removed and connecting external control interface signals on right-side of JP108 for interfacing with external equipment.

Submit Documentation Feedback

+ 23 hidden pages

Texas Instruments DEM-DAI3052A User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual