TEXAS INSTRUMENTS DDC118 Technical data
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DDC118
SBAS325A − JUNE 2004 − REVISED JUNE 2005
Octal Current Input 20-Bit
Analog-To-Digital Converter
FEATURES
D SINGLE-CHIP SOLUTION TO DIRECTLY
MEASURE EIGHT LOW-LEVEL CURRENTS
D HIGH PRECISION, TRUE INTEGRATING
FUNCTION
D INTEGRAL LINEARITY:
±0.01% of Reading ±0.5ppm of FSR
D VERY LOW NOISE: 5.2ppm of FSR
D LOW POWE R: 13.5mW/channel
D ADJUSTABLE DATA RATE: Up to 3.125kSPS
D PROGRAMMABLE FULL SCALE
D DAISY-CHAINABLE SERIAL INTERFACE
VREF DVDDAVDD
CLK
Control
Digital
CONV
RANGE0
RANGE1
RANGE2
TEST
CLK_4X
HISPD/LOPWR
RESET
FORMAT
DCLK
DCLK
DVALID
DOUT
DOUT
DIN
DIN
IN1
IN3
IN2
IN4
IN5
IN7
IN6
IN8
Dual
Switched
Integrator
Dual
Switched
Integrato r
Dual
Switched
Integrator
Dual
Switched
Integrator
Dual
Switched
Integrator
Dual
Switched
Integrato r
Dual
Switched
Integrator
Dual
Switched
Integrator
∆Σ
Modulator
∆Σ
Modulator
∆Σ
Modulator
∆Σ
Modulator
Digital
Filter
Digital
Filter
Digital
Filter
Digital
Filter
Input/Output
DGNDAGND
APPLICATIONS
D CT SCANNER DAS
D PHOTODIODE SENSORS
D INFRARED PYROMETER
D LIQUID/GAS CHROMATOGRAPHY
Protected b y U S Patent #5841310
DESCRIPTION
The DDC118 is a 20-bit octal channel, current-input
analog-to-digital (A/D) converter. It combines both
current-to-voltage and A/D conversion so that eight
low-level current output devices, such as photodiodes, can
be directly connected to its inputs and digitized.
For each of the eight inputs, the DDC118 provides a
dual-switched integrator front-end. This design allows for
continuous current integration: while one integrator is
being digitized by the onboard A/D converter, the other is
integrating the input current. Adjustable full-scale ranges
from 12pC to 350pC and adjustable integration times from
50µs to 1s allow currents from fAs to µAs to be measured
with outstanding precision. Low-level linearity is ±0.5ppm
of the full-scale range and noise is 5.2ppm of the full-scale
range.
Two modes of operation are provided. In Low-Power
mode, total power dissipation is only 13.5mW per channel
with a maximum data rate of 2.5kSPS. High-Speed mode
supports data rates up to 3.125kSPS with a corresponding
dissipation of 18mW per channel.
The DDC118 has a serial interface designed for
daisy-chaining in multi-device systems. Simply connect
the output of one device to the input of the next to create
the chain. Common clocking feeds all the devices in the
chain so that the digital overhead in a multi-DDC118
system is minimal.
The DDC118 is a single-supply device using a +5V analog
supply and supporting a +2.7V to +5.25V digital supply.
Operating over the industrial temperature range of −40°C
to 85°C, the DDC118 is offered in a QFN-48 package.
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
! !
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Copyright 2002−2005, Texas Instruments Incorporated
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SBAS325A − JUNE 2004 − REVISED JUNE 2005
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ABSOLUTE MAXIMUM RATINGS
Analog Input Current 750µA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AVDD to DVDD −0.3V to +6V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AVDD to AGND −0.3V to +6V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DVDD to DGND −0.3V to +6V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AGND to DGND ±0.2V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VREF Input to AGND 2.0V to AVDD + 0.3V. . . . . . . . . . . . . . . . . .
Analog Input to AGND −0.3V to +0.7V. . . . . . . . . . . . . . . . . . . . . . .
Digital Input Voltage to DGND −0.3V to DVDD + 0.3V. . . . . . . . . . .
Digital Output Voltage to DGND −0.3V to AVDD + 0.3V. . . . . . . . .
Operating Temperature −40°C to +85°C. . . . . . . . . . . . . . . . . . . . . .
Storage Temperature −60°C to +150°C. . . . . . . . . . . . . . . . . . . . . . .
Junction Temperature (TJ) +150°C. . . . . . . . . . . . . . . . . . . . . . . . . . .
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only , an d
functional operation of the device at these or any other conditions
beyond those specified is not implied.
(1)
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible t o damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION
For package and ordering information, see the Package
Option Addendum located at the end of this data sheet.
2
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Integration Time, T
Integral Linearity Error
(6)
Resolution
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SBAS325A − JUNE 2004 − REVISED JUNE 2005
ELECTRICAL CHARACTERISTICS
At TA = +25°C, AVDD = +5V, DVDD = 3V, VREF = +4.096V, Range 5 (250pC), and continuous mode operation, unless otherwise noted.
Low-Power Mode: T
PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
ANALOG INPUT RANGE
Range 0 10.2 12 13.8 ∗
Range 1 47.5 50 52.5 ∗ ∗ ∗ pC
Range 2 95 100 105 ∗ ∗ ∗ pC
Range 3 142.5 150 157.5 ∗ ∗ ∗ pC
Range 4 190 200 210 ∗ ∗ ∗ pC
Range 5 237.5 250 262.5 ∗ ∗ ∗ pC
Range 6 285 300 315 ∗ ∗ ∗ pC
Range 7 332.5 350 367.5 ∗ ∗ ∗ pC
Negative Full-Scale Range −0.4% of Positive Full-Scale Range ∗ pC
Input Current
DYNAMIC CHARACTERISTICS
Data Rate 2.5 3.125 kSPS
System Clock Input (CLK)
Data Clock (DCLK) 16 ∗ MHz
ACCURACY
Noise, Low-Level Input
Resolution FORMAT = 1 20 ∗ Bits
Input Bias Current 0.1 10 ∗ ∗ pA
Range Error Match
Range Sensitivity to VREF V
Offset Error Range 5 (250pC) ±400 ±1000 ∗ ∗ ppm of FSR
Offset Error Match
DC Bias Voltage
Power-Supply Rejection Ratio at dc ±25 ±200 ∗ ∗ ppm of FSR/V
Internal Test Signal 11 ∗ pC
Internal Test Accuracy ±10 ∗ %
PERFORMANCE OVER TEMPERATURE
Offset Drift ±0.5 ±3
Offset Drift Stability ±0.2 ±1
DC Bias Voltage Drift
Input Bias Current Drift TA = +25°C to +45°C 0.01 1
Range Drift
REFERENCE
Voltage 4.000 4.096 4.200 ∗ ∗ ∗ V
Input Current
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(2)
CLK_4X = 0 4 4.8 MHz
CLK_4X = 1 16 19.2 MHz
(9)
(10)
(11)
∗ indicates that specification is the same as Low-Power Mode.
Exceeding maximum input current specification may damage device.
Input is less than 1% of full scale.
C
FSR is Full-Scale Range.
A best-fit line is used in measuring nonlinearity.
Matching between side A and side B of the same input.
Ensured by design, not production tested.
Voltage produced by the DDC118 at its input which is applied to the sensor.
Range drift does not include external reference drift.
Input reference current decreases with increasing T
Data format is Straight Binary with a small offset. The number of bits in the output word is controlled by the FORMAT pin (see text).
is the capacitance seen at the DDC118 inputs from wiring, photodiode, etc.
SENSOR
= 400µs and CLK = 4MHz; High-Speed Mode: T
INT
INT
(3)
(7)
(7)
(9)
Continuous Mode 400 1,000,000 320 ∗ µS
Non-continuous Mode, Range 1 to 7 50 ∗ µS
(4)
C
= 50pF, Range 5 (250pC) 5.2 6.5 5.5 7
SENSOR
FORMAT = 0 16 ∗ Bits
All Ranges 0.1 0.5 ∗ ∗ % of FSR
= 4.096 ± 0.1V 1:1 ∗
REF
Low-Level Input (< 1% FSR) ±0.05 ±2 ∗ ∗ mV
Average Value 150 190 µA
(see the Voltage Reference section, page 11).
INT
= 320µs and CLK = 4.8MHz.
INT
Low-Power Mode High-Speed Mode
(1)
750 ∗ µA
±0.01% Reading ± 0.5ppm FSR, typ ∗
±0.025% Reading ± 1.0ppm FSR, max ∗
±100 ∗ ppm of FSR
(8)
(8)
3 ∗ µV/°C
25 ∗ ppm/°C
(8)
∗ ∗ pC
ppm of
(5)
FSR
∗ ∗
∗ ∗
ppm of
FSR/°C
ppm of FSR/
minute
∗ ∗ pA/°C
, rms
3
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SBAS325A − JUNE 2004 − REVISED JUNE 2005
ELECTRICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = +5V, DVDD = 3V, VREF = +4.096V, Range 5 (250pC), and continuous mode operation, unless otherwise noted.
Low-Power Mode: T
PARAMETER UNITSMAXTYPMINMAXTYPMINTEST CONDITIONS
DIGITAL INPUT/OUTPUT
Logic Levels
V
IH
V
IL
V
OH
V
OL
Input Current (IIN) 0 < VIN < DVDD ±10 ∗ µA
Data Format
POWER-SUPPLY REQUIREMENTS
Analog Power-Supply Voltage (AVDD) 4.75 5.25 ∗ ∗ V
Digital Power-Supply Voltage (DVDD) 2.7 5.25 ∗ ∗ V
Supply Current
Total Power Dissipation DVDD = +3V 108 150 144 200 mW
Total Power Dissipation per Channel DVDD = +3V 13.5 18.75 18 25 mW
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(12)
Total Analog Current 21 28 mA
Total Digital Current DVDD = +3V 1 1.34 mA
∗ indicates that specification is the same as Low-Power Mode.
Exceeding maximum input current specification may damage device.
Input is less than 1% of full scale.
C
FSR is Full-Scale Range.
A best-fit line is used in measuring nonlinearity.
Matching between side A and side B of the same input.
Ensured by design, not production tested.
Voltage produced by the DDC118 at its input which is applied to the sensor.
Range drift does not include external reference drift.
Input reference current decreases with increasing T
Data format is Straight Binary with a small offset. The number of bits in the output word is controlled by the FORMAT pin (see text).
is the capacitance seen at the DDC118 inputs from wiring, photodiode, etc.
SENSOR
= 400µs and CLK = 4MHz; High-Speed Mode: T
INT
IOH = −500µA DVDD − 0.4 V
IOL = 500µA 0.4 ∗ V
(see the Voltage Reference section, page 11).
INT
= 320µs and CLK = 4.8MHz.
INT
High-Speed ModeLow-Power Mode
0.8DVDD DVDD + 0.1 ∗ ∗ V
− 0.1 0.2DVDD ∗ ∗ V
Straight Binary ∗
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SBAS325A − JUNE 2004 − REVISED JUNE 2005
PIN CONFIGURATION
Top View QFN
DGND
DGND
CONV
DGND
DVA LID
DGND
CLK
DGND
DCLK
DCLK
DGND
DVDD
48 47 46 45 44 43 42
41 40 39 38
DOUT
DOUT
CLK_4X
FOR MA T
HISPD/LOPWR
RANG E0
RANG E1
RANG E2
AGND
VREF
AGND
AGND
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 233724
AIN8
AIN4
AGND
AIN7
DDC118
AIN3
AGND
AIN6
AGND
AIN2
AIN5
36
DIN
35
DIN
34
NC
33
NC
32
RESET
31
TEST
30
DGND
29
DGND
28
AGND
27
AVDD
26
AGND
25
AGND
AIN1
AGND
PIN DESCRIPTIONS
PIN NUMBER FUNCTION DESCRIPTION
DOUT 1 Digital Output Serial Data Output
DOUT 2 Digital Output Serial Data Output: Complementary Signal (optional, see text on page 13)
CLK_4X 3 Digital Input Master Clock Divider Control: 0 = divide by 1, 1 = divide by 4
FORMAT 4 Digital Input Digital Output Word Format: 0 = 16 Bits, 1 = 20 Bits
HISPD/LOPWR 5 Digital Input Mode Control: 0 = Low-Power, 1 = High-Speed
RANGE0 6 Digital Input Range Control 0 (least significant bit)
RANGE1 7 Digital Input Range Control 1
RANGE2 8 Digital Input Range Control 2 (most significant bit)
AGND 9, 11-13, 18, 19, 24-26, 28 Analog Analog Ground
VREF 10 Analog Input External Voltage Reference Input, 4.096V Nominal
AIN8 14 Analog Input Analog Input 8
AIN7 16 Analog Input Analog Input 7
AIN6 20 Analog Input Analog Input 6
AIN5 22 Analog Input Analog Input 5
AIN4 15 Analog Input Analog Input 4
AIN3 17 Analog Input Analog Input 3
AIN2 21 Analog Input Analog Input 2
AIN1 23 Analog Input Analog Input 1
AVDD 27 Analog Analog Power Supply, 5V Nominal
DGND 29, 30, 38, 41, 43, 45, 47, 48 Digital Digital Ground
TEST 31 Digital Input Test Mode Control
RESET 32 Digital Input Resets the Digital Circuitry, Active Low
NC 33, 34 — No connection. These pins must be left unconnected.
DIN 35 Digital Input Serial Data Input: Complementary Signal (optional, see text on page 13)
DIN 36 Digital Input Serial Data Input
DVDD 37 Digital Digital Power Supply, 3V Nominal
DCLK 39 Digital Input Serial Data Clock Input: Complementary Signal (optional, see text on page 13)
DCLK 40 Digital Input Serial Data Clock Input
CLK 42 Digital Input Master Clock Input
DVALID 44 Digital Output Data Valid Output, Active Low
CONV 46 Digital Input Conversion Control Input: 0 = Integrate on Side B, 1 = Integrate on Side A
5
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NOISE vs C
Range Drift (ppm)
SBAS325A − JUNE 2004 − REVISED JUNE 2005
TYPICAL CHARACTERISTICS
At TA = +25°C, characterization done with Range 5 (250pC), AVDD = +5V, DVDD = 3V, VREF = +4.096V, and Low-Power Mode: T
unless otherwise noted.
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= 400µs and CLK = 4MHz,
INT
45
NOISE vs C
40
35
30
25
20
15
10
Noise(ppmofFSR,rms)
5
0
100 4000 500300200
C
SENSOR
NOISE vs T
6
5
4
C
SENSOR
3
2
Noise (ppm of FSR, rms)
1
Range 5
0
1 10000.1 10010
C
SENSOR
= 50pF
T
=0pF
(ms)
INT
SENSOR
(pF)
INT
Range 1
Range 2
Range 7
SENSOR
Noise (ppmof FSR, rms)
C
SENSOR
(pF)
24
50
75
100
150
200
300
500
Range
Range
Range
5.2
6.7
8.2
8.9
10.0
11.9
13.5
16.3
22.4
Range
2
3
4.4
5.5
6.5
7.2
8.0
9.2
10.2
12.5
16.6
0
1
0
23.6
7.3
30.8
10.4
36.3
12.3
41.3
14.4
46.1
16.0
57.0
18.8
68.1
21.7
89.3
27.7
134.0
38.9
Range
4
4.2
4.9
5.6
6.0
6.7
7.8
8.6
10.6
13.5
Range
5
4.0
4.5
5.1
5.4
5.9
6.8
7.6
9.0
11.7
Range
6
3.8
4.3
4.8
5.1
5.4
6.1
6.8
8.1
10.4
Range
7
3.7
4.1
4.4
4.7
5.0
5.7
6.4
7.4
9.5
NOISE vs INPUT LEVEL
8
7
6
5
4
C
SENSOR
= 50pF
C
SENSOR
= 0pF
3
2
Noise (ppm of FSR, rms)
1
Range 5
0
20 3010 800 10060 70 9040 50
Input Level (% of Full−Scale)
14
C
=50pF
SENSOR
12
10
Range 2
Range 1
Range 3
8
2000
1500
1000
500
All Ranges
NOISE vs TEMPERATURE
RANGE DRIFT vs TEMPERATURE
0
6
4
Noise (ppm of FSR, rms)
2
Range 7
0
−
40
−
15 10 35 60 85
Temperature (_C)
−
−
−
−
500
1000
1500
2000
−
40
−
15 10 35 60 85
Temperature (_C)
6
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IBvs TEMPERATURE
ANALOG SUPPLY CURRENTvs TEMPERATURE
POWER CONSUMPTION HISTOGRAM
OFFSET DRIFT vs TEMPERATURE
SBAS325A − JUNE 2004 − REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, characterization done with Range 5 (250pC), AVDD = +5V, DVDD = 3V, VREF = +4.096V, and Low-Power Mode: T
unless otherwise noted.
""#
= 400µs and CLK = 4MHz,
INT
10
All Ranges
1
(pA)
B
I
0.1
0.01
25 35 45 55 65 75 85
Temperature (_C)
25
Low−Power Mode
20
15
10
Current (mA)
100
50
0
−
50
Offset Drift (ppm of FSR)
−
100
25 35 45 55 65 75 85
Temperature (_C)
2.5
2.0
1.5
1.0
Current (mA)
DIGITAL SUPPLY CURRENT vsTEMPERATURE
Low−Power Mode
DVDD= 5V
DVDD = 3V
5
0
−
40
40
35
30
25
20
15
Occurences(%)
10
5
0
−
15 10 35 60 85
Data collected
from multiple lots.
12.00
12.25
12.50
12.75
Temperature (_C)
13.00
13.25
13.50
13.75
14.00
Power per Channel (mW)
Low−Power Mode
14.25
14.50
14.75
15.00
15.25
15.50
15.75
16.00
Occurences
0.5
0
1200
1000
800
600
400
200
−
40
0
−
1.0
−
15 10 35 60 85
Temperature (_C)
OFFSET DRIFT HISTOGRAM AT ROOM TEMPERATURE
Repeated measurement
of offset drift over a
one minute interval.
−
0.6
−
0.2 0.2 0.6 1.0
Offset Drift (ppm of FSR/minute)
Range 5
7
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SBAS325A − JUNE 2004 − REVISED JUNE 2005
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THEORY OF OPERATION
The block diagram of the DDC118 is shown in Figure 1.
The device contains eight identical input channels that
perform the function of current-to-voltage integration
followed by a multiplexed A/D conversion. Each input has
two integrators so that the current-to-voltage integration
can be continuous in time. The output of the sixteen
integrators are switched to four delta-sigma (∆Σ)
converters via four four-input multiplexers. With the
VREF
Modulator
Modulator
IN1
IN3
IN2
AVDD
Switched
Integrator
Switched
Integrator
Switched
Integrator
Dual
Dual
Dual
DDC118 in the continuous integration mode, the output of
the integrators from one side of the inputs will be digitized
while the other eight integrators are in the integration
mode, as illustrated in the timing diagram in Figure 2. This
integration and A/D conversion process is controlled by
the system clock, CLK. The results from side A and side
B of each signal input are stored in a serial output shift
register. The DVALID
output goes low when the shift
register contains valid data.
DVDD
CLK
CONV
RANGE0
∆Σ
∆Σ
Digital
Filter
Digital
Filter
Control
RANGE1
RANGE2
TEST
CLK_4X
HISPD/LOPWR
RESET
FORMAT
IN4
IN5
IN7
IN6
IN8
Dual
Switched
Integrator
Dual
Switched
Integrator
Dual
Switched
Integrator
Dual
Switched
Integrator
Dual
Switched
Integrator
AGND
∆Σ
Modulator
∆Σ
Modulator
Digital
Filter
Digital
Filter
DCLK
DCLK
DVALID
Digital
Input/Output
DOUT
DOUT
DIN
DIN
DGND
Figure 1. DDC118 Block Diagram
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SBAS325A − JUNE 2004 − REVISED JUNE 2005
The digital interface of the DDC118 provides the digital
results via a synchronous serial interface consisting of
differential data clocks (DCLK and DCLK), a valid data pin
(DVALID
DOUT
DIN
), differential serial data output pins (DOUT and
), and differential serial data input pins (DIN and
). The DDC118 contains only four A/D converters, so
the conversion process is interleaved (see Figure 2). The
integration and conversion process is fundamentally
independent of the data retrieval process. Consequently,
the CLK frequency and DCLK frequencies need not be the
same. DIN and DIN
are only used when multiple
converters are cascaded and should be tied to DGND and
DVDD otherwise.
DEVICE OPERATION
Basic Integration Cycle
The topology of the front end of the DDC118 is an analog
integrator as shown in Figure 3. In this diagram, only Input
IN1 is shown. This representation of the input stage
consists of an operational amplifier, a selectable feedback
capacitor network (C
IN1, IN2, IN5, and IN6,
IN1, IN2, IN5, and IN6,
IN3, IN4, IN7, and IN8,
IN3, IN4, IN7, and IN8,
Conversion in Progress
Integrator A
Integrator B
Integrator A
Integrator B
DVALID
), and several switches that
F
Integrate
Integrate
IN1B
IN2B
IN5B
IN6B
IN3B
IN4B
IN7B
IN8B
IN1A
IN2A
IN5A
IN6A
implement the integration cycle. The timing relationships
of all of the switches shown in Figure 3 are illustrated in
Figure 4. Figure 4 is used to conceptualize the operation
of the integrator input stage of the DDC118 and should not
be used as an exact timing tool for design. See Figure 5 for
the block diagrams of the reset, integrate, wait and convert
states of the integrator section of the DDC118. This
internal switching network is controlled externally with the
convert pin (CONV), range selection pins
(RANGE0-RANGE2), and the system clock (CLK). For the
best noise performance, CONV must be synchronized
with the rising edge of CLK. It is recommended that CONV
toggle within ±10ns of the rising edge of CLK.
The noninverting inputs of the integrators are connected to
ground. Consequently, the DDC118 analog ground should
be as clean as possible. The range switches, along with
the internal and external capacitors (C
), are shown in
F
parallel between the inverting input and output of the
operational amplifier. At the beginning of a conversion, the
switches S
A/D
, S
INTA
, S
INTB
, S
REF1
, S
REF2
are set (see Figure 4).
Integrate
IN1A
IN2A
IN5A
IN6A
Integrate
Integrate
IN3A
IN4A
IN7A
IN8A
Integrate
Integrate
IN3A
IN4A
IN7A
IN8A
IN1B
IN2B
IN5B
IN6B
Integrate
IN3B
IN4B
IN7B
IN8B
, and S
RESET
Figure 2. Basic Integration and Conversion Timing for the DDC118 (continuous mode)
S
Photodiode
Input
Current
IN1
ESD
Protection
Diodes
REF1
3pF
50pF
25pF
12.5pF
S
INTA
S
RESET
S
INTB
Integrator A
IntegratorB (same asA)
S
S
REF2
A/D1A
VREF
RANGE2
RANGE1
RANGE0
To Converter
Figure 3. Basic Integration Configuration for Input 1, shown with a 250pC (CF = 62.5pF) Input Range
9
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