Texas Instruments DAC8742H User Manual
User's Guide
SLAU700A–June 2017–Revised November 2017
DAC8742H Evaluation Module
This user's guide describes the characteristics, operation, and use of the DAC8742H evaluation board
(EVM). This user’s guide also discusses the proper setup and configuration of both software and
hardware, and reviews various aspects of program operation. A complete circuit description, schematic
diagram, and bill of materials are also included in this document.
Contents
1 Overview...................................................................................................................... 3
1.1 DAC8742HEVM Kit Contents ..................................................................................... 3
1.2 Related Documentation From Texas Instruments.............................................................. 3
2 DAC8742HEVM Hardware Setup ......................................................................................... 4
2.1 DAC8742H Hardware Theory of Operation ..................................................................... 4
2.2 USB2ANY Signal Definition ....................................................................................... 5
3 DAC8742HEVM Software Setup .......................................................................................... 6
3.1 Operating Systems for DAC8742HEVM Software.............................................................. 6
3.2 DAC8742H Software Installation ................................................................................. 6
4 DAC8742HEVM Hardware Overview ..................................................................................... 7
4.1 Electrostatic Discharge Warning.................................................................................. 7
4.2 Connecting the Hardware.......................................................................................... 7
4.3 DAC8742HEVM Power Configurations .......................................................................... 7
4.4 DAC8742H Reference Connection............................................................................... 8
4.5 Digital Inputs......................................................................................................... 8
4.6 Clock Configuration................................................................................................. 9
4.7 HART/PAFF Shunt Selection .................................................................................... 10
5 DAC8742HEVM Software Overview .................................................................................... 11
5.1 Starting the DAC8742HEVM Software ......................................................................... 11
5.2 DAC8742HEVM Software Features ............................................................................ 12
6 DAC8742HEVM Documentation ......................................................................................... 16
6.1 DAC8742HEVM Board Schematic.............................................................................. 17
6.2 DAC8742HEVM PCB Components Layout.................................................................... 18
6.3 DAC8742H Test Board Bill of Materials........................................................................ 19
1 DAC8742HEVM Hardware Setup ......................................................................................... 4
2 DAC8742H Test Board Block Diagram................................................................................... 4
3 Launching Software Setup ................................................................................................. 6
4 DAC8742HEVM GUI Location............................................................................................ 11
5 DAC8742HEVM GUI – Power On ....................................................................................... 11
6 DAC8742H EVM Software Page Selection............................................................................. 12
7 Low Level Configuration Page............................................................................................ 13
8 Low Level Configuration Page Available Options...................................................................... 13
9 High Level Configuration Page........................................................................................... 14
10 MODE Section.............................................................................................................. 15
11 DAC8742HEVM Digital Input Selection ................................................................................. 15
12 HART/PAFF Write/Read Control and Indicator Section............................................................... 16
13 DAC8742HEVM Board Schematic....................................................................................... 17
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List of Figures
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14 DAC8742HEVM PCB Components Layout............................................................................. 18
1 Contents of DAC8742H Kit................................................................................................. 3
2 Related Documentation..................................................................................................... 3
3 J2 USB2ANY and Digital Signal Definition............................................................................... 5
4 Default Jumper Settings .................................................................................................... 7
5 DAC8742HEVM Power Supply Configuration ........................................................................... 7
6 DAC8742HEVM Reference Connection .................................................................................. 8
7 Digital Signal Definition ..................................................................................................... 8
8 J6 Digital Signal Definition.................................................................................................. 8
9 Clock Configuration.......................................................................................................... 9
10 XTAL1 and XTAL2 Configuration Settings ............................................................................... 9
11 Internal Mode Shunt Selection ........................................................................................... 10
12 External Filter Mode With Internal REF Shunt Selection ............................................................. 10
13 DAC8742H Test Board Bill of Materials................................................................................. 19
Trademarks
Microsoft, Windows are registered trademarks of Microsoft Corporation.
LabVIEW is a trademark of National Instruments Corporation.
All other trademarks are the property of their respective owners.
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List of Tables
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DAC8742H Evaluation Module
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1 Overview
This EVM features the DAC8742H device, which is a Highway Addressable Remote Transducer (HART),
FOUNDATION Fieldbus (FF), and Profibus process automation (PA) compliant low-power frequency-shift
keying (FSK) modem designed for industrial process control and industrial automation applications. The
device includes an integrated receive band-pass filter, flexible clocking options and can operate from a
1.8- to 5.5-V range. The wide temperature range, –55°C to 125°C, and low quiescent current make this
device an ideal candidate for smart transmitters, programmable-logic controller (PLC) I/O modules, and
other industrial process-control applications.
1.1 DAC8742HEVM Kit Contents
Table 1 details the contents of the kit. Contact the TI Product Information Center or visit the Texas
Instruments E2E Community (http://E2E.ti.com) if any component is missing. TI highly recommends that
the user verify the latest versions of the related software at the TI website, www.ti.com.
Table 1. Contents of DAC8742H Kit
Item Quantity
DAC8742HEVM PCB evaluation board 1
USB2ANY 1
1.2 Related Documentation From Texas Instruments
The following document provides information regarding Texas Instruments integrated circuits used in the
assembly of the DAC8742HEVM. This user's guide is available from the TI web site under literature
number SLAU700. Any letter appended to the literature number corresponds to the document revision that
is current at the time of the writing of this document. Newer revisions may be available from the TI web
site at http://www.ti.com/, or call the Texas Instruments Literature Response Center at (800) 477-8924 or
the Product Information Center at (972) 644-5580. When ordering, identify the document by both title and
literature number.
Overview
Table 2. Related Documentation
Document Literature Number
DAC8742H data sheet SBAS856
USB2ANY SBOU136
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DAC8742H Evaluation Module
3
(Optional)
External/Onboard REF
USB2ANY
Connection
(HART/PAFF)
TX/RX
Optional External Power
(AVDD/IOVDD)
DAC8742H
SPI
Power
Copyright © 2017, Texas Instruments Incorporated
DAC8742HEVM
USB Bus
from
Computer
(Optional) External
Power Source
LaunchPad
Connector
USB2ANY
Personal
Computer
(PC)
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DAC8742HEVM Hardware Setup
2 DAC8742HEVM Hardware Setup
This section provides the overall system setup for the EVM. A PC runs software that communicates with
the USB2ANY platform, which generates the optional IOVDD or AVDD power and digital signals used to
communicate with the EVM board. Test point connections are included on the EVM board for external
power supplies. Figure 1 displays the DAC8742HEVM system setup.
Figure 1. DAC8742HEVM Hardware Setup
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2.1 DAC8742H Hardware Theory of Operation
A block diagram of the DAC8742HEVM PCB board is displayed in Figure 2. The EVM board provides an
interface to optional external supplies, an external reference, and a USB2ANY connection for serial
peripheral interface (SPI) and universal asynchronous receiver and transmitter (UART) communication.
Figure 2. DAC8742H Test Board Block Diagram
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2.2 USB2ANY Signal Definition
The DAC8742HEVM provides a hardware connector (J2) that connects to the USB2ANY interface board,
which can supply IOVDD and AVDD power and is responsible for providing the SPI or UART commands
sent from the PC GUI software. Optionally, provide the AVDD and IOVDD supply through an external
supply, and access all digital communication lines through their respective digital test points. This
information is provided in Table 3.
Table 3. J2 USB2ANY and Digital Signal Definition
Pin On J2 Signal Description
2 COM_SELECT Select between SPI or UART
4, 6, 8, 16, 27, 28 GND CS | general purpose I/O
12 CS_GPIO6 SPI, CS, or general purpose I/O
13 RXD_MISO UART RXD or SPI MISO
14 TXD_MOSI UART TXD or SPI MOSI
15 USB 3.3V 3.3-V USB power
18 SCLK_GPIO2 SPI SCLK or general purpose I/O
25 REF_EN DAC8742H reference enable
26 IF_SEL DAC8742H IF_SEL pin
29 BPF_EN General purpose I/O
30 RST DAC8742H rest Line
DAC8742HEVM Hardware Setup
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DAC8742HEVM Software Setup
3 DAC8742HEVM Software Setup
This section provides the procedures for software installation.
3.1 Operating Systems for DAC8742HEVM Software
The EVM software has been tested on the Microsoft®Windows®XP and Windows 7 operating systems
with the United States and European regional settings. The software should also be compatible with other
Windows operating systems.
3.2 DAC8742H Software Installation
The software is available through the EVM product folder on the TI website. Once the software is
downloaded onto the PC, navigate to the DAC8742HEVM folder, and run the setup.exe file, as shown in
Figure 3. When the software is launched, an installation dialog will open, and prompt the user to select an
installation directory. If left unchanged, the software location defaults to C:\Program Files (x86)
\DAC8742HEVM.
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Figure 3. Launching Software Setup
The software installation will automatically copy the required LabVIEW™ software files and drivers to the
local machine.
NOTE: Verify that the USB2ANY is not connected before the software installation, as this may affect
file or driver installation.
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4 DAC8742HEVM Hardware Overview
The subsequent sections provide detailed information on the EVM hardware, and jumper configuration
settings. Table 4 displays the default configurations of all jumper connections on the DAC8742HEVM.
Connect the USB extender cable from the USB2ANY to the PC.
Table 4. Default Jumper Settings
Jumper Position Description
JP1 Shunt on 1 – 2 HART: Connects to 3.6864-MHz external crystal
JP2 Shunt on 1 – 2 HART: Connects to 3.6864-MHz external crystal
JP4 Shunt on 2 – 3 Connects TS5N412PW device
JP5 Populate HART: Connects IOVDD to AVDD for single supply
JP6 Shunt on 1 – 2 Connects IOVDD to USB2ANY 3.3-V supply
JP8 Populate HART: Connects to 0.022-µF load capacitor
JP9 Shunt on 2 – 3 HART: Connects to MOD_IN
JP10 Shunt on 2 – 3 HART: Connects to 2200 pF
JP11 Shunt on 1 – 2 HART: Connects to 2200 pF
JP14 Shunt on 2 – 3 CLK_CFG1 set to GND
JP16 Shunt on 5 – 6 HART: Connects to 680 pF
JP17 Populate CLK_CFG0 set to GND
JP20 Shunt on 1 – 2 /XEN set to GND
DAC8742HEVM Hardware Overview
operation
4.1 Electrostatic Discharge Warning
Many of the components on the DAC8742HEVM are susceptible to damage by electrostatic discharge
(ESD). Customers are advised to observe proper ESD handling precautions when unpacking and handling
the board, including the use of a grounded wrist strap at an approved ESD workstation.
4.2 Connecting the Hardware
To connect the USB2ANY to the EVM board, align and firmly connect the keyed ribbon connector to the
J2 connector. Verify the connection is snug, as loose connections may cause intermittent operation.
4.3 DAC8742HEVM Power Configurations
The DAC8742HEVM provides electrical connections to the device supply pins. The connectors and
optional configurations are shown in the Table 5.
Table 5. DAC8742HEVM Power Supply Configuration
Connector Connection Type Description
J3 AVDD terminal block Connects external supply to AVDD net
J4 IOVDD terminal block Connects external supply to IOVDD net
JP5 Shunt connection Connects AVDD to IOVDD
JP6
USB2ANY can supply IOVDD and AVDD by populating the JP6 shunt to position (1 – 2) and connecting
shunt J5.
Shunt (1 – 2) Connects USB2ANY 3.3 V to IOVDD
Shunt (2 – 3) Connects IOVDD net to J4 terminal block
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DAC8742HEVM Hardware Overview
4.4 DAC8742H Reference Connection
The DAC8742HEVM connects to an optional external reference through the J5 terminal block, or it can be
supplied by the internal reference of the DAC8742H device (see Table 6).
Table 6. DAC8742HEVM Reference Connection
Connector Connection Type Description
J5 REF Terminal Block Connects external reference to REF net
JP7 Populate Connects external reference to REF net
4.5 Digital Inputs
The digital communication lines of the DAC8742H device can be accessed through the USB2ANY header
connection (J2) or the J6 header block, which are listed in Table 7 and Table 8, along with the digital input
signals of the DAC8742H device.
Table 7. Digital Signal Definition
Name Connector Description
JP13 IF_SEL
JP15, JP17 CLK_CFG0
JP14 CLK_CFG1
JP20 /XEN
JP19 REF_EN
JP18 BPF_EN
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(1 – 2) IOVDD: SPI mode
(2 – 3) GND: UART mode
(JP15 – closed, JP17 – open): CLK_CFG0 set to IOVDD
(JP15 – open, JP17 – closed): CLK_CFG0 set to GND
(JP15 – closed, JP17 – closed): CLK_CFG0 set to (0.5) IOVDD
(1 – 2) CLK_CFG1 set to IOVDD
(2 – 3) CLK_CFG1 set to GND
(1 – 2) GND: external crystal
(2 – 3) IOVDD: external oscillator or internal oscillator required
(1 – 2) GND: external reference
(2 – 3) IOVDD: internal reference
(1 – 2) GND: external bandpass required
(2 – 3) IOVDD: internal bandpass filter
Name Connector
J6-1 UART_OUT/SDO
J6-2 DUPLEX/SDI
J6-3 /UART_RTS/SCLK
J6-4 UART_IN/CS
J6-5 CD/IRQ
J6-6 /RST
J6-7 IOVDD
J6-8 GND
NOTE: Control the REF_EN, BPF_EN, and IF_SEL lines through the GUI.
The DAC8742H data sheet lists acceptable clock configurations, and they are also listed in Table 9 for
reference.
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DAC8742H Evaluation Module
Table 8. J6 Digital Signal Definition
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4.6 Clock Configuration
The DAC8742H device supports a variety of clocking options in order to provide system flexibility and
reduce overall current consumption in HART applications. The clocking options include: an internal
oscillator (HART mode only), an external crystal oscillator, or an external CMOS clock.
Configure clock selection via the XEN, CLK_CFG1, and CLK_CFG0 pins (see Table 9).
XEN CLK_CFG1 CLK_CFG0 CLKO Description Mode
1 0 0 No output 3.6864-MHz CMOS clock connected at XTAL1
1 0 1 No output 1.2288-MHz CMOS clock connected at XTAL1
1 1 0 No output Internal oscillator enabled
1 1 1 1.2288-MHz output Internal oscillator enabled, CLKO enabled
0 0 0 No output Crystal oscillator enabled
0 0 1 3.6864-MHz output 3.6864-MHz crystal oscillator, CLKO enabled
0 1 0 1.8432-MHz output 1.8432-MHz crystal oscillator, CLKO enabled
0 1 1 1.2288-MHz output 1.2288-MHz crystal oscillator, CLKO enabled
1 0 0.5 × IOVDD No output 4-MHz CMOS clock connected at XTAL1
1 1 0.5 × IOVDD No output 2-MHz CMOS clock connected at XTAL1
0 0 0.5 × IOVDD No output 4-MHz crystal oscillator
0 1 0.5 × IOVDD 4-MHz output 4-MHz crystal oscillator, CLKO enabled
The XTAL1 and XTAL2 pins of the DAC8742H device are also configurable through the JP1, JP2, and J1
jumpers (see Table 10).
DAC8742HEVM Hardware Overview
Table 9. Clock Configuration
HART
FOUNDATION
Fieldbus and
PROFIBUS PA
Table 10. XTAL1 and XTAL2 Configuration Settings
Jumper Description
JP1
JP2
J1 Optional CMOS clock connection
(1 – 2) 3.686-MHz crystal
(2 – 3) 4-MHz crystal
(1 – 2) 3686-MHz crystal
(2 – 3) 4-MHz crystal
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