Texas Instruments DAC8555EVM User Manual

User's Guide

SLAU204 – December 2006

DAC8555EVM User's Guide

This user’s guide describes the characteristics, operation and use of the DAC8555
Evaluation Module (EVM). It covers all matters related to proper use and configuration
of this EVM along with the devices that it supports. The physical printed circuit board
(PCB) layout, schematic diagram and circuit descriptions are also included. For a more
detailed description of the DAC8555 , see the product data sheet available from the
Texas Instruments web site at http://www.ti.com. Additional support documents are
listed in the section of this guide entitled Related Documentation from Texas

Instruments. Throughout this document, the acronym EVM and the phrases evaluation
module and demonstration board are synonymous with the DAC8555EVM.

TMS320C5000, TMS320C6000 are trademarks of Texas Instruments.
LabVIEW is a trademark of National Instruments.

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Contents

1 Overview ............................................................................................. 3

2 PCB Design and Performance .................................................................... 6

3 EVM Operation .................................................................................... 16

4 Schematic .......................................................................................... 22

List of Figures

1 DAC8555EVM Functional Block Diagram ....................................................... 5

2 DAC8555EVM PCB—Top Silkscreen Image ................................................... 7

3 DAC8555EVM PCB—Layer 1 (Top Signal Layer) ............................................. 7

4 DAC8555EVM PCB—Layer 2 (Ground Plane) ................................................. 8

5 DAC8555EVM PCB—Layer 3 (Power Plane) .................................................. 8

6 DAC8555EVM PCB—Layer 4 (Bottom Signal Layer) ......................................... 9

7 DAC8555EVM PCB—Bottom Silkscreen Image ............................................... 9

8 DAC8555EVM—Drill Drawing ................................................................... 10

9 INL and DNL Characterization Graph of DAC A .............................................. 11

10 INL and DNL Characterization Graph of DAC B .............................................. 12

11 INL and DNL Characterization Graph of DAC C .............................................. 13

12 INL and DNL Characterization Graph of DAC D .............................................. 14

List of Tables

1 DAC8555EVM Parts List ......................................................................... 15

2 Factory Default Jumper Settings ................................................................ 16

3 DAC Output Channel Mapping .................................................................. 17

4 Unity Gain Output Jumper Settings ............................................................. 18

5 Output Gain of 2 Jumper Settings .............................................................. 18

6 Capacitive Load Drive Output Jumper Settings ............................................... 19

7 Jumper Settings and Functions ................................................................. 19

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1 Overview

This section gives a general overview of the DAC8555EVM and describes some of the factors that must
be considered when using this demonstration board.

1.1 Features

The DAC8555EVM is a simple evaluation module designed for a quick and easy way to evaluate the
functionality and performance of the high-resolution, quad-channel, serial input DAC8555 digital-to-analog
converter (DAC). This EVM features a serial interface to communicate with any host microprocessor or TI
DSP-based system.

1.2 Power Requirements

This subsection describes the power requirements for this device.

1.2.1 Supply Voltage

The DC power supply requirement for the digital section (V
the J5-1 terminal or via the J3-10 terminal (when plugged in with another EVM board or interface card)
and is referenced to ground through the J5-2 and J3-5 terminals. The DC power supply requirements for
the analog section of this EVM are: V
through J1-3 and J1-1 respectively, or through terminals J3-1 and J3-2. The +5V
terminals J5-3 or J3-3, and the +3.3V
are referenced to analog ground through terminals J1-2 and J3-6.

The analog power supply for the device under test, U1, can be powered by either +5V
selecting the proper position of jumper JMP7. This configuration allows the DAC8555 analog section to
operate from either supply power while the I/O and digital section are powered by +5V, V

The V
reference chip, U3 and the reference buffer, U4. The negative rail of the output op amp, U2, can be
selected between V
provide output signal conditioning or to boost capacitive load drive, or for other desired output mode
requirements.

) of this EVM is typically +5V connected to

DD

and V

CC

connects through terminal J3-8. All of the analog power supplies

A

supply source is primarily used to provide the positive rail of the external output op amp, U2, the

CC

and AGND via jumper JMP10. The external op amp is installed as an option to

SS

range from +15.75V to –15.75V (maximum), connecting

SS

connects through

A

or +3.3V

A

DD

Overview

by

A

.

CAUTION

To avoid potential damage to the EVM board, be sure that the correct cables
are connected to their respective terminals as labeled on the EVM board.
Stresses above the maximum listed voltage ratings may cause permanent
damage to the device.

1.2.2 Reference Voltage

The +5V precision voltage reference is provided to supply the external voltage reference for the DAC
through the REF02 (U3) via jumper JMP8, by shorting pins 1 and 2. The reference voltage goes through
an adjustable 100k Ω potentiometer, R15, in series with 20k Ω , R16, to allow the user to adjust the
reference voltage to its desired settings. The voltage reference is then buffered through U4A as seen by
the device under test. The test points TP2, TP3 and TP4 are also provided, as well as J4-18 and J4-20, in
order to allow the user to connect another external reference source if the onboard reference circuit is not
desired. The external voltage reference should not exceed +5V DC.

The REF02 precision reference is powered by V

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(+15V) through either terminal J1-3 or J3-1.

CC

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Overview

1.3 EVM Basic Functions

CAUTION

When applying an external voltage reference through TP2 or J4-20, make sure
that it does not exceed +5V maximum. External voltage references in excess of
+5V can permanently damage the DAC8555 being tested (U1).

The DAC8555EVM is designed to provide a demonstration platform for testing certain operational
characteristics of the DAC8555 digital-to-analog converter. Functional evaluation of the DAC8555 can be
accomplished with the use of any microprocessor, TI DSP or some sort of waveform generator.

Headers J2A (top side) and J2B (bottom side) are pass-through connectors provided to interface a host
processor or waveform generator with the DAC8555EVM using a custom-built cable. These connectors
enable the control signals and data to pass between the host and the device.

A mating adapter interface card (5-6k adapter interface) is also available to fit with TI’s TMS320C5000™
and TMS320C6000™ DSP Starter Kits (DSKs). This card resolves most of the trouble involved with
building a custom cable. Additionally, there is also an MSP430-based platform (HPA449) that uses the
MSP430F449 microprocessor, to which this EVM can connect and interface as well. For more details or
information regarding the 5-6k adapter interface card or the HPA449 platform, please contact your Texas
Instruments representative, visit the TI web site or email the Data Converter Applications Support Team at
[e-mail].

The DAC outputs can be monitored through the selected pins of the J4 header connector. All outputs can
be switched through their respective jumpers—JMP11, JMP12, JMP13 and JMP14—for the purpose of
stacking. Stacking allows a total of eight DAC channels to be used, provided the SYNC signals are unique
for each EVM board stacked.

In addition, the option of selecting one DAC output that can be fed to the noninverting side of the output
op amp, U2, is also possible by using a jumper across the selected pins of J4. The output op amp (U2)
must first be correctly configured for the desired waveform characteristic. For more information, refer to

Section 3 of this user’s guide.

A block diagram of the EVM is shown in Figure 1 .

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JMP11
JMP12
JMP13
JMP14

External

Reference

Module

+5V

A

V

DD

+3.3V

A

(J2A)
(J2B)

DACModule

(J4A)
(J4B)

8CH

(J1)

(J5)
(J3A)
(J3B)

4CH

JMP15

JMP16

JMP9

JMP10

DACOut

V

SS

V H

REF

TP4

TP3

V

CC

GND
V

SS

GND
V

DD

+5V

A

+3.3V

A

DIN
LDAC
SCLK
SYNC

JMP5

JMP6

JMP4 JMP3

JMP8

V H

REF

TP2

V

SS

V

CC

V L

REF

Output

Buffer

Module

RST RSTSEL

RSTSEL

EN

RST

Overview

Figure 1. DAC8555EVM Functional Block Diagram

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PCB Design and Performance

1.3.1 Related Documentation from Texas Instruments

The following documents provide information regarding Texas Instrument integrated circuits used in the
assembly of the DAC8555EVM. The latest revisions of these documents are available from the TI web site
at http://www.ti.com.

Data Sheet Literature Number

DAC8555 SLAS475
REF02 SBVS003
OPA627 SBOS165
OPA2132 SBOS054

2 PCB Design and Performance

This section discusses the layout design of the DAC8555EVM PCB, describing the physical and
mechanical characteristics of the EVM as well as a brief description of the demonstration board test
performance procedures performed. The list of components used in this evaluation module is also
included.

2.1 PCB Layout

The DAC8555EVM is designed to preserve the performance quality of the DAC8555, the device under
test (DUT), as specified in the data sheet. In order to take full advantage of the EVM capabilities, use care
during the schematic design phase to properly select the right components and to build the circuit
correctly. The circuit design should include adequate bypassing, identifying and managing the analog and
digital signals, and understanding the components' electrical and mechanical attributes.

The primary design concerns during the layout process are optimal component placement and proper
signal routing. Place the bypass capacitors as close as possible to the device pins, and properly separate
the analog and digital signals from each other. In the layout process, carefully consider the placement of
the power and ground planes. A solid plane is ideal, but because of its greater cost, a split plane can
sometimes be used satisfactorily. When considering a split plane design, analyze the component
placement and carefully split the board into its analog and digital sections starting from the DUT. The
ground plane plays an important role in controlling the noise and other effects that otherwise contribute to
the error of the DAC output. To ensure that the return currents are handled properly, route the appropriate
signals only in their respective sections, meaning that the analog traces should only lay directly above or
below the analog section and the digital traces in the digital section. Minimize trace length, but use the
largest possible trace width allowable within the design. These design practices are illustrated in Figure 2
through Figure 8 .

The DAC8555EVM board is constructed on a four-layer PCB using a copper-clad FR-4 laminate material.
The PCB has a dimension of 43,1800mm (1.7000in) by 82,5500mm (3.2500in), and the board thickness is
1,5748mm (0.062in). Figure 3 through Figure 7 show the individual artwork layers.

Note: Board layouts are not to scale. These are intended to show how the board is laid out; they

are not intended to be used for manufacturing DAC8555EVM PCBs.

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Figure 2. DAC8555EVM PCB—Top Silkscreen Image

PCB Design and Performance

Figure 3. DAC8555EVM PCB—Layer 1 (Top Signal Layer)

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PCB Design and Performance

Figure 4. DAC8555EVM PCB—Layer 2 (Ground Plane)

Figure 5. DAC8555EVM PCB—Layer 3 (Power Plane)

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