Texas Instruments DAC8555EVM User Manual

User's Guide

SLAU204 – December 2006

DAC8555EVM User's Guide

This user’s guide describes the characteristics, operation and use of the DAC8555
Evaluation Module (EVM). It covers all matters related to proper use and configuration
of this EVM along with the devices that it supports. The physical printed circuit board
(PCB) layout, schematic diagram and circuit descriptions are also included. For a more
detailed description of the DAC8555 , see the product data sheet available from the
Texas Instruments web site at http://www.ti.com. Additional support documents are
listed in the section of this guide entitled Related Documentation from Texas

Instruments. Throughout this document, the acronym EVM and the phrases evaluation
module and demonstration board are synonymous with the DAC8555EVM.

TMS320C5000, TMS320C6000 are trademarks of Texas Instruments.
LabVIEW is a trademark of National Instruments.

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Contents

1 Overview ............................................................................................. 3

2 PCB Design and Performance .................................................................... 6

3 EVM Operation .................................................................................... 16

4 Schematic .......................................................................................... 22

List of Figures

1 DAC8555EVM Functional Block Diagram ....................................................... 5

2 DAC8555EVM PCB—Top Silkscreen Image ................................................... 7

3 DAC8555EVM PCB—Layer 1 (Top Signal Layer) ............................................. 7

4 DAC8555EVM PCB—Layer 2 (Ground Plane) ................................................. 8

5 DAC8555EVM PCB—Layer 3 (Power Plane) .................................................. 8

6 DAC8555EVM PCB—Layer 4 (Bottom Signal Layer) ......................................... 9

7 DAC8555EVM PCB—Bottom Silkscreen Image ............................................... 9

8 DAC8555EVM—Drill Drawing ................................................................... 10

9 INL and DNL Characterization Graph of DAC A .............................................. 11

10 INL and DNL Characterization Graph of DAC B .............................................. 12

11 INL and DNL Characterization Graph of DAC C .............................................. 13

12 INL and DNL Characterization Graph of DAC D .............................................. 14

List of Tables

1 DAC8555EVM Parts List ......................................................................... 15

2 Factory Default Jumper Settings ................................................................ 16

3 DAC Output Channel Mapping .................................................................. 17

4 Unity Gain Output Jumper Settings ............................................................. 18

5 Output Gain of 2 Jumper Settings .............................................................. 18

6 Capacitive Load Drive Output Jumper Settings ............................................... 19

7 Jumper Settings and Functions ................................................................. 19

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1 Overview

This section gives a general overview of the DAC8555EVM and describes some of the factors that must
be considered when using this demonstration board.

1.1 Features

The DAC8555EVM is a simple evaluation module designed for a quick and easy way to evaluate the
functionality and performance of the high-resolution, quad-channel, serial input DAC8555 digital-to-analog
converter (DAC). This EVM features a serial interface to communicate with any host microprocessor or TI
DSP-based system.

1.2 Power Requirements

This subsection describes the power requirements for this device.

1.2.1 Supply Voltage

The DC power supply requirement for the digital section (V
the J5-1 terminal or via the J3-10 terminal (when plugged in with another EVM board or interface card)
and is referenced to ground through the J5-2 and J3-5 terminals. The DC power supply requirements for
the analog section of this EVM are: V
through J1-3 and J1-1 respectively, or through terminals J3-1 and J3-2. The +5V
terminals J5-3 or J3-3, and the +3.3V
are referenced to analog ground through terminals J1-2 and J3-6.

The analog power supply for the device under test, U1, can be powered by either +5V
selecting the proper position of jumper JMP7. This configuration allows the DAC8555 analog section to
operate from either supply power while the I/O and digital section are powered by +5V, V

The V
reference chip, U3 and the reference buffer, U4. The negative rail of the output op amp, U2, can be
selected between V
provide output signal conditioning or to boost capacitive load drive, or for other desired output mode
requirements.

) of this EVM is typically +5V connected to

DD

and V

CC

connects through terminal J3-8. All of the analog power supplies

A

supply source is primarily used to provide the positive rail of the external output op amp, U2, the

CC

and AGND via jumper JMP10. The external op amp is installed as an option to

SS

range from +15.75V to –15.75V (maximum), connecting

SS

connects through

A

or +3.3V

A

DD

Overview

by

A

.

CAUTION

To avoid potential damage to the EVM board, be sure that the correct cables
are connected to their respective terminals as labeled on the EVM board.
Stresses above the maximum listed voltage ratings may cause permanent
damage to the device.

1.2.2 Reference Voltage

The +5V precision voltage reference is provided to supply the external voltage reference for the DAC
through the REF02 (U3) via jumper JMP8, by shorting pins 1 and 2. The reference voltage goes through
an adjustable 100k Ω potentiometer, R15, in series with 20k Ω , R16, to allow the user to adjust the
reference voltage to its desired settings. The voltage reference is then buffered through U4A as seen by
the device under test. The test points TP2, TP3 and TP4 are also provided, as well as J4-18 and J4-20, in
order to allow the user to connect another external reference source if the onboard reference circuit is not
desired. The external voltage reference should not exceed +5V DC.

The REF02 precision reference is powered by V

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(+15V) through either terminal J1-3 or J3-1.

CC

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Overview

1.3 EVM Basic Functions

CAUTION

When applying an external voltage reference through TP2 or J4-20, make sure
that it does not exceed +5V maximum. External voltage references in excess of
+5V can permanently damage the DAC8555 being tested (U1).

The DAC8555EVM is designed to provide a demonstration platform for testing certain operational
characteristics of the DAC8555 digital-to-analog converter. Functional evaluation of the DAC8555 can be
accomplished with the use of any microprocessor, TI DSP or some sort of waveform generator.

Headers J2A (top side) and J2B (bottom side) are pass-through connectors provided to interface a host
processor or waveform generator with the DAC8555EVM using a custom-built cable. These connectors
enable the control signals and data to pass between the host and the device.

A mating adapter interface card (5-6k adapter interface) is also available to fit with TI’s TMS320C5000™
and TMS320C6000™ DSP Starter Kits (DSKs). This card resolves most of the trouble involved with
building a custom cable. Additionally, there is also an MSP430-based platform (HPA449) that uses the
MSP430F449 microprocessor, to which this EVM can connect and interface as well. For more details or
information regarding the 5-6k adapter interface card or the HPA449 platform, please contact your Texas
Instruments representative, visit the TI web site or email the Data Converter Applications Support Team at
[e-mail].

The DAC outputs can be monitored through the selected pins of the J4 header connector. All outputs can
be switched through their respective jumpers—JMP11, JMP12, JMP13 and JMP14—for the purpose of
stacking. Stacking allows a total of eight DAC channels to be used, provided the SYNC signals are unique
for each EVM board stacked.

In addition, the option of selecting one DAC output that can be fed to the noninverting side of the output
op amp, U2, is also possible by using a jumper across the selected pins of J4. The output op amp (U2)
must first be correctly configured for the desired waveform characteristic. For more information, refer to

Section 3 of this user’s guide.

A block diagram of the EVM is shown in Figure 1 .

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JMP11
JMP12
JMP13
JMP14

External

Reference

Module

+5V

A

V

DD

+3.3V

A

(J2A)
(J2B)

DACModule

(J4A)
(J4B)

8CH

(J1)

(J5)
(J3A)
(J3B)

4CH

JMP15

JMP16

JMP9

JMP10

DACOut

V

SS

V H

REF

TP4

TP3

V

CC

GND
V

SS

GND
V

DD

+5V

A

+3.3V

A

DIN
LDAC
SCLK
SYNC

JMP5

JMP6

JMP4 JMP3

JMP8

V H

REF

TP2

V

SS

V

CC

V L

REF

Output

Buffer

Module

RST RSTSEL

RSTSEL

EN

RST

Overview

Figure 1. DAC8555EVM Functional Block Diagram

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PCB Design and Performance

1.3.1 Related Documentation from Texas Instruments

The following documents provide information regarding Texas Instrument integrated circuits used in the
assembly of the DAC8555EVM. The latest revisions of these documents are available from the TI web site
at http://www.ti.com.

Data Sheet Literature Number

DAC8555 SLAS475
REF02 SBVS003
OPA627 SBOS165
OPA2132 SBOS054

2 PCB Design and Performance

This section discusses the layout design of the DAC8555EVM PCB, describing the physical and
mechanical characteristics of the EVM as well as a brief description of the demonstration board test
performance procedures performed. The list of components used in this evaluation module is also
included.

2.1 PCB Layout

The DAC8555EVM is designed to preserve the performance quality of the DAC8555, the device under
test (DUT), as specified in the data sheet. In order to take full advantage of the EVM capabilities, use care
during the schematic design phase to properly select the right components and to build the circuit
correctly. The circuit design should include adequate bypassing, identifying and managing the analog and
digital signals, and understanding the components' electrical and mechanical attributes.

The primary design concerns during the layout process are optimal component placement and proper
signal routing. Place the bypass capacitors as close as possible to the device pins, and properly separate
the analog and digital signals from each other. In the layout process, carefully consider the placement of
the power and ground planes. A solid plane is ideal, but because of its greater cost, a split plane can
sometimes be used satisfactorily. When considering a split plane design, analyze the component
placement and carefully split the board into its analog and digital sections starting from the DUT. The
ground plane plays an important role in controlling the noise and other effects that otherwise contribute to
the error of the DAC output. To ensure that the return currents are handled properly, route the appropriate
signals only in their respective sections, meaning that the analog traces should only lay directly above or
below the analog section and the digital traces in the digital section. Minimize trace length, but use the
largest possible trace width allowable within the design. These design practices are illustrated in Figure 2
through Figure 8 .

The DAC8555EVM board is constructed on a four-layer PCB using a copper-clad FR-4 laminate material.
The PCB has a dimension of 43,1800mm (1.7000in) by 82,5500mm (3.2500in), and the board thickness is
1,5748mm (0.062in). Figure 3 through Figure 7 show the individual artwork layers.

Note: Board layouts are not to scale. These are intended to show how the board is laid out; they

are not intended to be used for manufacturing DAC8555EVM PCBs.

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Figure 2. DAC8555EVM PCB—Top Silkscreen Image

PCB Design and Performance

Figure 3. DAC8555EVM PCB—Layer 1 (Top Signal Layer)

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PCB Design and Performance

Figure 4. DAC8555EVM PCB—Layer 2 (Ground Plane)

Figure 5. DAC8555EVM PCB—Layer 3 (Power Plane)

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Figure 6. DAC8555EVM PCB—Layer 4 (Bottom Signal Layer)

PCB Design and Performance

Figure 7. DAC8555EVM PCB—Bottom Silkscreen Image

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PCB Design and Performance

2.2 EVM Performance

Figure 8. DAC8555EVM—Drill Drawing

The EVM performance test is executed using a high-density DAC bench test board, an Agilent 3458A
digital multimeter and a PC running LabVIEW™ software. The EVM board is tested for linearity for all
codes between 485 and 64741. The DUT is then allowed to settle for 1ms before the meter is read. This
process is repeated for all codes to generate the measurements for INL and DNL.

Results of the DAC8555EVM tests are shown in Figure 9 through Figure 12 .

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PCB Design and Performance

Figure 9. INL and DNL Characterization Graph of DAC A

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PCB Design and Performance

Figure 10. INL and DNL Characterization Graph of DAC B

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PCB Design and Performance

Figure 11. INL and DNL Characterization Graph of DAC C

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PCB Design and Performance

Figure 12. INL and DNL Characterization Graph of DAC D

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2.3 Bill of Materials

PCB Design and Performance

The parts list, showing the components used in the assembly of the DAC8555EVM, is given in Table 1 .

Table 1. DAC8555EVM Parts List

QTY

ITEM BOARD Ref Des MFR PART NUMBER DESCRIPTION

1 4 R11–R14 Panasonic ERJ-3GEY0R00V Chip Resistor, 0 Ω , 1/10W, 0603
2 1 R24 Panasonic ERJ-8GEYJ101V Chip Resistor, 100 Ω , 1/4W, 1206

Not

Installed

3 7 Panasonic ERJ-3EKF1002V Chip Resistor, 10k Ω , 1/16W, 0603
4 1 R16 Panasonic ERJ-3EKF2002V Chip Resistor, 20k Ω , 1/16W, 0603

5 1 R10 Bourns 3214W-1-203E Series 5T Pot., 20k Ω , BOURNS_32X4W
6 1 R15 Bourns 3214W-1-104E Series 5T Pot., 100k Ω , BOURNS_32X4W

Not

Installed

7 1 C12 TDK C1608C0G1H102J Multilayer Ceramic Capacitor, 1nF, 0603 C0G
8 4 C4–C7 TDK C1608X7R1E104K Multilayer Ceramic Capacitor, 0.1 µ F, 0603 X7R
9 2 C10, C11 TDK C2012X7R1E105K Multilayer Ceramic Capacitor, 1 µ F, 0805 X7R

10 3 C1, C2, C3 TDK C3216X7R1C106M Multilayer Ceramic Capacitor, 10 µ F, 1206 X7R

Not

Installed

11 1 U1 Texas Instruments DAC8555IPW
12 1 U2 Texas Instruments OPA627AU 8-SOP(D) Precision Op Amp

13 1 U3 Texas Instruments REF02AU +5V, 8-SOP(D) Precision Voltage Reference
14 1 U4 Texas Instruments OPA2132UA 8-SOP(D) Dual Precision Op Amp

Not

Installed

15 2 J2A, J4A Samtec TSM-110-01-L-DV-P
16 1 J3A Samtec TSM-105-01-L-DV-P
17 2 J2B, J4B Samtec SSW-110-22-F-D-VS-K
18 1 J3B Samtec SSW-105-22-F-D-VS-K
19 6 JMP1–JMP6 Samtec TSW-102-07-G-S 2-position Jumper_ .1in spacing

20 10 JMP7–JMP16 Samtec TSW-103-07-G-S 3-position Jumper_ .1in spacing
21 1 TP4 Keystone Electronics 5011 Testpoint, Large-Loop

Not TP1, TP2, TP3,

Installed TP5, TP6

22 16 N/A Samtec SNT-100-BK-G-H Shorting Block

PER MFR

2 R5, R6 Panasonic ERJ-3GEYJ302V Chip Resistor, 3k Ω , 1/10W, 0603

R1–R4, R7, R8,
R9

7 R17–R23 Panasonic Chip Resistor, 1/4W 1206

2 C8, C9 TDK Multilayer Ceramic Capacitor, 1206

16-bit, Quad Voltage Output, Serial Input DAC,
TSSOP-16

2 J1, J5 On-Shore Technology ED555/3DS 3-Pin Terminal Connector

SMT Header, 10x2x0.1, 20-pin, .025in
SMT Header, 5x2x0.1, 10-pin, .025in
SMT Socket, 10x2x0.1, 20-pin, .025in
SMT Socket, 5x2x0.1, 10-pin, .025in

5 Keystone Electronics 5000 Testpoint, Mini-Loop

2

2

2

2

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EVM Operation

3 EVM Operation

3.1 Default Settings

This section covers the operation of the EVM in detail, in order to provide guidance to the user in
evaluating the onboard DAC as well as how to interface the EVM to a specific host processor. Refer to the

DAC8555 datasheet for information about its serial interface and other related topics. The EVM board is

factory-tested and configured.

The EVM is set to its factory default configuration as described in Table 2 to operate in 5V mode.

Table 2. Factory Default Jumper Settings

Reference Jumper Position Function

JMP1 CLOSE ENABLE pin is tied to DGND
JMP2 CLOSE LDAC pin is tied to DGND. Software LDAC is used.
JMP3 CLOSE RSTSEL pin is tied to DGND.
JMP4 OPEN RST pin is tied to VDD.

V

H is not routed to the inverting input of the op amp for voltage offset with gain of 2

JMP5 OPEN
JMP6 OPEN Output op amp U2 is not configured for a gain of 2.

JMP7 1-2 Analog supply for the DAC8555 is +5V
JPM8 1-2 Onboard external buffered reference U3 is routed to V

JMP9 1-2 V
JMP10 1-2 Negative supply rail of U2 op amp is supplied with VSS.
JMP11 1-2 DAC output A (V
JMP12 1-2 DAC output B (V
JMP13 1-2 DAC output C (V
JMP14 1-2 DAC output D (V
JMP15 1-2 J4-1 is connected to the noninverting input of the output op amp U2.
JMP16 1-2 J4-5 is connected to the output of the op amp U2.

REF

output.

.

A

H.

REF

L is tied to AGND.

REF

A) is routed to J4-2.

OUT

B) is routed to J4-4.

OUT

C) is routed to J4-6.

OUT

D) is routed to J4-8.

OUT

3.2 Host Processor Interface

The host processor drives the DAC. Thus, proper DAC operation depends on a successful configuration
between the host processor and the EVM board. In addition, properly written code is also required to
operate the DAC.

As discussed earlier, a custom cable can be made specific to the host interface platform. The EVM allows
interface to the host processor through header connector J2 for the serial control signals and the serial
data input. The output can be monitored through header connector J4.

An interface adapter card is also available for specific TI DSP DSKs as well as an MSP430-based
microprocessor (see Section 1.3 of this manual). Using the interface card alleviates the tedious task of
building customized cables and allows easy configuration of a simple evaluation system.

The DAC8555 interfaces with any host processor capable of handling SPI protocols or the popular TI
DSPs. For more information regarding the DAC8555 data interface, please refer to the DAC8555

datasheet .

3.3 EVM Stacking

Stacking multiple EVMS is possible if there is a need to evaluate two DAC8555s, yielding a total of eight
output channels. A maximum of two EVMs can be stacked since the output terminal, J4, dictates the
number of DAC channels that can be connected without colliding. Table 3 shows how the DAC output
channels are mapped into the output terminal, J4, with respect to the jumper positions of JMP11, JMP12,
JMP13, and JMP14.

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EVM Operation

Table 3. DAC Output Channel Mapping

Reference Jumper Position Function

JMP11

JMP12

JMP13

JMP14

1-2 DAC output A (V
2-3 DAC output A (V
1-2 DAC output B (V
2-3 DAC output B (V
1-2 DAC output C (V
2-3 DAC output C (V
1-2 DAC output D (V
2-3 DAC output D (V

A) is routed to J4-2.

OUT

A) is routed to J4-10.

OUT

B) is routed to J4-4.

OUT

B) is routed to J4-12.

OUT

C) is routed to J4-6.

OUT

C) is routed to J4-14.

OUT

D) is routed to J4-8.

OUT

D) is routed to J4-16.

OUT

In order to allow exclusive control of each EVM, different SYNC signals must be selected for each
DAC8555. This difference is not easily accomplished as it involves hardware alterations. The EVM board
that sits on the bottom of the stack can use the SYNC signal coming from J2B-7. The pin of J2A-7 can be
cut so that the SYNC signal coming from the bottom EVM board in the stack does not pass through. The
EVM board that sits on top can use the CNTL signal coming from J2-1. The signal of J2-1 must be
jumpered across to J2-7 of the EVM board that sits on the top of the stack. The LDAC, SYNC and
ENABLE control signals are shared. The DAC8555 only responds when the correct SYNC signal is
generated.

The raw outputs of the DAC can be probed through the even numbered pins of J4, the output terminal,
which also provides mechanical stability when stacking or plugging into any interface card. In addition, it
provides easy access for monitoring up to eight DAC channels when stacking two EVMs together.

3.4 Output Op Amp

The DAC8555EVM includes an optional signal conditioning circuit for the DAC output through an external
operational amplifier, U2. The output op amp is set to unity gain configuration by default. Only one DAC
output channel can be monitored at any given time. JMP15 selects which pin of J4 is the input. Either J4-1
or J4-3 can be used as the op amp signal input. The default setting for JMP15 selects J4-1. A shorting
jumper can be placed between one of the DAC outputs and the op amp input. For example, a jumper
across J4-1 and J4-2 places the DAC A output as the input for the op amp if board jumpers are in the
default position. If JMP15 is in the alternate position, then a shorting block between J4-3 and J4-2 makes
the DAC B output the input to the op amp.

The output of U2 passes through JMP16. In the default position, the output connects to J4-5. When
JMP16 is in the alternate position, the output from U2 connects to J4-7. The output can be monitored
from, or passed to, another device from the J4 connector.

The jumper arrangement of JMP15 and JMP16 connecting to J4 allows U2 to be used in the stacked
board arrangement discussed above in Section 3.3 .

The following subsections describe the different configurations of the output amplifier, U2.

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EVM Operation

3.4.1 Unity Gain Output

The buffered output configuration can be used to prevent loading of the DAC8555, though it may add
some slight distortion because of the feedback resistor and capacitor. The feedback circuit can be altered
by simply desoldering R8 and C12 and replacing them with components of desired value. If desired, R8
and C12 can be removed altogether by replacing R8 with a 0 Ω resistor.

Table 4 shows the jumper setting for the unity gain configuration of the DAC external output buffer in

unipolar or bipolar mode.

Reference Unipolar Bipolar Function

JMP5 Open Open Disconnect V

JMP10 2-3 1-2 Supplies V

JMP6 Open Open Disconnect negative input of op amp from the gain resistor, R9.

3.4.2 Output Gain of 2

There are two types of configurations that will yield an output gain of 2, depending on the setup of jumpers
JMP5 and JMP6. These configurations allow the user to choose whether the DAC output will use V
as an offset. Table 5 shows the proper jumper settings of the EVM for the DAC8555 output gain of 2.

Table 4. Unity Gain Output Jumper Settings

Jumper Setting

H from the inverting input of the op amp.

REF

to the negative rail of the op amp or ties it to AGND.

SS

H

REF

Jumper Setting

Reference Unipolar Bipolar Function

Close Close

JMP5

Open Open

JMP10 2-3 1-2

Close Close

JMP6

Open Open

Table 5. Output Gain of 2 Jumper Settings

Inverting input of the output op amp U2 is connected to V
voltage with a gain of 2. JMP6 must be open.

V

H is disconnected from the inverting input of the output op amp U2. JMP6 must be

REF

closed.
Supplies power, VSS, to the negative rail of op amp U2 for bipolar mode, or ties it to

AGND for unipolar mode.
Configures op amp U2 for a gain of 2 output without a voltage offset. JMP5 must be

open.
Inverting input of op amp U2 is disconnected from the gain resistor, R9. JMP5 must be

closed.

H for use as its offset

REF

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3.4.3 Capacitive Load Drive

It may be required to drive a wide range of capacitive loads. However, under certain conditions, all op
amps may become unstable, depending on the op amp configuration, gain, and load value. These factors
are just few of the issues that can affect op amp stability and should be considered during implementation.

In unity gain configuration, the OPA627 op amp (U2) performs very well with very large capacitive loads.
Increasing the gain enhances amplifier ability to drive even more capacitance, and adding a load resistor
even improves the capacitive load drive capability.

Table 6 shows the jumper setting configuration for a capacitive load drive.

Table 6. Capacitive Load Drive Output Jumper Settings

Jumper Setting

Reference Unipolar Bipolar Function

JMP5 Open Open V

JMP10 2-3 1-2

JMP6 Open Open

H is disconnected from the inverting input of the output op amp U2.

REF

Supplies power, VSS, to the negative rail of op amp U2 for bipolar mode, or ties it to AGND
for unipolar mode.

Capacitive load drive output of DAC is routed to pin 2 of JMP6 and may be used as the
output terminal.

3.5 Optional Signal Conditioning Op-Amp (U4B)

One half of the OPA2132 dual package op amp (U4) is used for reference buffering (U4A), while the other
half is unused. This unused op amp (U4B) is left for whatever op amp circuit application the user desires
to implement. The 1206 footprint for the resistors and capacitors surrounding the U4B op amp are not
populated and are made available for easy configuration. Test points TP5 and TP6 are not installed, so it
is up to the user on how to connect the ( ± ) input signals to this op amp. No test point has been made
available for the output because of space restrictions, but a wire can be soldered to the output of the op
amp via an unused component pad that connects to it. The op amp circuit can be configured by populating
the corresponding components to those that match the circuit design while leaving all other unused
component footprints unpopulated.

EVM Operation

3.6 Jumper Settings

Table 7 shows the function of each specific jumper setting of the EVM.

Table 7. Jumper Settings and Functions

Reference Jumper Setting

JMP1

JMP2

JMP3

(1)

Indicates the corresponding pins that are shorted or closed.

(1)

Function

ENABLE pin is set high through pull-up resistor R1. ENABLE can be driven by GPIO2,
J2-8.

ENABLE pin is set low and DAC is enabled.

LDAC pin is set high through pull-up resistor R2. LDAC can be driven by GPIO0, J2-2.

LDAC pin is set low and DAC update is accomplished via software.

RSTSEL pin is set high through pull-up resistor R3. RSTSEL can be driven by GPIO4,
J2-14.

RSTSEL pin is set low.

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1 3

1 3

1 3

1 3

1 3

1 3

1 3

1 3

1 3

1 3

EVM Operation

Table 7. Jumper Settings and Functions (continued)

Reference Jumper Setting

JMP4

(1)

Function

RST pin is set high through pull-up resistor R4. RST can be driven by GPIO5, J2-19.

RST pin is set low.

Disconnects V

H to the inverting input of the op amp U2.

REF

JMP5

Connects V

H to the inverting input of the op amp U2.

REF

Disconnects the inverting input of the op amp U2 from the gain resistor, R9.

JMP6

Connects the inverting input of the op amp U2 from the gain resistor, R9 for output gain of

2.

+5V analog supply is selected for AV

.

DD

JMP7

+3.3V analog supply is selected for AV

Routes the adjustable, buffered, onboard +5V reference to the V
DAC8555.

.

DD

H input of the

REF

JMP8

Routes the user-supplied reference from TP2 or J4-20 to the V
DAC8555.

V

L is tied to AGND.

REF

REF

H input of the

JMP9

Routes the user-supplied negative reference from TP3 or J4-18 to the V
DAC8555. This voltage should be within the range of 0V to V

H.

REF

REF

L input of the

Negative supply rail of the op amp U2 is powered by V

for bipolar operation.

SS

JMP10

Negative supply rail of the op amp U2 is tied to AGND for unipolar operation.

Routes V

A to J4-2.

OUT

JMP11

Routes V

A to J4-10.

OUT

20 DAC8555EVM User's Guide SLAU204 – December 2006

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1 3

1 3

1 3

1 3

1 3

1 3

1 3

1 3

1 3

1 3

Reference Jumper Setting

Table 7. Jumper Settings and Functions (continued)

(1)

Function

EVM Operation

Routes V

B to J4-4.

OUT

JMP12

Routes V

Routes V

B to J4-12.

OUT

C to J4-6.

OUT

JMP13

Routes V

Routes V

C to J4-14.

OUT

D to J4-8.

OUT

JMP14

Routes V

D to J4-16.

OUT

Routes J4-1 to U2 noninverting input.

JMP15

Routes J4-3 to U2 noninverting input.

Routes U2 output to J4-5.

JMP16

Routes U2 output to J4-7.

SLAU204 – December 2006 DAC8555EVM User's Guide 21

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Schematic

4 Schematic

22 DAC8555EVM User's Guide SLAU204 – December 2006

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REV ENGINEERING CHANGE NUMBER APPROVED

K

K

K

REVISION HISTORY

JMP7

VDD

D

R1
10KR210KR310KR410KR5NIR6NI

+5VA

C5

0.1uFC210uF

LDAC

ENABLE
RSTSEL
RST

SDI

JMP2

JMP1

1 2

C

B

A

1 2

VCC

C1
10uFC40.1uF

U3

2

3

VCC VSS+5VA -5VA VDD+3.3VD +1.8VD +3.3VA

1 2

VIN

TEMP

JMP3

1
3
5
7
9

1 2

JMP4

GND

REF02AU

4

J3A

+VA
+5VA
DGND
+1.8VD
+3.3VD

1

VOUT

TRIM

2

R10 20K

-VA

-5VA

AGND

VD1

+5VD

SCLK
SYNC

6

5

3

2
4
6
8
10

DAUGHTER-POWER

J3A (TOP) = SAM_TSM-105-01-L-DV-P
J3B (BOTTOM) = SAM_SSW-105-22-F-D-VS-

123

TP1
REF OUT

3

R15

100K

1

R16
20k

+3.3VA

AVDD

R11 0
R12 0

2

U1

4

AVDD

16

LDAC

15

ENABLE

14

RSTSEL

13

RST

11

Din

10

SCLK

9

SYNC

6

GND

DAC8555IPW

VCC

C6

0.1uF

84

3

2

U4A
OPA2132UA

R13
0

VCC = +15V Analog
VDD = +2.7V to +5.0V Digital
VSS = 0V to -15V Analog

VCC

VDD

R14

IO_V/DVDD

VrefH

VrefL

VoutA

VoutB

VoutC

VoutD

C7

0.1uFC310uF

12

3

VrefH

JMP11

5

VrefL

OUT_A

1
2
3

OUT A

JMP12

1

2

7

8

OUT_B

OUT_C
OUT_D

1
2
3

1
2
3

OUT B

JMP13

-REFin

+REFin

J4A

2

A0(+)
A1(+)
A2(+)
A3(+)
A4
A5
A6
A7
REF­REF+

A0(-)
A1(-)
A2(-)

A3(-)
AGND
AGND
AGND
VCOM
AGND
AGND

4
6

8
10
12
14
16
18
20

OUTPUT HEADER

J4A (TOP) = SAM_TSM-110-01-L-DV-P
J4B (BOTTOM) = SAM_SSW-110-22-F-D-VS-

123

JMP15
OPA IN

1
3
5
7
9
11
13
15
17
19

U2_+IN

JMP5

1 2

R7
10K

VrefH

0

U2_-IN

3

2

C10
1uF

JMP6

OUT C

JMP14

1
2
3

OUT D

1

JMP8

JMP9

1
2
3

3
2
1

+REFin

-REFin

VrefH

TP2

EXTERNAL
REFERENCE

TP3

NOTE: Voltage range of -REFin input should not exceed
0 - VrefH.

VrefL

TP4
AGND

C8

NI

R17

R18
NI

TP5
+Vin

J1

J5

TP6

-Vin

R19 NI
R20 NI

R21

1

2

3

1

2

3

NI

NI

5

6

U4B

R23

7

NI

OPA2227UA

R22
NI

123

JMP16
OPA OUT

J2A

1

SCLK
SYNC
SDI

RST

CNTL

3

CLKX

5

CLKR

7

FSX

9

FSR

11

DX

13

DR

15

INT

17

TOUT

19

GPIO5

DAUGHTER-SERIAL

J2A (TOP) = SAM_TSM-110-01-L-DV-P
J2B (BOTTOM) = SAM_SSW-110-22-F-D-VS-

C9

VSS

VCC VDD

+5VA

NI

ENGINEER
DRAWN BY
DOCUMENT CONTROL NO.
SHEET OF FILE

J. PARGUIAN
R. BENJAMIN

6486604

1 1 C:\USERDATA\Projects\DAC8555\DAC8555EVM .ddb

C11

1uF

71

U2

U2_OUT

6

OPA627AU

5

4

VSS

123

R24
100

JMP10

R8
10K

C12

1nF
R9

12

10K

LDAC

2

GPIO0

4

DGND

6

GPIO1
GPIO2

DGND
GPIO3
GPIO4

SCL

DGND

SDA

ENABLE

8
10
12

RSTSEL

14
16
18
20

ti

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HIGH-PERFORMANCE ANALOG DIVISION

SEMICONDUCTOR GROUP

6730 SOUTH TUCSON BLVD., TUCSON, AZ 85706 USA

TITLE

SIZE

DAC8555EVM

B

DATE REV

A11-Oct-2006

D

C

B

A

FCC Warning

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Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are
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