TEXAS INSTRUMENTS DAC6573 Technical data

www.ti.com

Resistor
Network

8

18

Data

Buffer A

DAC

Register A

Data

Buffer D

DAC

Register D

DAC A

DAC D

Buffer

Control

Register

Control

Power−Down
Control Logic

V

OUT

A

V

OUT

B

V

OUT

C

V

OUT

D

V

REF

LA0 A1 A2 A3GND

I2C Block

SCL
SDA

LDAC

V

REF

H

IOV

DD

V

DD

QUAD, 10-Bit, LOW-POWER, VOLTAGE OUTPUT,

I2C INTERFACE DIGITAL-TO-ANALOG CONVERTER

FEATURES DESCRIPTION

• Micropower Operation: 500 µA at 3 V V

• Fast Update Rate: 188 kSPS

• Power-On Reset to Zero

• 2.7-V to 5.5-V Analog Power Supply

• 10-Bit Monotonic

• I2C™ Interface up to 3.4 Mbps

• Data Transmit Capability

• Rail-to-Rail Operation Output Buffer Amplifier

• Double-Buffered Input Register

• Address Support for up to Sixteen DAC6573s

• Synchronous Update for up to 64 Channels

• Voltage Translators for all Digital Inputs

• Operation From –40 ° C to 105 ° C

• Small 16 Lead TSSOP Package

APPLICATIONS

• Process Control

• Data Acquisition Systems

• Closed-Loop Servo Control

• PC Peripherals

• Portable Instrumentation

DAC6573

SLAS402 – NOVEMBER 2003

DD

The DAC6573 is a low-power, quad channel, 10-Bit
buffered voltage output DAC. Its on-chip precision
output amplifier allows rail-to-rail output swing. The
DAC6573 utilizes an I2C compatible two wire serial
interface supporting high-speed interface mode with
address support of up to sixteen DAC6573s for a total
of 64 channels on the bus.

The DAC6573 requires an external reference voltage
to set the output range of the DAC. The DAC6573
incorporates a power-on-reset circuit that ensures
that the DAC output powers up at zero volts and
remains there until a valid write takes place in the
device. The DAC6573 contains a power-down fea­ture, accessed via the internal control register, that
reduces the current consumption of the device to 200
nA at 5 V.

The low power consumption of this part in normal
operation makes it ideally suited to portable battery
operated equipment. The power consumption is less
than 3 mW at V

=5 V reducing to 1 µW in

DD

power-down mode.
The DAC6573 is available in a 16-lead TSSOP

package.

I2C is a trademark of Philips Corporation.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 2003, Texas Instruments Incorporated

www.ti.com

3

A3
A2

A1

1
2
3

4
5

6
7
8

16
15
14

1
12

11
10

9

V

OUT

A

V

OUT

B

V

REF

H

V

DD

V

REF

L

GND

V

OUT

C

V

OUT

D

A0
IOV

DD

SDA
SCL

LDAC

DAC6573

DAC6573

SLAS402 – NOVEMBER 2003

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION

PRODUCT PACKAGE PACKAGE SPECIFICATION PACKAGE ORDERING TRANSPORT MEDIA

DAC6573 16-TSSOP PW –40 °C TO +105 °C D6573I DAC6573IPW 90 Piece Tube

DRAWING TEMPERATURE MARKING NUMBER

NUMBER RANGE

DAC6573IPWR 2000 Piece Tape and Reel

PW PACKAGE

(TOPVIEW)

PIN NAME DESCRIPTION

1 V
2 V
3 V
4 V
5 V

6 GND
7 V

8 V

9 LDAC H/W synchronous V
10 SCL Serial clock input
11 SDA Serial data input
12 IOV
13 A0 Device address select - I2C
14 A1 Device address select - I2C
15 A2 Device address select - Extended
16 A3 Device address select - Extended

ABSOLUTE MAXIMUM RATINGS

V

to GND –0.3 V to +6 V

DD

Digital input voltage to GND –0.3 V to V
V

to GND –0.3 V to V

OUT

Operating temperature range –40 °C to +105 °C
Storage temperature range –65 °C to +150 °C
Junction temperature range (T
Power dissipation Thermal impedance (

Lead temperature, soldering Vapor phase (60s) 215 °C

(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute

maximum conditions for extended periods may affect device reliability.

max) +150 °C

J

Thermal impedance (R

Infrared (15s) 220 °C

(1)

) 161 °C/W

R ΘJA

) 29 °C/W

ΘJC

PIN DESCRIPTIONS

A Analog output voltage from DAC A

OUT

B Analog output voltage from DAC B

OUT

H Positive reference voltage input

REF

Analog voltage supply input

DD

L Negative reference voltage input

REF

Ground reference point for all circuitry on the
part

C Analog output voltage from DAC C

OUT

D Analog output voltage from DAC D

OUT

OUT

I/O voltage supply input

DD

update

+ 0.3 V

DD

+ 0.3 V

DD

2

www.ti.com

DAC6573

SLAS402 – NOVEMBER 2003

ELECTRICAL CHARACTERISTICS

V

= 2.7 V to 5.5 V, RL= 2 k Ω to GND; CL= 200 pF to GND; all specifications -40 ° C to +105 ° C, unless otherwise specified.

DD

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

STATIC PERFORMANCE

Resolution 10 Bits
Relative accuracy ± 0.5 ± 2 LSB
Differential nonlinearity Specified monotonic by design ± 0.1 ± 0.5 LSB
Zero-scale error 5 20 mV
Full-scale error -0.15 ± 1.0 % of FSR
Gain error ± 1.0 % of FSR
Zero code error drift ± 7 µV/ °C
Gain temperature coefficient ± 3 ppm of FSR/ °C

OUTPUT CHARACTERISTICS

Output voltage range 0 V
Output voltage settling time (full scale) RL= ∞ ; 0 pF < CL< 200 pF 7 9 µs

Slew rate 1 V/ µs
dc crosstalk (channel-to-channel) 0.01 LSB
ac crosstalk (channel-to-channel) 1 kHz Sine Wave -100 dB
Capacitive load stability RL= ∞ 470 pF

Digital-to-analog glitch impulse 1 LSB change around major 12 nV-s

Digital feedthrough 0.3 nV-s
dc output impedance 1 Ω
Short-circuit current VDD= 5 V 50 mA

Power-up time Coming out of power-down 2.5 µs

REFERENCE INPUT

V

H Input range 0 V

REF

V

L Input range V

REF

Reference input impedance 25 k Ω
Reference current V

LOGIC INPUTS

(3)

Input current ± 1 µA
V

, Input low voltage 0.3xIOV

IN_L

V

, Input high voltage 0.7xIOV

IN_H

Pin Capacitance 3 pF

POWER REQUIREMENTS

VDD, IOV

DD

IDD(normal operation), including reference current Excluding load current

IDD@ VDD=+3.6V to +5.5V VIH= IOV

IDD@ V

IDD(all power-down modes)

(1) (2)

(3)

=+2.7V to +3.6V VIH= IOV

DD

H V

REF

RL= ∞ ; CL= 500 pF 12 µs

RL= 2 k Ω 1000 pF

carry

VDD= 3 V 20 mA

mode, VDD= +5 V

Coming out of power-down 5 µs

mode, VDD= +3 V

DD

L<V

REF

=V

REF

V

=V

REF

H 0 GND VDD/2 V

REF

= +5 V 185 260 µA

DD

= +3 V 122 200

DD

DD

DD

2.7 5.5 V

and VIL=GND 600 900 µA

DD

and VIL=GND 500 750 µA

DD

V

V
V

(1) Linearity tested using a reduced code range of 12 to 1012; output unloaded.
(2) V
(3) Specified by design and characterization, not production tested.

H = V

REF

- 0.1, V

DD

L = GND

REF

3

www.ti.com

DAC6573

SLAS402 – NOVEMBER 2003

ELECTRICAL CHARACTERISTICS (continued)

V

= 2.7 V to 5.5 V, RL= 2 k Ω to GND; CL= 200 pF to GND; all specifications -40 ° C to +105 ° C, unless otherwise specified.

DD

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

IDD@ VDD=+3.6V to +5.5V VIH= IOV

IDD@ V

=+2.7V to +3.6V VIH= IOV

DD

POWER EFFICIENCY

I

/I

OUT

DD

I

LOAD

TEMPERATURE RANGE

Specified performance -40 +105 °C

TIMING CHARACTERISTICS

V

= 2.7 V to 5.5 V, RL= 2 k Ω to GND; all specifications -40 ° C to +105 ° C, unless otherwise specified.

DD

SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

tHD; t

tSU; t

tSU; t

tHD; t

f

SCL

t

BUF

STA

t

LOW

t

HIGH

STA

DAT

DAT

t

RCL

t

RCL1

SCL clock frequency

High-Speed mode, CB= 100 pF max 3.4 MHz

High-speed mode, CB= 400 pF max 1.7 MHz

Bus free time between a

STOP and START condition

Hold time (repeated) START

condition

LOW period of the SCL clock

High-speed mode, CB= 100 pF max 160 ns
High-speed mode, CB= 400 pF max 320 ns

HIGH period of the SCL clock

High-Speed Mode, CB= 100 pF max 60 ns

High-speed mode, CB= 400 pF max 120 ns

Setup time for a repeated

START condition

Data setup time Fast mode 100 ns

Data hold time

High-speed mode, CB= 100 pF max 0 70 ns
High-speed mode, CB= 400 pF max 0 150 ns

Rise time of SCL signal

High-speed mode, CB= 100 pF max 10 40 ns
High-speed mode, CB= 400 pF max 20 80 ns

Rise time of SCL signal after
a repeated START condition

and after an acknowledge

BIT

High-speed mode, CB= 100 pF max 10 80 ns
High-speed mode, CB= 400 pF max 20 160 ns

and VIL=GND 0.2 1 µA

DD

and VIL=GND 0.05 1 µA

DD

= 2 mA, VDD= +5 V 93%

Standard mode 100 kHz

Fast mode 400 kHz

Standard mode 4.7 µs

Fast mode 1.3 µs

Standard mode 4.0 µs

Fast mode 600 ns

High-speed mode 160 ns

Standard mode 4.7 µs

Fast mode 1.3 µs

Standard mode 4.0 µs

Fast mode 600 ns

Standard mode 4.7 µs

Fast mode 600 ns

High-speed mode 160 ns

Standard mode 250 ns

High-speed mode 10 ns

Standard mode 0 3.45 µs

Fast mode 0 0.9 µs

Standard mode 1000 ns

Fast mode 20 + 0.1C

B

300 ns

Standard mode 1000 ns

Fast mode 20 + 0.1C

B

300 ns

4

www.ti.com

TIMING CHARACTERISTICS (continued)

V

= 2.7 V to 5.5 V, RL= 2 k Ω to GND; all specifications -40 ° C to +105 ° C, unless otherwise specified.

DD

SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Standard mode 300 ns

tSU; t

t

FCL

Fall time of SCL signal

High-speed mode, CB= 100 pF max 10 40 ns

Fast mode 20 + 0.1C

High-speed mode, CB= 400 pF max 20 80 ns

Standard mode 1000 ns

t

RDA

Rise time of SDA signal

High-speed mode, CB= 100 pF max 10 80 ns

Fast mode 20 + 0.1C

High-speed mode, CB= 400 pF max 20 160 ns

Standard mode 300 ns

t

FDA

Fall time of SDA signal

High-speed mode, CB= 100 pF max 10 80 ns

Fast mode 20 + 0.1C

High-speed mode, CB= 400 pF max 20 160 ns

Standard mode 4.0 µs

STO

Setup time for STOP

condition

Fast mode 600 ns

High-speed mode 160 ns

C

B

t

SP

Capacitive load for SDA and

SCL

Pulse width of spike

suppressed

Fast mode 50 ns

High-speed mode 10 ns

Noise margin at the HIGH Standard mode

V

NH

level for each connected

device (including

hysteresis)

Fast mode

High-speed mode

Noise margin at the LOW Standard mode

V

NL

level for each connected

device (including

hysteresis)

Fast mode

High-speed mode

0.2 V

0.1 V

B

B

B

DD

DD

DAC6573

SLAS402 – NOVEMBER 2003

300 ns

300 ns

300 ns

400 pF

V

V

5

www.ti.com

−2

−1

0

1

2

−0.5

−0.25

0

0.25

0.5

0 128 256 384 512 640 768 896 1023

Channel B VDD = 5 V

Digital Input Code

LE − LSBDLE − LSB

−2

−1

0

1

2

−0.5

−0.25

0

0.25

0.5

0 128 256 384 512 640 768 896 1023

Digital Input Code

Channel A VDD = 5 V

LE − LSBDLE − LSB

−0.5

−0.25

0

0.25

0.5

0 128 256

384 512 640 768 896 1023

Channel C VDD = 5 V

Digital Input Code

−2

−1

0

1

2

LE − LSBDLE − LSB

−2

−1

0

1

2

−0.5

−0.25

0

0.25

0.5

0 128 256 384 512 640 768 896 1023

Channel D VDD = 5 V

Digital Input Code

LE − LSBDLE − LSB

−2

−1

0

1

2

−0.5

−0.25

0

0.25

0.5

0 128 256 384 512 640 768 896 1023

Channel A VDD = 2.7 V

Digital Input Code

LE − LSBDLE − LSB

−2

−1

0

1

2

−0.5

−0.25

0

0.25

0.5

0 128 256 384 512 640 768 896 1023

Channel B VDD = 2.7 V

Digital Input Code

LE − LSBDLE − LSB

DAC6573

SLAS402 – NOVEMBER 2003

LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR vs DIGITAL INPUT CODE

LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR vs DIGITAL INPUT CODE

TYPICAL CHARACTERISTICS

At TA= +25 ° C, unless otherwise noted.

LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR AND DIFFERENTIAL

Figure 1. Figure 2.

LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR vs DIGITAL INPUT CODE

6

Figure 3. Figure 4.

Figure 5. Figure 6.

www.ti.com

−2

−1

0

1

2

−0.5

−0.25

0

0.25

0.5

0 128 256 384 512 640 768 896 1023

Channel D VDD = 2.7 V

Digital Input Code

LE − LSBDLE − LSB

−2

−1

0

1

2

−0.5

−0.25

0

0.25

0.5

0 128 256 384 512 640 768 896 1023

Channel C VDD = 2.7 V

Digital Input Code

LE − LSBDLE − LSB

0

3

6

9

−40 −10 20 50 80

VDD = 5 V

CH A

CH D

CH C

CH B

TA − Free-Air Temperature − °C

Zero-Scale Error − mV

−2

0

2

4

−40 −10 20 50 80

CH A

CH D

CH C

CH B

T

A

− Free-Air Temperature − °C

Zero-Scale Error − mV

VDD = 2.7 V

−4

−3

−2

−1

−40 −10 20 50 80

CH A

CH D

CH C

CH B

T

A

− Free-Air Temperature − °C

Full-Scale Error − mV

VDD = 5 V

−2

−1.75

−1.5

−1.25

−1

−40 −10 20 50 80

CH A

CH D

CH C

CH B

T

A

− Free-Air Temperature − °C

Full-Scale Error − mV

VDD = 2.7 V

TYPICAL CHARACTERISTICS (continued)

At TA= +25 ° C, unless otherwise noted.

LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR vs DIGITAL INPUT CODE

ZERO-SCALE ERROR ZERO-SCALE ERROR

DAC6573

SLAS402 – NOVEMBER 2003

Figure 7. Figure 8.

vs TEMPERATURE vs TEMPERATURE

FULL-SCALE ERROR FULL-SCALE ERROR

vs TEMPERATURE vs TEMPERATURE

Figure 9. Figure 10.

Figure 11. Figure 12.

7

www.ti.com

0.000

0.025

0.050

0.075

0.100

0.125

0.150

0 1 2 3 4 5

I

SINK

- Sink Current - mA

V

OUT

- Output Voltage - V

VDD = 2.7 V

VDD = 5.5 V

DAC Loaded With 000

H

Typical For All Channels

5.30

5.35

5.40

5.45

5.50

0 1 2 3 4 5

I

SOURCE

− Source Current − mA

V

OUT

− Output Voltage − V

DAC Loaded With CFF

H

VDD = 5.5 V

Typical For All Channels

2.3

2.4

2.5

2.6

2.7

0 1 2 3 4 5

I

SOURCE

− Source Current − mA

V

OUT

− Output Voltage − V

DAC Loaded With CFF

H

VDD = 2.7 V

Typical For All Channels

Digital Input Code

0

100

200

300

400

500

600

700

800

0 128 256 384 512 640 768 896

I

DD

− Supply Current − µA

VDD = 2.7 V

VDD = 5.5 V

All Channels Powered, No Load

1023

TA - Free-Air Temperature - °C

0

100

200

300

400

500

600

700

-40 -10 20 50 80 110

I

DD

- Supply Current - µA

VDD = 2.7 V

VDD = 5.5 V

All Channels Powered, No Load

VDD - Supply Voltage - V

200

250

300

350

400

450

500

550

600

650

700

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

I

DD

- Supply Current - µA

All DACs Powered, No Load

DAC6573

SLAS402 – NOVEMBER 2003

TYPICAL CHARACTERISTICS (continued)

At TA= +25 ° C, unless otherwise noted.

SINK CURRENT CAPABILITY SOURCE CURRENT CAPABILITY

SOURCE CURRENT CAPABILITY SUPPLY CURRENT

AT NEGATIVE RAIL AT POSITIVE RAIL

Figure 13. Figure 14.

AT POSITIVE RAIL vs DIGITAL INPUT CODE

SUPPLY CURRENT SUPPLY CURRENT

vs TEMPERATURE vs SUPPLY VOLTAGE

8

Figure 15. Figure 16.

Figure 17. Figure 18.

www.ti.com

IDD - Current Consumption - µA

0

500

1000

1500

2000

500 520 540 560 580 600 620 640 660 680 700 720 740

VDD = 5 V

Frequency

V

Logic

− Logic Input Voltage − V

200

400

600

800

1000

1200

0 1 2 3 4 5

I

DD

− Supply Current − µA

TA = 25°C
A0 Input (All Other Inputs = GND)

VDD = 2.7 V

VDD = 5.5 V

−1

0

1

2

3

4

5

6

Time (2 µs/div)

V

OUT

− Output Voltage − V

VDD = 5 V
Powerup to Code 1000

IDD - Current Consumption - µA

0

500

1000

1500

2000

400 420 440 460 480 500 520 540 560 580 600 620

VDD = 2.7 V

Frequency

0

1

2

3

4

5

Time (25 µs/div)

V

OUT

- Output Voltage - V

VDD = 5 V

Output Loaded with

200 pF to GND

10% to 90% FSR

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Time (25 µs/div)

V

OUT

- Output Voltage - V

VDD = 2.7 V

Output Loaded with

200 pF to GND

10% to 90% FSR

TYPICAL CHARACTERISTICS (continued)

At TA= +25 ° C, unless otherwise noted.

vs LOGIC INPUT VOLTAGE OF CURRENT CONSUMPTION

DAC6573

SLAS402 – NOVEMBER 2003

SUPPLY CURRENT HISTOGRAM

Figure 19. Figure 20.

OF CURRENT CONSUMPTION POWER-DOWN MODE

HISTOGRAM EXITING

Figure 21. Figure 22.

LARGE SIGNAL LARGE SIGNAL
SETTLING TIME SETTLING TIME

Figure 23. Figure 24.

9

www.ti.com

−6

−2

2

6

10

14

18

0 128 256 384 512 640 768 896 1023

Channel A Output

Channel B Output

VDD = 2.7 V, TA = 25°C

Digital Input Code

Output Error − mV

Channel D Output

Channel C Output

0

4

8

12

16

20

24

0 128 256 384 512 640 768 896 1023

Channel A Output

Channel D Output

Channel B Output

Channel B Output

VDD = 5 V, TA = 25°C

Digital Input Code

Output Error − mV

DAC6573

SLAS402 – NOVEMBER 2003

TYPICAL CHARACTERISTICS (continued)

At TA= +25 ° C, unless otherwise noted.

ABSOLUTE ERROR

†

ABSOLUTE ERROR

Figure 25. Figure 26.

†

Absolute error is the deviation from ideal DAC characteristics. It includes affects of offset, gain, and integral

linearity.

†

10

www.ti.com

_ +Resistor String

Ref+
Ref−

DAC Register

V

OUT

50 k 50 k

V

REF

H

V

REF

L

70 k

OUT

 2  V

REF

L  (V

REF

H  V

REF

L) 

D

1024

V

REF

H

To Output
Amplifier

R

R R

R

V

REF

L

DAC6573

SLAS402 – NOVEMBER 2003

THEORY OF OPERATION

D/A SECTION

The architecture of the DAC6573 consists of a string DAC followed by an output buffer amplifier. Figure 27
shows a generalized block diagram of the DAC architecture.

Figure 27. R-String DAC Architecture

The input coding to the DAC6573 is unsigned binary, which gives the ideal output voltage as:

Where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 1023.

RESISTOR STRING

The resistor string section is shown in Figure 28 . It is basically a divide-by-2 resistor, followed by a string of
resistors, each of value R. The code loaded into the DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the
amplifier. Because the architecture consists of a string of resistors, it is specified monotonic.

Figure 28. Typical Resistor String

Output Amplifier

The output buffer is a gain-of-2 noninverting amplifier, capable of generating rail-to-rail voltages on its output,
which gives an output range of 0V to V

. It is capable of driving a load of 2 k Ω in parallel with 1000 pF to GND.

DD

The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is 1 V/ µs
with a half-scale settling time of 7 µs with the output unloaded.

I2C Interface

I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus
is idle, both SDA and SCL lines are pulled high. All the I2C-compatible devices connect to the I2C bus through
open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor,
controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also
generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or
transmits data on the bus under control of the master device.

11

www.ti.com

Start

Condition

SDA

Stop

Condition

SDA

SCL

S P

SCL

DAC6573

SLAS402 – NOVEMBER 2003

THEORY OF OPERATION (continued)

The DAC6573 works as a slave and supports the following data transfer modes, as defined in the I2C-Bus
Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (3.4 Mbps). The data
transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/S-mode in
this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as
H/S-mode. The DAC6573 supports 7-bit addressing; 10-bit addressing and general call address are not
supported.

F/S-Mode Protocol

• The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 29 . All I2C-compatible devices
recognize a start condition.

• The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit
R/ W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 30 ). All devices
recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave
device with a matching address generates an acknowledge (see Figure 31 ) by pulling the SDA line low
during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that
communication link with a slave has been established.

• The master generates further SCL cycles to either transmit data to the slave (R/ W bit 1) or receive data from
the slave (R/ W bit 0). In either case, the receiver must acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-Bit data and 1-bit acknowledge can continue as long as
necessary.

• To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 29 ). This releases the bus and stops the communication link
with the addressed slave. All I2C-compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and they wait for a start condition followed by a
matching address.

H/S-Mode Protocol

• When the bus is idle, both SDA and SCL lines are pulled high by the pullup devices.

• The master generates a start condition followed by a valid serial byte containing H/S master code

00001XXX. This transmission is made in F/S mode at no more than 400 Kbps. No device is allowed to
acknowledge the H/S master code, but all devices must recognize it and switch their internal setting to
support 3.4 Mbps operation.

• The master then generates a repeated start condition (a repeated start condition has the same timing as the
start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that
transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the H/S-mode and switches all the
internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated
start conditions must be used to secure the bus in H/S-mode.

Figure 29. START and STOP Conditions

12

www.ti.com

Change of Data Allowed

Data Line

Stable;

Data Valid

SDA

SCL

Not Acknowledge

Acknowledge

1 2 8 9

Clock Pulse for

Acknowledgement

S

START

Condition

Data Output

by Transmitter

Data Output

by Receiver

SCL From

Master

Recognize START or

REPEATED START

Condition

Recognize STOP or

REPEATED START

Condition

Generate ACKNOWLEDGE

Signal

Acknowledgement
Signal From Slave

SDA

SCL

MSB

P

Sr

Sr
or

P

S
or
Sr

START or

Repeated START

Condition

STOP or

Repeated START

Condition

Clock Line Held Low While

Interrupts are Serviced

1 2 7 8 9

ACK

1 2 3 - 8 9

ACK

Address

R/W

THEORY OF OPERATION (continued)

DAC6573

SLAS402 – NOVEMBER 2003

Figure 30. Bit Transfer on the I2C Bus

Figure 31. Acknowledge on the I2C Bus

Figure 32. Bus Protocol

13

www.ti.com

DAC6573

SLAS402 – NOVEMBER 2003

DAC6573 I2C Update Sequence

The DAC6573 requires a start condition, a valid I2C address, a control byte, an MSB byte, and an LSB byte for a
single update. After the receipt of each byte, DAC6573 acknowledges by pulling the SDA line low during the high
period of a single clock pulse. A valid I2C address selects the DAC6573. The control byte sets the operational
mode of the selected DAC6573. Once the operational mode is selected by the control byte, DAC6573 expects an
MSB byte followed by an LSB byte for data update to occur. DAC6573 performs an update on the falling edge of
the acknowledge signal that follows the LSB byte.

The control byte needs not to be resent until a change in operational mode is required. The bits of the control
byte continuously determine the type of update performed. Thus, for the first update, DAC6573 requires a start
condition, a valid I2C address, a control byte, an MSB byte and an LSB byte. For all consecutive updates,
DAC6573 needs an MSB byte, and an LSB byte as long as the control command remains the same.

Using the I2C high-speed mode (f
the first update can be done within 18 clock cycles (MSB byte, acknowledge signal, LSB byte, acknowledge
signal), at 188.88 kSPS. Using the fast mode (f
rate is limited to 22.22 kSPS. Once a stop condition is received, DAC6573 releases the I2C bus and awaits a
new start condition.

Address Byte

MSB LSB

1 0 0 1 1 A1 A0 R/ W

= 3.4 MHz), the clock running at 3.4 MHz, each 10-Bit DAC update other than

scl

= 400 kHz), clock running at 400 kHz, maximum DAC update

scl

The address byte is the first byte received following the START condition from the master device. The first five
bits (MSBs) of the address are factory preset to 10011. The next two bits of the address are the device select
bits A1 and A0. The A1, A0 address inputs can be connected to V

or digital GND, or can be actively driven by

DD

TTL/CMOS logic levels. The device address is set by the state of these pins during the power-up sequence of
the DAC6573. Up to 16 devices (DAC6573) can still be connected to the same I2C-bus.

Broadcast Address Byte

MSB LSB

1 0 0 1 0 0 0 0

Broadcast addressing is also supported by DAC6573. Broadcast addressing can be used for synchronously
updating or powering down multiple DAC6573 devices. DAC6573 is designed to work with other members of the
DAC857x, DAC757x, and DAC557x families to support multichannel synchronous update. Using the broadcast
address, DAC6573 responds regardless of the states of the address pins. Broadcast is supported only in write
mode (master writes to DAC6573).

14

www.ti.com

Control Byte

MSB LSB

A3 A2 L1 L0 X Sel1 Sel0 PD0

Table 1. Control Register Bit Descriptions

Bit Name Bit Number/Description

A3 Extended address bit
A2 Extended address bit
L1 Load1 (mode select) bit
L2 Load0 (mode select) bit

00 Store I2C data. The contents of MS-BYTE and LS-BYTE (or power down information) are stored in the

temporary register of a selected channel. This mode does not change the DAC output of the selected
channel.

01 Update selected DAC with I2C data. Most commonly utilized mode. The contents of MS-BYTE and

LS-BYTE (or power down information) are stored in the temporary register and in the DAC register of the
selected channel. This mode changes the DAC output of the selected channel with the new data.

10 4-channel synchronous update. The contents of MS-BYTE and LS-BYTE (or power down information) are

stored in the temporary register and in the DAC register of the selected channel. Simultaneously, the
other three channels get updated with previously stored data from the temporary register. This mode
updates all four channels together.

11 Broadcast update mode. This mode has two functions. In broadcast mode, DAC6573 responds

regardless of local address matching, and channel selection becomes irrelevant as all channels update.
This mode is intended to enable up to 64 channels simultaneous update, if used with the I2C broadcast
address (1001 0000).

If Sel1=0 All four channels are updated with the contents of their temporary register data.

If Sel1=1 All four channels are updated with the MS-BYTE and LS-BYTE data or powerdown.
Sel1 Buff Sel1 Bit
Sel0 Buff Sel0 Bit

00 Channel A
01 Channel B
10 Channel C
11 Channel D

PD0 Power Down Flag

0 Normal operation
1 Power-down flag (MSB7 and MSB6 indicate a power-down operation, as shown in Table 2 ).

The state of these bits must match the state of pins A3 and A2 in order for a proper
DAC6573 data update, except in broadcast update mode.

Are used for selecting the update mode.

Channel select bits

DAC6573

SLAS402 – NOVEMBER 2003

15

www.ti.com

DAC6573

SLAS402 – NOVEMBER 2003

Table 2. Control Byte

C7 C6 C5 C4 C3 C2 C1 C0 MSB7 MSB6 MSB5...
A3 A2 Load1 Load0 Ch Sel 1 Ch Sel 0 PD0

(Address

Select)

(A3 and A2 0 0 X 0 0 0 Data Write to temporary

should corre- register A (TRA) with

spond to the data
package ad-

dress, set via

pins A3 and

A2)

X X 1 1 X 0 X X X devices with previously

X X 1 1 X 1 X 0 Data devices with MSB[7:0]

X X 1 1 X 1 X 1 see Table 8 0

0 0 X 0 1 0 Data register B (TRB) with

0 0 X 1 0 0 Data register C (TRC) with

0 0 X 1 1 0 Data register D (TRD) with

0 0 X 1 See Table 8 0

0 1 X 0 Data by C2 & C1 and load

0 1 X 1 See Table 8 0 (selected by C2 and

1 0 X 0 Data by C2 & C1 w/ data

1 0 X 1 See Table 8 0 (selected by C2 and

Broadcast Modes (controls up to 4 devices on a single serial bus)

Don't MSB MSB-1 MSB-2

Care (PD1) (PD2) ...LSB DESCRIPTION

Write to temporary
data

Write to temporary
data

Write to temporary
data

(00, 01, 10, or 11) Write to TRx (selected

by C2 & C1
w/Powerdown
Command

(00, 01, 10, or 11) Write to TRx (selected

DACx w/data

(00, 01, 10, or 11) Power-down DACx

C1)

(00, 01, 10, or 11) Write to TRx (selected

and load all DACs

(00, 01, 10, or 11) Power-down DACx

C1) & load all DACs

Update all DACs, all
stored TRx data

Update all DACs, all
and LSB[7:0] data

Power-down all DACs,
all devices

Most Significant Byte

Most significant byte MSB[7:0] consists of eight most significant bits of 10-bit unsigned binary D/A conversion
data. If C0=1, MSB[7], MSB[6] indicate a power-down operation as shown in Table 8 .

Least Significant Byte

Least significant byte LSB[7:0] consists of the 2 least significant bits of the 10-Bit unsigned binary D/A conversion
data, followed by 6 don't care bits. DAC6573 updates at the falling edge of the acknowledge signal that follows
the LSB[0] bit.

Default Readback Condition

If the user initiates a readback of a specified channel without first writing data to that specified channel, the
default readback is all zeros, since the readback register is initialized to 0 during the power on reset phase.

16

www.ti.com

SLAVE ADDRESS R/W A Ctrl-Byte A MS-Byte A LS-Byte A/A P

0 (write)

Data Transferred

(n* Words + Acknowledge)

Word = 16 Bit

From Master to DAC6573
From DAC6573 to Master

A = Acknowledge (SDA LOW)
A = Not Acknowledge (SDA HIGH)
S = START Condition
Sr = Repeated START Condition
P = STOP Condition

DAC6573 I2C-SLAVE ADDRESS:

1 0 0 1 1 A1 A0 R/W

MSB LSB

Factory Preset

A0 = I2C Address Pin
A1 = I2C Address Pin

S

0 = Write to DAC6573
1 = Read from DAC6573

DAC6573

SLAS402 – NOVEMBER 2003

LDAC Functionality

Depending on the control byte, DACs are synchronously updated on the falling edge of the acknowledge signal
that follows LS byte. The LDAC pin is required only when an external timing signal is used to update all the
channels of the DAC asynchronously. LDAC is a positive edge triggered asynchronous input that allows four
DAC output voltages to be updated simultaneously with temporary register data. The LDAC trigger should only
be used after the buffer's temporary registers are properly updated through software.

DAC6573 Registers

Table 3. DAC6573 Architecture Register Descriptions

REGISTER DESCRIPTION

CTRL[7:0] Stores 8-Bit wide control byte sent by the master
MSB[7:0]
LSB[7:0] Stores the 2 least significant bits of unsigned binary data sent by the master (in LSB[7] and LSB[6]).

TRA[11:0], TRB[11:0], 12-bit temporary storage registers assigned to each channel. Two MSBs store power-down information, 10 LSBs
TRC[11:0], TRD[11:0] store data.

DRA[11:0], DRB[11:0], 12-bit DAC registers for each channel. Two MSBs store power-down information, 10 LSBs store DAC data. An
DRC[11:0], DRD[11:0] update of this register means a DAC update with data or power-down.

DAC6573 as a Slave Receiver—Standard and Fast Mode

Figure 33 shows the standard and fast mode master transmitter addressing a DAC6573 Slave Receiver with a
7-bit address.

Stores the 8 most significant bits of unsigned binary data sent by the master. Can also store 2-bit power-down
data.

Figure 33. Standard and Fast Mode: Slave Receiver

17

www.ti.com

HS-Master Code R/W A Ctrl-Byte A MS-Byte A LS-Byte A/A P

0 (write)

Data Transferred

(n* Words + Acknowledge)

Word = 16 Bit

S A Sr Slave Address

HS-Mode Continues

F/S-Mode HS-Mode F/S-Mode

Sr Slave Address

0 0 0 0 1 X X R/W

MSB LSB

HS-Mode Master Code:

A3 A2 L1 L0 X Sel1 Sel2 PD0

MSB LSB

Control Byte:

A3 = Extended Address Bit
A2 = Extended Address Bit
L1 = Load1 (Mode Select) Bit
L0 = Load0 (Mode Select) Bit
Sel1 = Buff Sel1 (Channel) Select Bit
Sel0 = Buff Sel0 (Channel) Select Bit
PD0 = Power Down Flag

D9 D8 D7 D6 D5 D4 D3 D2

MSB LSB

MS-Byte:

D1 D0 X X X X X X

MSB LSB

LS-Byte:

D9 − D0 = Data Bits

X = Don’t Care

DAC6573

SLAS402 – NOVEMBER 2003

DAC6573 as a Slave Receiver - High-Speed Mode

Figure 34 shows the high-speed mode master transmitter addressing a DAC6573 Slave Receiver with a 7-bit
address.

Figure 34. High-Speed Mode: Slave Receiver

18

www.ti.com

DAC6573

SLAS402 – NOVEMBER 2003

Master Transmitter Writing to a Slave Receiver (DAC6573) in Standard/Fast Modes

All write access sequences begin with the device address (with R/ W = 0) followed by the control byte. This
control byte specifies the operation mode of DAC6573 and determines which channel of DAC6573 is being
accessed in the subsequent read/write operation. The LSB of the control byte (PD0-Bit) determines whether the
following data is power-down data or regular data.

With (PD0-Bit = 0) the DAC6573 expects to receive data in the following sequence HIGH-BYTE –LOW-BYTE –
HIGH-BYTE – LOW-BYTE..., until a STOP Condition or REPEATED START Condition on the I2C-bus is
recognized (refer to the DATA INPUT MODE section of Table 4 ).

With (PD0-Bit = 1) the DAC6573 expects to receive 2 bytes of power-down data (refer to the POWER DOWN
MODE section of Table 4 ).

Table 4. Write Sequence in F/S Mode

DATA INPUT MODE
Transmitter MSB 6 5 4 3 2 1 LSB Comment

Master Start Begin sequence
Master 1 0 0 1 1 A1 A0 R/ W Write addressing ( R/ W=0)
DAC6573 DAC6573 Acknowledges
Master A3 A2 Load 1 Load 0 x Buff Sel 1 Buff Sel 0 PD0 Control byte ( PD0=0)
DAC6573 DAC6573 Acknowledges
Master D9 D8 D7 D6 D5 D4 D3 D2 Writing data word, high byte
DAC6573 DAC6573 Acknowledges
Master D1 D0 x x x x x x Writing data word, low byte
DAC6573 DAC6573 Acknowledges
Master Data or Stop or Repeated Start

POWER DOWN MODE

Transmitter MSB 6 5 4 3 2 1 LSB Comment
Master Start Begin sequence
Master 1 0 0 1 1 A1 A0 R/ W Write addressing (R/ W=0)
DAC6573 DAC6573 Acknowledges
Master A3 A2 Load 1 Load 0 x Buff Sel 1 Buff Sel 0 PD0 Control byte ( PD0 = 1)
DAC6573 DAC6573 Acknowledges
Master PD1 PD2 0 0 0 0 0 0 Writing data word, high byte
DAC6573 DAC6573 Acknowledges
Master 0 0 x x x x x x Writing data word, low byte
DAC6573 DAC6573 Acknowledges
Master Stop or Repeated Start

(1) Use repeated START to secure bus operation and loop back to the stage of write addressing for next Write.
(2) Once DAC6573 is properly addressed and control byte is sent, HIGH–BYTE–LOW–BYTE sequences can repeat until a STOP condition

or repeated START condition is received.

(1)

(1)

Data or done

Done

(2)

19

www.ti.com

DAC6573

SLAS402 – NOVEMBER 2003

Master Transmitter Writing to a Slave Receiver (DAC6573) in HS Mode

When writing data to the DAC6573 in HS-mode, the master begins to transmit what is called the HS-Master
Code (0000 1XXX) in F/S-mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master
Code is followed by a NOT acknowledge.

The master then switches to HS-mode and issues a repeated start condition, followed by the address byte (with
R/ W = 0) after which the DAC6573 acknowledges by pulling SDA low. This address byte is usually followed by
the control byte, which is also acknowledged by the DAC6573. The LSB of the control byte (PD0-Bit) determines
if the following data is power-down data or regular data.

With (PD0-Bit = 0) the DAC6573 expects to receive data in the following sequence HIGH-BYTE – LOW-BYTE –

HIGH-BYTE – LOW-BYTE...., until a STOP condition or repeated start condition on the I2C-Bus is recognized

(refer to Table 5 HS-MODE WRITE SEQUENCE - DATA).
With (PD0-Bit = 1) the DAC6573 expects to receive 2 bytes of power-down data (refer to Table 5 HS-MODE

WRITE SEQUENCE - POWER DOWN).

Table 5. Master Transmitter Writes to Slave Receiver (DAC6573) in HS-Mode

HS MODE WRITE SEQUENCE - DATA

Transmitter MSB 6 5 4 3 2 1 LSB Comment
Master Start Begin sequence
Master 0 0 0 0 1 X X X HS mode master code

NONE Not acknowledge
Master Repeated start

Master 1 0 0 1 1 A1 A0 R/ W Write addressing ( R/ W=0)
DAC6573 DAC6573 acknowledges
Master 0 0 Load 1 Load 0 0 Buff Sel 1 Buff Sel 0 PD0 Control byte ( PD0=0)
DAC6573 DAC6573 acknowledges
Master D9 D8 D7 D6 D5 D4 D3 D2 Writing data word, MSB
DAC6573 DAC6573 acknowledges
Master D1 D0 x x x x x x Writing data word, LSB
DAC6573 DAC6573 acknowledges
Master Data or stop or repeated start

HS MODE WRITE SEQUENCE - POWER DOWN

Transmitter MSB 6 5 4 3 2 1 LSB Comment
Master Start Begin sequence
Master 0 0 0 0 1 X X X HS mode master code

NONE Not acknowledge
Master Repeated start

Master 1 0 0 1 1 A1 A0 R/ W Write addressing ( R/ W = 0)
DAC6573 DAC6573 acknowledges
Master 0 0 Load 1 Load 2 0 Buff Sel 1 Buff Sel 0 PD0 Control byte ( PD0=1)
DAC6573 DAC6573 acknowledges
Master PD1 PD2 0 0 0 0 0 0 Writing data word, high byte
DAC6573 DAC6573 acknowledges
Master 0 0 x x x x x x Writing data word, low byte
DAC6573 DAC6573 acknowledges
Master Stop or repeated start

(1) Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write.
(2) Once DAC6573 is properly addressed and control byte is sent, high-byte-low-byte sequences can repeat until a stop or repeated start

condition is received.

(1)

(1)

No device may acknowledge HS mas­ter code

Data or done

No device may acknowledge HS mas­ter code

Done

(2)

20

www.ti.com

SLAVE ADDRESS R/W A Ctrl <7:1> A MS-Byte A LS-Byte A P

0 (write)

Data Transferred

(2 Bytes + Acknowledge)

PDN-Byte:

PD1 PD2 1 1 1 1 1 1

MSB LSB

S

PD0 Sr Slave Address R/W A

1 (read)

0 = (Normal Mode)

A PDN-Byte A LS-Byte A PPD0 Sr Slave Address R/W A MS-Byte A

(DAC6573) (MASTER) (MASTER)

1 = (Power Down Flag)

Data Transferred

(3 Bytes + Acknowledge)

(DAC6573) (MASTER) (MASTER) (MASTER)

PD1 = Power Down Bit
PD2 = Power Down Bit

1 (read)

(DAC6573) (DAC6573)

Slave Address R/WACtrl <7:1> A MS-Byte A LS-Byte A P

0 (write)

Data Transferred

(2 Bytes + Acknowledge)

PD0Sr Slave Address R/W A

1 (read)

0 = (Normal Mode)

A PDN-Byte A LS-Byte A PPD0 Sr Slave Address R/W A MS-Byte A

(DAC6573) (DAC6573) (DAC6573) (MASTER) (MASTER)

1 = (Power Down Flag)

Data Transferred

(3 Bytes + Acknowledge)

(DAC6573) (MASTER) (MASTER) (MASTER)

Sr

HS-Mode

AS

F/S-Mode

1 (read)

HS-Master Code

DAC6573

SLAS402 – NOVEMBER 2003

DAC6573 as a Slave Transmitter—Standard and Fast Mode

Figure 35 shows the standard and fast mode master receiver addressing a DAC6573 Slave Transmitter with a
7-bit address.

Figure 35. Standard and Fast Mode: Slave Transmitter

DAC6573 as a Slave Transmitter - High-Speed Mode

Figure 36 shows an I2C-Master addressing DAC6573 in high-speed mode (with a 7-bit address), as a Slave
Transmitter.

Figure 36. High-Speed Mode: Slave Transmitter

21

www.ti.com

DAC6573

SLAS402 – NOVEMBER 2003

Master Receiver Reading From a Slave Transmitter (DAC6573) in Standard/Fast Modes

When reading data back from the DAC6573, the user begins with an address byte (with R/ W = 0) after which the
DAC6573 acknowledges by pulling SDA low. This address byte is usually followed by the control byte, which is
also acknowledged by the DAC6573. Following this there is a REPEATED START condition by the master and
the address is resent with (R/ W = 1). This is acknowledged by the DAC6573, indicating that it is prepared to
transmit data. Two or three bytes of data are then read back from the DAC6573, depending on the (PD0-Bit).
The value of Buff-Sel1 and Buff-Sel0 determines, which channel data is read back. A STOP Condition follows.

With the (PD0-Bit = 0) the DAC6573 transmits 2 bytes of data, HIGH-BYTE followed by the LOW-BYTE (refer to
Table 6 . Data Readback Mode - 2 bytes).

With the (PD0-Bit = 1) the DAC6573 transmits 3 bytes of data, POWER-DOWN-BYTE followed by the
HIGH-BYTE followed by the LOW-BYTE (refer to Table 6 . Data Readback Mode - 3 bytes).

Table 6. Read Sequence in F/S Mode

DATA READBACK MODE - 2 BYTES
Transmitter MSB 6 5 4 3 2 1 LSB Comment

Master Start Begin sequence
Master 1 0 0 1 1 A1 A0 R/ W Write addressing ( R/ W=0)
DAC6573 DAC6573 acknowledges
Master A3 A2 Load 1 Load 0 x Buff Sel 1 Buff Sel 0 PD0 Control byte ( PD0=0)
DAC6573 DAC6573 acknowledges
Master Repeated start
Master 1 0 0 1 1 A1 A0 R/ W Read addressing ( R/ W = 1)
DAC6573 DAC6573 acknowledges
DAC6573 D9 D8 D7 D6 D5 D4 D3 D2 Reading data word, high byte
Master Master acknowledges
DAC6573 D1 D0 x x x x x x Reading data word, low byte
Master Master not acknowledges Master signal end of read
Master Stop or repeated start

DATA READBACK MODE - 3 BYTES

Transmitter MSB 6 5 4 3 2 1 LSB Comment
Master Start Begin sequence
Master 1 0 0 1 1 A1 A0 R/ W Write addressing ( R/ W=0)
DAC6573 DAC6573 acknowledges
Master A3 A2 Load 1 Load 0 x Buff Sel 1 Buff Sel 0 PD0 Control byte ( PD0=1)
DAC6573 DAC6573 acknowledges
Master Repeated start
Master 1 0 0 1 1 A1 A0 R/ W Read addressing ( R/ W = 1)
DAC6573 DAC6573 acknowledges
DAC6573 PD1 PD2 1 1 1 1 1 1 Read power down byte
Master Master acknowledges
DAC6573 D9 D8 D7 D6 D5 D4 D3 D2 Reading data word, high byte
Master Master acknowledges
DAC6573 D1 D0 x x x x x x Reading data word, low byte
Master Master not acknowledges Master signal end of read
Master Stop or repeated start

(1) Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write.

(1)

(1)

Done

Done

22

www.ti.com

DAC6573

SLAS402 – NOVEMBER 2003

Master Receiver Reading From a Slave Transmitter (DAC6573) in HS-Mode

When reading data to the DAC6573 in HS-MODE, the master begins to transmit, what is called the HS-Master
Code (0000 1XXX) in F/S mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master
Code is followed by a NOT acknowledge.

The master then switches to HS-mode and issues a REPEATED START condition, followed by the address byte
(with R/ W = 0) after which the DAC6573 acknowledges by pulling SDA low. This address byte is usually followed
by the control byte, which is also acknowledged by the DAC6573.

Then there is a REPEATED START condition initiated by the master and the address is resent with (R/ W = 1).
This is acknowledged by the DAC6573, indicating that it is prepared to transmit data. Two or three bytes of data
are then read back from the DAC6573, depending on the (PD0-Bit). The value of Buff-Sel1 and Buff-Sel0
determines, which channel data is read back. A STOP condition follows.

With the (PD0-Bit = 0) the DAC6573 transmits 2 bytes of data, HIGH-BYTE followed by LOW-BYTE (refer to
Table 7 HS-Mode Readback Sequence).

With the (PD0-Bit = 1) the DAC6573 transmits 3 bytes of data, POWER-DOWN-BYTE followed by the
HIGH-BYTE followed by the LOW-BYTE (refer to Table 7 HS-Mode Readback Sequence).

Table 7. Master Receiver Reading Slave Transmitter (DAC6573) in HS-Mode

HS MODE READBACK SEQUENCE

Transmitter MSB 6 5 4 3 2 1 LSB Comment

Master Start Begin sequence
Master 0 0 0 0 1 X X X HS mode master code

NONE Not acknowledge

Master Repeated start
Master 1 0 0 1 1 A1 A0 R/ W Write addressing ( R/ W=0)

DAC6573 DAC6573 acknowledges

Master A3 A2 Load 1 Load 0 X Buff Sel 1 Buff Sel 0 PD0 Control byte ( PD0 = 1)

DAC6573 DAC6573 acknowledges

Master Repeated start

Master 1 0 0 1 1 A1 A0 R/ W Read addressing ( R/ W=1)
DAC6573 DAC6573 acknowledges
DAC6573 PD1 PD2 1 1 1 1 1 1 Power-down byte

Master Master acknowledges
DAC6573 D9 D8 D7 D6 D5 D4 D3 D2 Reading data word, high byte

Master Master acknowledges
DAC6573 D1 D0 x x x x x x Reading data word, low byte

Master Master not acknowledges Master signal end of read

Master Stop or repeated start Done

No device may acknowledge HS

master code

Power-On Reset

The DAC6573 contains a power-on-reset circuit that controls the output voltage during power up. On power up,
the DAC register is filled with zeros and the output voltage is 0 V; it remains there until a valid write sequence is
made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC
while it is in the process of powering up. Device pins must not be brought high before supply is applied.

Power-Down Modes

The DAC6573 contains four separate power-down modes of operation. The modes are programmable via two
most significant bits of the MSB byte, while (CTRL[0] = PD0 = 1). Table 8 shows how the state of these bits
corresponds to the mode of operation of the device.

23

www.ti.com

Resistor

String DAC

Powerdown

Circuitry

V

OUT

Amplifier

Resistor
Network

DAC6573

SLAS402 – NOVEMBER 2003

Table 8. Power-Down Modes of Operation for the DAC6573

CTRL[0] MSB[7] MSB[6] OPERATING MODE

1 0 0 PWD, high impedance DAC output
1 0 1 PWD, 1 k Ω to GND DAC ouptut
1 1 0 PWD, 100 k Ω to GND DAC output
1 1 1 PWD, high impedance DAC output

When (CTRL[0] = PD0 = 0), the device works normally with its normal power consumption of 150 µA at 5 V per
channel. However, for the power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only
does the supply current fall but also the output stage is also internally switched from the output of the amplifier to
a resistor network of known values. This has the advantage that the output impedance of the device is known
while in power-down mode. There are three different options: The output is connected internally to GND through
a 1 k Ω resistor, a 100 k Ω resistor or left open-circuit (high impedance). The output stage is illustrated in
Figure 37 .

Figure 37. Output Stage During Power Down

All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time to exit power down is typically 2.5 µs for V
µs for V

= 3 V. (See the Typical Curves section for additional information.)

DD

= 5 V and 5

DD

The DAC6573 offers a flexible power-down interface based on channel register operation. A channel consists of
a single 10-bit DAC with power-down circuitry, a temporary storage register (TR) and a DAC register (DR). TR
and DR are both 12 bits wide. Two MSBs represent the power-down condition and the 10 LSBs represent data
for TR and DR. By using bits 11 and 10 of TR and DR, a power-down condition can be temporarily stored and
used just like data. Internal circuits ensure that MSB[7] and MSB[6] get transferred to TR[11] and TR[10] (DR[11]
and DR[10]) when the power-down flag (CTRL[0] = PD0) is set. Therefore, DAC6573 treats power-down
conditions like data and all the operational modes are still valid for power down. It is possible to broadcast a
power-down condition to all the DAC6573s in the system, or it is possible to simultaneously power down a
channel while updating data on other channels.

CURRENT CONSUMPTION

The DAC6573 typically consumes 150 µA at V
including reference current consumption. Additional current consumption can occur at the digital inputs if V
V

. For most efficient power operation, CMOS logic levels are recommended at the digital inputs to the DAC. In

DD

power-down mode, typical current consumption is 200 nA.

= 5 V and 125 µA at V

DD

= 3 V for each active channel,

DD

IH

<<

24

www.ti.com

DAC6573

SLAS402 – NOVEMBER 2003

IOV

IOV
V
ies—connect it to the logic supply of the system. Analog circuits and internal logic of the DAC6573 use V
the supply voltage. The external logic high inputs get translated to V
the IOV
V regardless of the V
V, IOV
consumption, ensure that logic V

AND VOLTAGE TRANSLATORS

DD

pin powers the digital input structures of the DAC6573. For single-supply operation, IOV

DD

. For dual-supply operation, the IOV

DD

voltage as a reference to shift the incoming logic HIGH levels to V

DD

operates as low as 1.8 V with degraded timing and temperature performance. For lowest power

DD

voltage, ensuring compatibility with various logic families. Although specified down to 2.7

DD

levels are as close as possible to IOV

IH

pin provides interface flexibility with various CMOS logic famil-

DD

by level shifters. These level shifters use

DD

. IOV

DD

, and logic V

DD

can be tied to

DD

operates from 2.7 V to 5.5

DD

levels as close as

IL

DD

possible to GND voltages.

DRIVING RESISTIVE AND CAPACITIVE LOADS

The DAC6573 output stage is capable of driving loads of up to 1000 pF while remaining stable. Within the offset
and gain error margins, the DAC6573 can operate rail-to-rail when driving a capacitive load. Resistive loads of 2
k Ω can be driven by the DAC6573 while achieving a good load regulation. When the outputs of the DAC are
driven to the positive rail under resistive loading, the PMOS transistor of each Class-AB output stage can enter
into the linear region. When this occurs, the added IR voltage drop deteriorates the linearity performance of the
DAC. This only occurs within approximately the top 20 mV of the DAC's digital input-to-voltage output transfer
characteristic. The reference voltage applied to the DAC6573 may be reduced below the supply voltage applied
to V

in order to eliminate this condition if good linearity is a requirement at full scale (under resistive loading

DD

conditions).

CROSSTALK

The DAC6573 architecture uses separate resistor strings for each DAC channel in order to achieve ultra-low
crosstalk performance. DC crosstalk seen at one channel during a full-scale change on the neighboring channel
is typically less than 0.01 LSBs. The ac crosstalk measured (for a full-scale, 1-kHz sine wave output generated at
one channel, and measured at the remaining output channel) is typically under -100 dB.

as

OUTPUT VOLTAGE STABILITY

The DAC6573 exhibits excellent temperature stability of ±3 ppm/ °C typical output voltage drift over the specified
temperature range of the device. This enables the output voltage of each channel to stay within a ±25- µV window
for a ±1 °C ambient temperature change. Combined with good dc noise performance and true 10-Bit differential
linearity, the DAC6573 becomes a perfect choice for closed-loop control applications.

SETTLING TIME AND OUTPUT GLITCH PERFORMANCE

Settling time to within the 10-bit accurate range of the DAC6573 is achievable within 7 µs for a full-scale code
change at the input. Worst case settling times between consecutive code changes is typically less than 2 µs. The
high-speed serial interface of the DAC6573 is designed in order to support up to 188-kSPS update rate. For
full-scale output swings, the output stage of each DAC6573 channel typically exhibits less than 100 mV of
overshoot and undershoot when driving a 200 pF capacitive load. Code-to-code change glitches are extremely
low (~10 µV) given that the code-to-code transition does not cross an Nx64 code boundary. Due to internal
segmentation of the DAC6573, code-to-code glitches occur at each crossing of an Nx64 code boundary. These
glitches can approach 100 mVs for N = 15, but settle out within ~2 µs.

25

www.ti.com

8

6

4

9

5

7

1

2
3

12

14

11
10

13

16

15

DAC6573

V

OUTA

V

OUTB

V

REFH

V

DD

V

REFL

GND
V

OUTC

V

OUTD

A3
A2

A1
A0

IOV

DD

SDA

SCL

L

DAC

SDA

SCL

I2C Pullup Resistors

1 kΩ to 10 kΩ (typical)

IOV

DD

Microcontroller or

Microprocessor With

I2C Port

NOTE: DAC6573 power and input/output connections are omitted for clarity, except IC Inputs.

DAC6573

SLAS402 – NOVEMBER 2003

APPLICATION INFORMATION

The following sections give example circuits and tips for using the DAC6573 in various applications. For more
information, contact your local TI representative, or visit the Texas Instruments website at http://www.ti.com.

BASIC CONNNECTIONS

For many applications, connecting the DAC6573 is extremely simple. A basic connection diagram for the
DAC6573 is shown in Figure 38 . The 0.1 µF bypass capacitors provide the momentary bursts of extra current
needed from the supplies.

The DAC6573 interfaces directly to standard mode, fast mode and high-speed mode I2C controllers. Any
microcontroller's I2C peripheral, including master-only and non-multiple-master I2C peripherals, work with the
DAC6573. The DAC6573 does not perform clock-stretching (i.e., it never pulls the clock line low), so it is not
necessary to provide for this unless other devices are on the same I2C bus.

Pullup resistors are necessary on both the SDA and SCL lines because I2C bus drivers are open-drain. The size
of the these resistors depend on the bus operating speed and capacitance on the bus lines. Higher-value
resistors consume less power, but increase the transition times on the bus, limiting the bus speed. Lower-value
resistors allow higher speed at the expense of higher power consumption. Long bus lines have higher
capacitance and require smaller pullup resistors to compensate. If the pullup resistors are too small the bus
drivers may not be able to pull the bus line low.

USING GPIO PORTS FOR I2C

Most microcontrollers have programmable input/output pins that can be set in software to act as inputs or
outputs. If an I2C controller is not available, the DAC6573 can be connected to GPIO pins, and the I2C bus
protocol simulated, or bit-banged, in software. An example of this for a single DAC6573 is shown in Figure 39 .

26

Figure 38. Typical DAC6573 Connections

www.ti.com

8

6

4

9

5

7

1

2
3

12

14

11
10

13

16

15

DAC6573

V

OUTA

V

OUTB

V

REFH

V

DD

V

REFL

GND
V

OUTC

V

OUTD

A3
A2

A1
A0

IOV

DD

SDA

SCL

L

DAC

GPIO-2

GPIO-1

IOV

DD

Microcontroller or

Microprocessor

NOTE: DAC6573 power and input/output connections are omitted for clarity, except IC Inputs.

APPLICATION INFORMATION (continued)

DAC6573

SLAS402 – NOVEMBER 2003

Bit-banging I2C with GPIO pins can be done by setting the GPIO line to zero and toggling it between input and
output modes to apply the proper bus states. To drive the line low, the pin is set to output a zero; to let the line
go high, the pin is set to input. When the pin is set to input, the state of the pin can be read; if another device is
pulling the line low, this reads as a zero in the port's input register.

Note that no pullup resistor is shown on the SCL line. In this simple case the resistor is not needed. The
microcontroller can simply leave the line on output, and set it to one or zero as appropriate. It can do this
because the DAC6573 never drives its clock line low. This technique can also be used with multiple devices, and
has the advantage of lower current consumption due to the absence of a resistive pullup.

If there are any devices on the bus that may drive their clock lines low, do not use the above method. The SCL
line must be high-Z or zero, and a pullup resistor must be provided as usual. Note also that this cannot be done
on the SDA line in any case, because the DAC6573 drives the SDA line low from time to time, as all I2C devices
do.

Some microcontrollers have selectable strong pullup circuits built in to their GPIO ports. In some cases, these
can be switched on and used in place of an external pullup resistor. Weak pullups are also provided on some
microcontrollers, but usually these are too weak for I2C communication. Test any circuit before committing it to
production.

USING REF02 AS A POWER SUPPLY FOR DAC6573

Due to the extremely low supply current required by the DAC6573, a possible configuration is to use a REF02
+5-V precision voltage reference to supply the required voltage to the DAC6573 supply input as well as the
reference input, as shown in Figure 40 . This is especially useful if the power supply is quite noisy or if the system
supply voltages are at some value other than 5 V. The REF02 outputs a steady supply voltage for the DAC6573.
If the REF02 is used, the current it needs to supply to the DAC6573 is 600 µA typical and 900 µA max for

Figure 39. Using GPIO With a Single DAC6573

27

www.ti.com

REF02

15 V

5 V

1.6 mA

V

DD

SCL

SDA

I2C

Interface

V

OUT

= 0 V to 5 V

DAC6573

DAC6573

SLAS402 – NOVEMBER 2003

APPLICATION INFORMATION (continued)

V

= 5 V. When a DAC output is loaded, the REF02 also needs to supply the current to the load. The total

DD

typical current required (with a 5-k Ω load on a single DAC output) is:
600 µA + (5 V / 5 k Ω) = 1.6 mA
The load regulation of the REF02 is typically 0.005%/mA, which results in an error of 400 µV for 1.6 mA of

current drawn from it. This corresponds to a 0.08 LSB error for a 0 V to 5 V output range.

Figure 40. REF02 Power Supply

LAYOUT

A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power
supplies.

For best performance, the power applied to V
and dc/dc converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital
components can create similar high-frequency spikes as their internal logic switches states. This noise can easily
couple into the DAC output voltage through various paths between the power connections and analog output.

As with the GND connection, V

must be connected to a positive power-supply plane or trace that is separate

DD

from the connection for digital logic until they are connected at the power-entry point. In addition, a 1- µF to 10- µF
capacitor in parallel with a 0.1- µF bypass capacitor is strongly recommended. In some situations, additional
bypassing may be required, such as a 100 µF electrolytic capacitor or even a Pi filter made up of inductors and
capacitors—all designed to essentially low-pass filter the –5-V supply, removing the high-frequency noise.

must be well-regulated and low noise. Switching power supplies

DD

28

PACKAGE OPTION ADDENDUM

www.ti.com

18-Oct-2005

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

DAC6573IPW ACTIVE TSSOP PW 16 90 Green (RoHS &

no Sb/Br)

DAC6573IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &

no Sb/Br)

DAC6573IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS &

no Sb/Br)

DAC6573IPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

(3)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DAT A

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

1,20 MAX

14

0,30
0,19

8

4,50
4,30

PINS **

7

Seating Plane

0,15
0,05

8

1

A

DIM

14

0,10

6,60
6,20

M

0,10

0,15 NOM

2016

0°–8°

Gage Plane

24

0,25

0,75
0,50

28

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

4040064/F 01/97

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. T esting and other quality control techniques are used to the extent TI
deems necessary to support this warranty . Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:

Products Applications

Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive

DSP dsp.ti.com Broadband www.ti.com/broadband
Interface interface.ti.com Digital Control www.ti.com/digitalcontrol
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security

Telephony www.ti.com/telephony
Video & Imaging www.ti.com/video
Wireless www.ti.com/wireless

Mailing Address: Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

Copyright  2005, Texas Instruments Incorporated