TEXAS INSTRUMENTS DAC6573 Technical data

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Resistor
Network

8

18

Data

Buffer A

DAC

Register A

Data

Buffer D

DAC

Register D

DAC A

DAC D

Buffer

Control

Register

Control

Power−Down
Control Logic

V

OUT

A

V

OUT

B

V

OUT

C

V

OUT

D

V

REF

LA0 A1 A2 A3GND

I2C Block

SCL
SDA

LDAC

V

REF

H

IOV

DD

V

DD

QUAD, 10-Bit, LOW-POWER, VOLTAGE OUTPUT,

I2C INTERFACE DIGITAL-TO-ANALOG CONVERTER

FEATURES DESCRIPTION

• Micropower Operation: 500 µA at 3 V V

• Fast Update Rate: 188 kSPS

• Power-On Reset to Zero

• 2.7-V to 5.5-V Analog Power Supply

• 10-Bit Monotonic

• I2C™ Interface up to 3.4 Mbps

• Data Transmit Capability

• Rail-to-Rail Operation Output Buffer Amplifier

• Double-Buffered Input Register

• Address Support for up to Sixteen DAC6573s

• Synchronous Update for up to 64 Channels

• Voltage Translators for all Digital Inputs

• Operation From –40 ° C to 105 ° C

• Small 16 Lead TSSOP Package

APPLICATIONS

• Process Control

• Data Acquisition Systems

• Closed-Loop Servo Control

• PC Peripherals

• Portable Instrumentation

DAC6573

SLAS402 – NOVEMBER 2003

DD

The DAC6573 is a low-power, quad channel, 10-Bit
buffered voltage output DAC. Its on-chip precision
output amplifier allows rail-to-rail output swing. The
DAC6573 utilizes an I2C compatible two wire serial
interface supporting high-speed interface mode with
address support of up to sixteen DAC6573s for a total
of 64 channels on the bus.

The DAC6573 requires an external reference voltage
to set the output range of the DAC. The DAC6573
incorporates a power-on-reset circuit that ensures
that the DAC output powers up at zero volts and
remains there until a valid write takes place in the
device. The DAC6573 contains a power-down fea­ture, accessed via the internal control register, that
reduces the current consumption of the device to 200
nA at 5 V.

The low power consumption of this part in normal
operation makes it ideally suited to portable battery
operated equipment. The power consumption is less
than 3 mW at V

=5 V reducing to 1 µW in

DD

power-down mode.
The DAC6573 is available in a 16-lead TSSOP

package.

I2C is a trademark of Philips Corporation.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 2003, Texas Instruments Incorporated

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3

A3
A2

A1

1
2
3

4
5

6
7
8

16
15
14

1
12

11
10

9

V

OUT

A

V

OUT

B

V

REF

H

V

DD

V

REF

L

GND

V

OUT

C

V

OUT

D

A0
IOV

DD

SDA
SCL

LDAC

DAC6573

DAC6573

SLAS402 – NOVEMBER 2003

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION

PRODUCT PACKAGE PACKAGE SPECIFICATION PACKAGE ORDERING TRANSPORT MEDIA

DAC6573 16-TSSOP PW –40 °C TO +105 °C D6573I DAC6573IPW 90 Piece Tube

DRAWING TEMPERATURE MARKING NUMBER

NUMBER RANGE

DAC6573IPWR 2000 Piece Tape and Reel

PW PACKAGE

(TOPVIEW)

PIN NAME DESCRIPTION

1 V
2 V
3 V
4 V
5 V

6 GND
7 V

8 V

9 LDAC H/W synchronous V
10 SCL Serial clock input
11 SDA Serial data input
12 IOV
13 A0 Device address select - I2C
14 A1 Device address select - I2C
15 A2 Device address select - Extended
16 A3 Device address select - Extended

ABSOLUTE MAXIMUM RATINGS

V

to GND –0.3 V to +6 V

DD

Digital input voltage to GND –0.3 V to V
V

to GND –0.3 V to V

OUT

Operating temperature range –40 °C to +105 °C
Storage temperature range –65 °C to +150 °C
Junction temperature range (T
Power dissipation Thermal impedance (

Lead temperature, soldering Vapor phase (60s) 215 °C

(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute

maximum conditions for extended periods may affect device reliability.

max) +150 °C

J

Thermal impedance (R

Infrared (15s) 220 °C

(1)

) 161 °C/W

R ΘJA

) 29 °C/W

ΘJC

PIN DESCRIPTIONS

A Analog output voltage from DAC A

OUT

B Analog output voltage from DAC B

OUT

H Positive reference voltage input

REF

Analog voltage supply input

DD

L Negative reference voltage input

REF

Ground reference point for all circuitry on the
part

C Analog output voltage from DAC C

OUT

D Analog output voltage from DAC D

OUT

OUT

I/O voltage supply input

DD

update

+ 0.3 V

DD

+ 0.3 V

DD

2

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DAC6573

SLAS402 – NOVEMBER 2003

ELECTRICAL CHARACTERISTICS

V

= 2.7 V to 5.5 V, RL= 2 k Ω to GND; CL= 200 pF to GND; all specifications -40 ° C to +105 ° C, unless otherwise specified.

DD

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

STATIC PERFORMANCE

Resolution 10 Bits
Relative accuracy ± 0.5 ± 2 LSB
Differential nonlinearity Specified monotonic by design ± 0.1 ± 0.5 LSB
Zero-scale error 5 20 mV
Full-scale error -0.15 ± 1.0 % of FSR
Gain error ± 1.0 % of FSR
Zero code error drift ± 7 µV/ °C
Gain temperature coefficient ± 3 ppm of FSR/ °C

OUTPUT CHARACTERISTICS

Output voltage range 0 V
Output voltage settling time (full scale) RL= ∞ ; 0 pF < CL< 200 pF 7 9 µs

Slew rate 1 V/ µs
dc crosstalk (channel-to-channel) 0.01 LSB
ac crosstalk (channel-to-channel) 1 kHz Sine Wave -100 dB
Capacitive load stability RL= ∞ 470 pF

Digital-to-analog glitch impulse 1 LSB change around major 12 nV-s

Digital feedthrough 0.3 nV-s
dc output impedance 1 Ω
Short-circuit current VDD= 5 V 50 mA

Power-up time Coming out of power-down 2.5 µs

REFERENCE INPUT

V

H Input range 0 V

REF

V

L Input range V

REF

Reference input impedance 25 k Ω
Reference current V

LOGIC INPUTS

(3)

Input current ± 1 µA
V

, Input low voltage 0.3xIOV

IN_L

V

, Input high voltage 0.7xIOV

IN_H

Pin Capacitance 3 pF

POWER REQUIREMENTS

VDD, IOV

DD

IDD(normal operation), including reference current Excluding load current

IDD@ VDD=+3.6V to +5.5V VIH= IOV

IDD@ V

IDD(all power-down modes)

(1) (2)

(3)

=+2.7V to +3.6V VIH= IOV

DD

H V

REF

RL= ∞ ; CL= 500 pF 12 µs

RL= 2 k Ω 1000 pF

carry

VDD= 3 V 20 mA

mode, VDD= +5 V

Coming out of power-down 5 µs

mode, VDD= +3 V

DD

L<V

REF

=V

REF

V

=V

REF

H 0 GND VDD/2 V

REF

= +5 V 185 260 µA

DD

= +3 V 122 200

DD

DD

DD

2.7 5.5 V

and VIL=GND 600 900 µA

DD

and VIL=GND 500 750 µA

DD

V

V
V

(1) Linearity tested using a reduced code range of 12 to 1012; output unloaded.
(2) V
(3) Specified by design and characterization, not production tested.

H = V

REF

- 0.1, V

DD

L = GND

REF

3

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DAC6573

SLAS402 – NOVEMBER 2003

ELECTRICAL CHARACTERISTICS (continued)

V

= 2.7 V to 5.5 V, RL= 2 k Ω to GND; CL= 200 pF to GND; all specifications -40 ° C to +105 ° C, unless otherwise specified.

DD

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

IDD@ VDD=+3.6V to +5.5V VIH= IOV

IDD@ V

=+2.7V to +3.6V VIH= IOV

DD

POWER EFFICIENCY

I

/I

OUT

DD

I

LOAD

TEMPERATURE RANGE

Specified performance -40 +105 °C

TIMING CHARACTERISTICS

V

= 2.7 V to 5.5 V, RL= 2 k Ω to GND; all specifications -40 ° C to +105 ° C, unless otherwise specified.

DD

SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

tHD; t

tSU; t

tSU; t

tHD; t

f

SCL

t

BUF

STA

t

LOW

t

HIGH

STA

DAT

DAT

t

RCL

t

RCL1

SCL clock frequency

High-Speed mode, CB= 100 pF max 3.4 MHz

High-speed mode, CB= 400 pF max 1.7 MHz

Bus free time between a

STOP and START condition

Hold time (repeated) START

condition

LOW period of the SCL clock

High-speed mode, CB= 100 pF max 160 ns
High-speed mode, CB= 400 pF max 320 ns

HIGH period of the SCL clock

High-Speed Mode, CB= 100 pF max 60 ns

High-speed mode, CB= 400 pF max 120 ns

Setup time for a repeated

START condition

Data setup time Fast mode 100 ns

Data hold time

High-speed mode, CB= 100 pF max 0 70 ns
High-speed mode, CB= 400 pF max 0 150 ns

Rise time of SCL signal

High-speed mode, CB= 100 pF max 10 40 ns
High-speed mode, CB= 400 pF max 20 80 ns

Rise time of SCL signal after
a repeated START condition

and after an acknowledge

BIT

High-speed mode, CB= 100 pF max 10 80 ns
High-speed mode, CB= 400 pF max 20 160 ns

and VIL=GND 0.2 1 µA

DD

and VIL=GND 0.05 1 µA

DD

= 2 mA, VDD= +5 V 93%

Standard mode 100 kHz

Fast mode 400 kHz

Standard mode 4.7 µs

Fast mode 1.3 µs

Standard mode 4.0 µs

Fast mode 600 ns

High-speed mode 160 ns

Standard mode 4.7 µs

Fast mode 1.3 µs

Standard mode 4.0 µs

Fast mode 600 ns

Standard mode 4.7 µs

Fast mode 600 ns

High-speed mode 160 ns

Standard mode 250 ns

High-speed mode 10 ns

Standard mode 0 3.45 µs

Fast mode 0 0.9 µs

Standard mode 1000 ns

Fast mode 20 + 0.1C

B

300 ns

Standard mode 1000 ns

Fast mode 20 + 0.1C

B

300 ns

4

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TIMING CHARACTERISTICS (continued)

V

= 2.7 V to 5.5 V, RL= 2 k Ω to GND; all specifications -40 ° C to +105 ° C, unless otherwise specified.

DD

SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Standard mode 300 ns

tSU; t

t

FCL

Fall time of SCL signal

High-speed mode, CB= 100 pF max 10 40 ns

Fast mode 20 + 0.1C

High-speed mode, CB= 400 pF max 20 80 ns

Standard mode 1000 ns

t

RDA

Rise time of SDA signal

High-speed mode, CB= 100 pF max 10 80 ns

Fast mode 20 + 0.1C

High-speed mode, CB= 400 pF max 20 160 ns

Standard mode 300 ns

t

FDA

Fall time of SDA signal

High-speed mode, CB= 100 pF max 10 80 ns

Fast mode 20 + 0.1C

High-speed mode, CB= 400 pF max 20 160 ns

Standard mode 4.0 µs

STO

Setup time for STOP

condition

Fast mode 600 ns

High-speed mode 160 ns

C

B

t

SP

Capacitive load for SDA and

SCL

Pulse width of spike

suppressed

Fast mode 50 ns

High-speed mode 10 ns

Noise margin at the HIGH Standard mode

V

NH

level for each connected

device (including

hysteresis)

Fast mode

High-speed mode

Noise margin at the LOW Standard mode

V

NL

level for each connected

device (including

hysteresis)

Fast mode

High-speed mode

0.2 V

0.1 V

B

B

B

DD

DD

DAC6573

SLAS402 – NOVEMBER 2003

300 ns

300 ns

300 ns

400 pF

V

V

5

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−2

−1

0

1

2

−0.5

−0.25

0

0.25

0.5

0 128 256 384 512 640 768 896 1023

Channel B VDD = 5 V

Digital Input Code

LE − LSBDLE − LSB

−2

−1

0

1

2

−0.5

−0.25

0

0.25

0.5

0 128 256 384 512 640 768 896 1023

Digital Input Code

Channel A VDD = 5 V

LE − LSBDLE − LSB

−0.5

−0.25

0

0.25

0.5

0 128 256

384 512 640 768 896 1023

Channel C VDD = 5 V

Digital Input Code

−2

−1

0

1

2

LE − LSBDLE − LSB

−2

−1

0

1

2

−0.5

−0.25

0

0.25

0.5

0 128 256 384 512 640 768 896 1023

Channel D VDD = 5 V

Digital Input Code

LE − LSBDLE − LSB

−2

−1

0

1

2

−0.5

−0.25

0

0.25

0.5

0 128 256 384 512 640 768 896 1023

Channel A VDD = 2.7 V

Digital Input Code

LE − LSBDLE − LSB

−2

−1

0

1

2

−0.5

−0.25

0

0.25

0.5

0 128 256 384 512 640 768 896 1023

Channel B VDD = 2.7 V

Digital Input Code

LE − LSBDLE − LSB

DAC6573

SLAS402 – NOVEMBER 2003

LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR vs DIGITAL INPUT CODE

LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR vs DIGITAL INPUT CODE

TYPICAL CHARACTERISTICS

At TA= +25 ° C, unless otherwise noted.

LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR AND DIFFERENTIAL

Figure 1. Figure 2.

LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR vs DIGITAL INPUT CODE

6

Figure 3. Figure 4.

Figure 5. Figure 6.

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−2

−1

0

1

2

−0.5

−0.25

0

0.25

0.5

0 128 256 384 512 640 768 896 1023

Channel D VDD = 2.7 V

Digital Input Code

LE − LSBDLE − LSB

−2

−1

0

1

2

−0.5

−0.25

0

0.25

0.5

0 128 256 384 512 640 768 896 1023

Channel C VDD = 2.7 V

Digital Input Code

LE − LSBDLE − LSB

0

3

6

9

−40 −10 20 50 80

VDD = 5 V

CH A

CH D

CH C

CH B

TA − Free-Air Temperature − °C

Zero-Scale Error − mV

−2

0

2

4

−40 −10 20 50 80

CH A

CH D

CH C

CH B

T

A

− Free-Air Temperature − °C

Zero-Scale Error − mV

VDD = 2.7 V

−4

−3

−2

−1

−40 −10 20 50 80

CH A

CH D

CH C

CH B

T

A

− Free-Air Temperature − °C

Full-Scale Error − mV

VDD = 5 V

−2

−1.75

−1.5

−1.25

−1

−40 −10 20 50 80

CH A

CH D

CH C

CH B

T

A

− Free-Air Temperature − °C

Full-Scale Error − mV

VDD = 2.7 V

TYPICAL CHARACTERISTICS (continued)

At TA= +25 ° C, unless otherwise noted.

LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR vs DIGITAL INPUT CODE

ZERO-SCALE ERROR ZERO-SCALE ERROR

DAC6573

SLAS402 – NOVEMBER 2003

Figure 7. Figure 8.

vs TEMPERATURE vs TEMPERATURE

FULL-SCALE ERROR FULL-SCALE ERROR

vs TEMPERATURE vs TEMPERATURE

Figure 9. Figure 10.

Figure 11. Figure 12.

7

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0.000

0.025

0.050

0.075

0.100

0.125

0.150

0 1 2 3 4 5

I

SINK

- Sink Current - mA

V

OUT

- Output Voltage - V

VDD = 2.7 V

VDD = 5.5 V

DAC Loaded With 000

H

Typical For All Channels

5.30

5.35

5.40

5.45

5.50

0 1 2 3 4 5

I

SOURCE

− Source Current − mA

V

OUT

− Output Voltage − V

DAC Loaded With CFF

H

VDD = 5.5 V

Typical For All Channels

2.3

2.4

2.5

2.6

2.7

0 1 2 3 4 5

I

SOURCE

− Source Current − mA

V

OUT

− Output Voltage − V

DAC Loaded With CFF

H

VDD = 2.7 V

Typical For All Channels

Digital Input Code

0

100

200

300

400

500

600

700

800

0 128 256 384 512 640 768 896

I

DD

− Supply Current − µA

VDD = 2.7 V

VDD = 5.5 V

All Channels Powered, No Load

1023

TA - Free-Air Temperature - °C

0

100

200

300

400

500

600

700

-40 -10 20 50 80 110

I

DD

- Supply Current - µA

VDD = 2.7 V

VDD = 5.5 V

All Channels Powered, No Load

VDD - Supply Voltage - V

200

250

300

350

400

450

500

550

600

650

700

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

I

DD

- Supply Current - µA

All DACs Powered, No Load

DAC6573

SLAS402 – NOVEMBER 2003

TYPICAL CHARACTERISTICS (continued)

At TA= +25 ° C, unless otherwise noted.

SINK CURRENT CAPABILITY SOURCE CURRENT CAPABILITY

SOURCE CURRENT CAPABILITY SUPPLY CURRENT

AT NEGATIVE RAIL AT POSITIVE RAIL

Figure 13. Figure 14.

AT POSITIVE RAIL vs DIGITAL INPUT CODE

SUPPLY CURRENT SUPPLY CURRENT

vs TEMPERATURE vs SUPPLY VOLTAGE

8

Figure 15. Figure 16.

Figure 17. Figure 18.

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IDD - Current Consumption - µA

0

500

1000

1500

2000

500 520 540 560 580 600 620 640 660 680 700 720 740

VDD = 5 V

Frequency

V

Logic

− Logic Input Voltage − V

200

400

600

800

1000

1200

0 1 2 3 4 5

I

DD

− Supply Current − µA

TA = 25°C
A0 Input (All Other Inputs = GND)

VDD = 2.7 V

VDD = 5.5 V

−1

0

1

2

3

4

5

6

Time (2 µs/div)

V

OUT

− Output Voltage − V

VDD = 5 V
Powerup to Code 1000

IDD - Current Consumption - µA

0

500

1000

1500

2000

400 420 440 460 480 500 520 540 560 580 600 620

VDD = 2.7 V

Frequency

0

1

2

3

4

5

Time (25 µs/div)

V

OUT

- Output Voltage - V

VDD = 5 V

Output Loaded with

200 pF to GND

10% to 90% FSR

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Time (25 µs/div)

V

OUT

- Output Voltage - V

VDD = 2.7 V

Output Loaded with

200 pF to GND

10% to 90% FSR

TYPICAL CHARACTERISTICS (continued)

At TA= +25 ° C, unless otherwise noted.

vs LOGIC INPUT VOLTAGE OF CURRENT CONSUMPTION

DAC6573

SLAS402 – NOVEMBER 2003

SUPPLY CURRENT HISTOGRAM

Figure 19. Figure 20.

OF CURRENT CONSUMPTION POWER-DOWN MODE

HISTOGRAM EXITING

Figure 21. Figure 22.

LARGE SIGNAL LARGE SIGNAL
SETTLING TIME SETTLING TIME

Figure 23. Figure 24.

9

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−6

−2

2

6

10

14

18

0 128 256 384 512 640 768 896 1023

Channel A Output

Channel B Output

VDD = 2.7 V, TA = 25°C

Digital Input Code

Output Error − mV

Channel D Output

Channel C Output

0

4

8

12

16

20

24

0 128 256 384 512 640 768 896 1023

Channel A Output

Channel D Output

Channel B Output

Channel B Output

VDD = 5 V, TA = 25°C

Digital Input Code

Output Error − mV

DAC6573

SLAS402 – NOVEMBER 2003

TYPICAL CHARACTERISTICS (continued)

At TA= +25 ° C, unless otherwise noted.

ABSOLUTE ERROR

†

ABSOLUTE ERROR

Figure 25. Figure 26.

†

Absolute error is the deviation from ideal DAC characteristics. It includes affects of offset, gain, and integral

linearity.

†

10