DAC7571, DAC6571, DAC5571,
DAC7574, DAC6574, DAC5574,
and DAC8571 Evaluation Module
User’ s Gu ide
February 2004 Data Acquisition
About This Manual
This user’s guide describes the DAC7574, DAC6574, DAC5574, DAC7571,
DAC6571, DAC5571, and DAC8571 evaluation module. It covers the
operating procedures and characteristics of the EVM board along with the
devices that it supports.
How to Use This Manual
This document contains the following chapters:
Preface
Read This First
Chapter 1 – EVM Overview
Chapter 2 – PCB Design and Performance
Chapter 3 – EVM Operation
Information About Cautions and Warnings
This book may contain cautions and warnings.
This is an example of a caution statement.
A caution statement describes a situation that could potentially
damage your software or equipment.
This is an example of a warning statement.
A warning statement describes a situation that could potentially
cause harm to you
.
Read This First
-3
The information in a caution or a warning is provided for your protection.
Please read each caution and warning carefully.
Related Documentation From Texas Instruments
To obtain a copy of any of the following TI documents, call the Texas
Instruments Literature Response Center at (800) 477–8924 or the Product
Information Center (PIC) at (972) 644–5580. When ordering, identify this
manual by its title and literature number. Updated documents can also be
obtained through our website at www.ti.com.
Data Sheets: Literature Number:
DAC7574 SLAS375
DAC6574 SLAS408
DAC5574 SLAS407
DAC7571 SLAS374
DAC6571 SLAS406
DAC5571 SLAS405
DAC8571 SLAS373A
REF02 SBVS-003A
OPA627 PDS-998H
Questions about this or other Data Converter EVMs?
If you have questions about this or other Texas Instruments Data Converter
evaluation modules, feel free to e-mail the Data Converter Application Team
at datacnvapp
s@list.ti.com Include in the subject heading the product you
have questions or concerns with.
FCC Warning
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested
for compliance with the limits of computing devices pursuant to subpart J of
part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case
the user at his own expense will be required to take whatever measures may
be required to correct this interference.
Trademarks
I2C is a trademark of Phillips Corporation.
-4
Contents
1 EVM Overview 1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Features 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Power Requirements 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.1 Supply Voltage 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.2 Reference Voltage 1-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 EVM Basic Functions 1-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 PCB Design and Performance 2-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 PCB Layout 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 EVM Performance 2-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Bill of Materials 2-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 EVM Operation 3-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Factory Default Setting 3-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Host Processor Interface 3-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 EVM Stacking 3-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 The Output Op Amp 3-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1 Unity Gain Output (Default Configuration) 3-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 Output Gain of Two 3-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Jumper Setting 3-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Schematic 3-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
-5
Figures
1-1 EVM Block Diagram 1-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1 Top Silkscreen 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-2 Layer 1 (Top Signal Plane) 2-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-3 Layer 2 (Ground Plane) 2-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-4 Layer 3 (Power Plane) 2-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-5 Layer 4 (Bottom Signal Plane) 2-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-6 Bottom Silkscreen 2-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-7 Drill Drawing 2-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-8 DAC7574EVM Test Parameters and Results 2-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-9 INL and DNL Characterization Graph of DAC7574 Channel A 2-7 . . . . . . . . . . . . . . . . . . . . . . .
2-10 INL and DNL Charactaerization Graph of DAC7574 Channel B 2-8 . . . . . . . . . . . . . . . . . . . . .
2-11 INL and DNL Characterization Graph of DAC7574 Channel C 2-9 . . . . . . . . . . . . . . . . . . . . . .
2-12 INL and DNL Characterization Graph of DAC7574 Channel D 2-10 . . . . . . . . . . . . . . . . . . . . .
2-13 DAC8571EVM Test Parameters and Results 2-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-14 INL and DNL Characterization Graph of DAC8571 2-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
1-1 Featured DAC Selections 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1 Parts List 2-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1 DACx574EVM Factory Default Jumper Setting 3-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2 DACx571EVM Factory Default Jumper Setting 3-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3 DAC8571EVM Factory Default Jumper Setting 3-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4 DACx571 Output Channel Mapping 3-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5 DAC8571 Output Channel Mapping 3-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-6 DACx574 Output Channel Mapping 3-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-7 DACx574 I
3-8 DACx571 I2C Slave Address Map 3-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-9 DAC8571 I2C Slave Address Map 3-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-10 Unity Gain Output Jumper Settings 3-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-11 Gain of Two Output Jumper Settings 3-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-12 Jumper Setting Function 3-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-6
2
C Slave Address Map 3-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IMPORTANT NOTICE
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sale in accordance with TI’s standard warranty. Testing and other quality control techniques are
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Post Office Box 655303 Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
-8
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EVM IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR
EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use. As
such, the goods being provided may not be complete in terms of required design-, marketing-,
-9
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 0 V - V
+0.3 V and the
DD
output voltage range of ±10 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible
damage to the EVM. If there are questions concerning the input range, please contact a TI field
representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or
possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification, please
contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than
100°C. The EVM is designed to operate properly with certain components above 100°C as long
as the input and output ranges are maintained. These components include but are not limited
to linear regulators, switching transistors, pass transistors, and current sense resistors. These
types of devices can be identified using the EVM schematic located in the EVM User’s Guide.
When placing measurement probes near these devices during operation, please be aware that
these devices may be very warm to the touch.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
-10
Chapter 1
EVM Overview
This chapter provides an overview of the DAC7574, DAC6574, DAC5574,
DAC7571, DAC6571, DAC5571, and DAC8571 evaluation module (EVM),
and instructions on setting up and using this module.
Topic Page
1.1 Features 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Power Requirements 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 EVM Basic Functions 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EVM Overview
1-1
Features
1.1 Features
This EVM features the DAC7574, DAC6574, DAC5574, DAC7571, DAC6571,
DAC5571, and DAC8571 digital-to-analog converter (DAC). It provides a
quick and easy way to evaluate the functionality and performance of the
2
high-resolution as well as the low - resolution I
C-input DACs. Although the
EVM supports seven DAC types, only the selected DAC and its associated
1-2
1.2 Power Requirements
The following sections describe the power requirements of this EVM.
1.2.1 Supply Voltage
The dc power supply for the digital section (VDD) of this EVM is selected
between 3.3 V and 5 V via the 3-position jumper W14. The digital power
connects to the J5-1, J6-9, or J6-10 terminal (when plugged in with another
EVM board or interface card) and is referenced to ground through the J5-2
and J6-5 terminals. The 5 V V
W14. Therefore, if V
connected through J5-1 must be disconnected to prevent damage to the EVM
or other equipment.
Caution
T o avoid potential damage to the EVM board or equipments, make
sure that any cable connected to J5 - 1 is disconnected prior to
supplying 3.3 V V
Power Requirements
can also come directly from J5-1, bypassing
DD
must be powered by 3.3 V via J6 -9, any source
DD
via J6-9 terminal.
DD
The dc power supply requirements for the analog section of this EVM are as
follows; the VCC and VSS supplies, typically ±15 V, can range from ±4.5 V to
±18 V. V
and VSS connect through J1-3 and J1-1 respectively, or through
CC
J6 -1 and J6 -2 terminals. 5 VA connects through J5 -3 or J6 -3 and 3.3 VA
connects through J6 - 8. All of the analog power supplies are referenced to
analog ground through J1-2 and J6-6 terminals.
The analog power supply for the device under test (U1, U4, or U8) can be
provided by either 5 VA (via J5- 3 or J6- 3) or by U3 through a resistor
potentiometer, R11, by selecting the proper position of jumper W1. Although
the digital and analog supplies are separate on the EVM to allow flexibility in
supply evaluation, the supplies are treated as one, and considered analog
since the DUT does not have separate analog and digital supply pins.
The V
supply source provides the positive rail of the external output op-amp
CC
(U2) and the voltage reference (U3). The negative rail of U2 can be selected
between V
and AGND via W5 jumper. The external op-amp is installed as
SS
an option to provide output signal conditioning, or for other output
configurations.
EVM Overview
1-3
EVM Basic Functions
1.2.2 Reference Voltage
The 5-V precision voltage reference is provided to supply the external voltage
reference for the DAC8571 only through REF02, U3, via jumper TP9 by
shorting pins 1 and 2. The reference voltage goes through an adjustable 5-kΩ
potentiometer R11 in series with 0-Ω R10, to allow the user to adjust the
reference voltage.
Caution
To avoid potential damage to the EVM board, make sure that the
correct cables are connected to their respective terminals as
labeled on the EVM board.
Stresses above the maximum listed voltage ratings may cause
permanent damage to the device.
Header J4 pin 20 provides a connection point for an alternative external
reference source if desired. In this configuration the jumper on TP9 must be
removed and TP8 must be shorted. The external voltage reference must not
exceed 5 V.
The REF02 circuit also provides an alternative adjustable analog supply for
U1, U4, and U8 (whichever is installed on the EVM) through W1 pin 1 if desired.
It also provides both reference and supply voltages for U4 by shorting TP9.
Since it is possible to install all DAC devices (U1, U4 and U8) on the EVM, the
possibility of d i f ferent supply requirements may arise. To isolate the supply and
reference voltages of U4 from U1 and U8, remove R25 and install R38. This
allows the DAC8571 (U4) to operate using the REF02 (U3) as its supply and
reference sources while U1 and U8 are supplied by 5 VA.
The REF02 precision reference is powered by V
(+15V) through J1 -3 or
CC
J6-1.
1-4
EVM Basic Functions
A specific adapter interface card is also available for most of TI’s DSP Starter
Kits (DSK). The card model depends on the type of TI DSP Starter Kit to be
used. When ordering an adapter interface card, specify the DSP that will be
used.
In addition, an MSP430-based platform (HPA449) that uses the MSP430F449
microprocessor can be used with this EVM. For more information regarding
the adapter interface card or the HPA449 platform, please call Texas
Instruments Inc. or email us at dataconvapps@list.ti.com.
The DAC outputs can be monitored through selected pins of J4. The outputs
of U1 can be switched using their respective jumpers W2, W11, W12, and
W13, for stacking, while U4 or U8 uses only W2. Stacking allows a total of eight
DAC channels (if two DACx574 EVMs are stacked) or two DAC channels (if
2
two DACx571 EVM are stacked) to be used provided that the I
C address is
unique for each stacked EVM board.
Any DAC output can be connected to the noninverting input of op-amp U2 by
using a jumper across the appropriate pins of J4 (See EVM schematic
diagram). U2 must be configured correctly for the desired waveform
characteristic. (Refer to Chapter 3 of this user’s guide.)
A block diagram of the EVM is shown in Figure 1-1.
Figure 1-1.EVM Block Diagram
V
SENSE
V
H
REF
EVM Overview
1-5
1-6
PCB Design and Performance
This chapter describes the physical and mechanical characteristics of the
PCB Design and Performance
2-1
PCB Layout
2.1 PCB Layout
The DAC EVM demonstrates the high performance of the DAC under test
conditions specified in the datasheet by implementing design practices that
preserve DAC performance. Careful analysis of these practices is the key to
a successful design implementation. Many of the practices affect the
schematic design phase, including correct component selection, adequate
bypassing, separating and managing analog and digital signals, and
understanding component mechanical attributes.
The circuit layout is critical in any high-performance analog circuit, and DAC
circuit design is no exception. Component placement and signal routing are
important considerations. Place bypass capacitors as close as possible to the
pins, with analog and digital signals properly separated from each other.
The power and ground planes are very important and must be carefully
designed. A solid plane is best, but when solid planes are not possible, a split
plane is usually adequate. When considering a split plane design, analyze the
component placement and carefully divide the board into its analog and digital
sections starting from the device under test. The ground plane plays an
important role in controlling the noise and other effects that contribute to DAC
output errors. To ensure that return currents are handled properly, route the
signals only in their respective sections; analog traces must only lie directly
above or below the analog section and digital traces in the digital section.
Minimize the length of the traces but use the widest allowable trace in the
design. The EVM layout incorporates these design practices and are shown
in the illustrations presented below.
This DAC EVM board is constructed on a four-layer printed circuit board using
a copper-clad FR-4 laminate material. The printed circuit board dimensions
are 43,1800 mm (1.7000 inch) × 82,5500 mm (3.2500 inch), and the board
thickness is 1,5748 mm (0.0620 inch). Figure 2-1 through Figure 2-7 shows
the artwork for the individual layers.
Figure 2-1.Top Silkscreen
2-2
Figure 2-2.Layer 1 (Top Signal Plane)
PCB Layout
PCB Design and Performance
2-3
PCB Layout
Figure 2-5. Layer 4 (Bottom Signal Plane)
2-4
EVM Performance
2.2 EVM Performance
EVM performance is tested using a high-density DAC bench test board, an
Agilent 3458A digital multimeter, and a PC running National Instruments
LABVIEW software. The EVM board is tested for all codes of the device under
test (DUT) and is allowed to settle for 1 ms before the meter is read. This
process is repeated for all codes to generate the measurements for INL and
DNL.
The parameters and results of the DAC EVM characterization test for the
DAC7574 are shown in Figures 2- 8 through 2- 12. Test parameters and
results for the DAC8571 are shown in Figures 2-13 and 2-14.
The characterization-test data for the DAC7571, DAC6574, DAC6571,
DAC5574, and DAC5571 are not shown; it is assumed that their performance
is comparable to or better than that of the DAC7574 EVM.
Figure 2-8.DAC7574EVM Test Parameters and Results
2-6
Figure 2-9.INL and DNL Characterization Graph of DAC7574 Channel A
EVM Performance
PCB Design and Performance
2-7
EVM Performance
Figure 2-10. INL and DNL Characterization Graph of DAC7574 Channel B
2-8
Figure 2-11. INL and DNL Characterization Graph of DAC7574 Channel C
EVM Performance
PCB Design and Performance
2-9
EVM Performance
Figure 2-12. INL and DNL Characterization Graph of DAC7574 Channel D
2-10
Figure 2-13. DAC8571EVM Test Parameters and Results
EVM Performance
PCB Design and Performance
2-11
EVM Performance
Figure 2-14. INL and DNL Characterization Graph of DAC8571
2-12
Bill of Materials
2-14
Chapter 3
EVM Operation
This chapter details the operation of the EVM to guide the user in evaluating
the onboard DAC and in interfacing the EVM to a host processor.
Refer to the specific DAC data sheet, as listed in the Related Documentation
from Texas Instruments section in the Preface of this user’s guide for more in-
formation about the DAC serial interface and other related topics.
The EVM board is factory-configured to operate in the unipolar output mode.
Topic Page
3.1 Factory Default Setting 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Host Processor Interface 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 EVM Stacking 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 The Output Op Amp 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Jumper Setting 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Schematic Diagram 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EVM Operation
3-1
Factory Default Setting
3.1 Factory Default Setting
The EVM board is factory-configured to operate in unipolar 5-V output mode.
Table 3-1.DAC7574/DAC6574/DAC5574 EVM Factory Default Jumper Setting
DAC7574/DAC6574/DAC5574 EVM CONFIGURATION
Jumper
Reference
W1 2-3 Power supply for U1 is 5 VA.
W2 1-2 DAC output A (V
Position
Function
OUT
3-2
Table 3-3.DAC8571EVM Factory Default Jumper Setting
DAC8571 EVM CONFIGURATION
Jumper
Reference
W1 2-3 Power supply for the DAC8571 is 5 VA.
W2
W3 OPEN U2 is configured as unity gain op-amp.
W4 2-3 SDA is routed to SDATA..
W5 1-2 Negative supply rail of U2 op-amp is supplied with
W6 2-3 SCL is routed to SCLK.
W7 OPEN For U1 use only
W8 OPEN For U1 use only
W9 OPEN For I2C SDA bit-bang using the DSP
W10 CLOSE V
W11 1-2
W12 1-2
W13 1-2
W14 2-3 The 5 VD is routed for digital supply.
TP8 OPEN For connecting external V
TP9 OPEN For tying VDD and V
Position
1-2 DAC output is routed to J4-2.
V
SS.
is tied to V
SENSE
For U1 use only
For U1 use only
For U1 use only
U1 and U8 (if all DUTs are installed)
Host Processor Interface
Function
for feedback.
OUT
if desired
REF
together and isolating it from
REF
3.2 Host Processor Interface
Because the host processor controls the DAC, proper operation depends on
the correct interface of the host processor and the EVM board. Properly written
code is also required to operate the DAC.
A host-platform-specific cable assembly connects the EVM to the host
processor through J2 for the I
monitored through J4.
An interface-adapter card is available for specific TI DSP starter kits as well
as for an MSP430 based microprocessor as mentioned in Chapter 1, section
1.3. Using the interface card alleviates the tedious task of building custom
cables and allows easy configuration of a simple evaluation system.
This DAC EVM interfaces with any host processor capable of I2C protocols or
the popular TI DSP. For more information regarding the serial interface of the
particular DAC installed, please refer to the specific DAC datasheet, as listed
in the Related Documentation from Texas Instruments section in the Preface
of this user’s guide.
2
C serial-control and data signals. The output is
EVM Operation
3-3
EVM Stacking
3.3 EVM Stacking
EVM stacking enables the designer to evaluate two DACx574s in tandem to
yield an eight channel output, or two DACx571s, or two DAC8571s. Any
combination of the seven may be used provided the outputs do not collide. A
maximum of two DACx574 EVMs are allowed since the output terminal, J4,
dictates the number of DAC channels that can be connected without colliding.
For the DACx571 and DAC8571, more than two EVMs can be stacked
together provided the I
outputs can be monitored through TP1 instead of shorting W2 jumper and
routing the DAC output to J4. Table 4 shows how the DAC output channels are
mapped into the output terminal, J4, with respect to the jumper position of W2,
W11, W12, and W13.
Table 3-4.DAC7571/DAC6571/DAC5571 Output Channel Mapping
Jumper
Reference
W2 1-2 U8 output (V
Position
2-3 U8 output (V
2
C address of each stacked EVMs are unique, as the
Function
) is routed to J4-2.
OUT
) is routed to J4-10.
OUT
Table 3-5.DAC8571 Output Channel Mapping
Jumper
Reference
W2 1-2 U4 output (V
Position
2-3 U4 output (V
OUT
OUT
Function
) is routed to J4-2.
) is routed to J4-10.
Table 3-6.DAC7574/DAC6574/DAC5574 Output Channel Mapping
Jumper
Reference
W2 1-2 U1 output A (V
W11 1-2 U1 output B (V
W12 1-2 U1 output C (V
W13 1-2 U1 output D (V
Position
2-3 U1 output A (V
2-3 U1 output B (V
2-3 U1 output C (V
2-3 U1 output D (V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Each DAC EVM in a stacked configuration must have a unique I2C address.
This is accomplished by configuring the address jumpers W7 and W8 (refer
2
to the datasheet for I
C addressing) for the DACx574 EVM. The DACx571 and
DAC8571 use pullup and pulldown resistors R13, R22, R2, and R23
respectively. The table below shows the I
The cells shaded in gray are factory preset and cannot be changed.
Function
A) is routed to J4-2.
A) is routed to J4-10.
B) is routed to J4-4.
B) is routed to J4-12.
C) is routed to J4-6.
C) is routed to J4-14.
D) is routed to J4-8.
D) is routed to J4-16.
2
C address settings of each EVM.
3-4
Table 3-7.DAC7574/DAC6574/DAC5574 I2C Slave Address Map
The Output Op Amp
Factory Set I2C Address W7 W8 R/W
I2C Address and
Function
EVM Operation
3-5
The Output Op Amp
easy access for monitoring up to eight DAC channels when stacking two
DACx574 EVMs together, as described in section 3.3.
The inverting input of U2 can be tied to AGND or to any voltage source through
TP2, which is selectable by the jumper configuration of W3. The voltage
source connected to TP2 is adjustable via potentiometer R14.
The following sections describe various configurations of the output amplifier,
U2.
3.4.1 Unity Gain Output (Default Configuration)
The buffered output configuration can be used to prevent loading the DAC.
However, it may present some slight distortion because of the feedback
resistor and capacitor . The user can tailor the feedback circuit to closely match
their desired wave shape by simply removing R7 and C11 and replacing them
with the desired values. R7 can be replaced with a zero-ohm resistor and C1 1
can be left open if desired.
Table 3-10 shows the jumper settings for the unity gain configuration of the
output buffer in unipolar or bipolar supply mode.
Table 3-10.Unity Gain Output Jumper Settings
Reference
W3 Open Open
W5 2-3 1-2
Jumper Setting
Unipolar Bipolar
3.4.2 Output Gain of Two
Table 3-11 shows the proper jumper settings of the EVM for the 2× gain output
of the DAC.
Table 3-11.Gain of Two Output Jumper Settings
Reference
W3 1-2 1-2
W5 2-3 1-2
Jumper Setting
Unipolar Bipolar
Function
Disconnects TP2 input or AGND from the inverting input of the op-amp
Supplies VSS to the negative rail of op-amp or
ties it to AGND
Function
Inverting input of the output op-amp, U2, is
connected to AGND to set for a gain of 2.
Supplies power, VSS, to the negative rail of
op-amp, U2, for bipolar supply mode, or ties
it to AGND for unipolar supply mode
3-6
3.5 Jumper Setting
Table 3-12 shows the function of each specific jumper setting of the EVM.
Table 3-12.Jumper Setting Function
Jumper Setting
Reference
W1
Jumper
Setting
1 3
1
Function
5-V analog supply is selected for AVDD.
EVM Operation
3-7
Jumper Setting
Reference Function
Jumper
Setting
U4 V
pin is disconnected to its V
SENSE
OUT
pin.
W10
W11
W12
W13
1 3
1 3
1 3
1 3
1 3
1 3
1 3
U4 V
Routes V
Routes V
Routes V
Routes V
Routes V
Routes V
Connects 3.3 VD to VDD for digital supply.847 4624.64 463.861eW 344.8069 261. 490.62 l92.208 l146.438 l4 467.15 63.861 l1fB2.154 w 901 -0.397 r5.222 l 344.80699 l1l13.0264 0.397 -27.893 reET74.041 513.071 0.9074146267 refBT8.1 0 0 8.1 134.14492.4 l130.224 41403967 m133.6251403967 m133.62531.4912 l161.80231.4912 l1 134.1l1348162 l133.625 44492.4 l130.224 41403967 m133.6251403967 m133.62531.4912 l161.80231.4912 l1 134.1l1348162 l133.625 487.1395130.224 490.1331361 l137.0831399458 l138.386 550422 l139.0116 550422 l139.2381399458 l139.8611331361 l138.387139518 l139.861138.666 l136.461359518 l139.011138.818 l138.38138.818 l137.0831359518 l24 490.138.666l135.666 492.208 l134.9294146267 refBT8.1 0 0 8.1 152.7874 51675792 Tm(3)TjET2.154 w 141.506 489.41395130.145.4741331361 l146.0981399458 l147.4026 550422 l147.9696 550422 l148.2521399458 l147.9691331361 l147.402139518 l147.969138.666 148.2521359518 l147.969138.818 l147.402138.818 l146.0981359518 l145.474138.666l144.624 491395130.154.4881331361 l155.0551399458 l156.4166 550422 l156.9836 550422 l157.2091399458 l157.8331331361 l156.416139518 l157.833138.666 157.2091359518 l156.983138.818 l156.416138.818 l155.0551359518 l154.488138.666l14*127.84l13.0264igital su7.893 re4*127.84l13.0235 0.397 -27.836 ref127.843 485.235 441365951397 refBT9 0 0 9 176.54 467.4897 Tm-0.0003 Tc(Connects 3.3 VD to l13.0264igital su7.893 re 4624.64 l13.0264 0.397 -27.893 re.3 VD to l13.0271 0.907 -27.836 ref172.743 m0..41 344.806 -34907 refq74.551 462901 490.03365951397 r5.22TP89 0 0 9 91.7291 213061eW 344.1.l14)TjETQ74.0213061235 0.907 -27.836 r0 0 821.8741046.7.45.5663 3157.6836 * 821.8741046.7.45.5663 3157.6836Sl133.635 .9831901 7 l130.968022 T4518 l247.25219 46718 l134965219 64118 l138.3819 64118 l139.01119 46718 l Tm.1752 T4518 l147.4021901 7 8 l Tm.17526242318 l139.0111137.861 l138.381.201918 l13496521.201918 l247.2521137.861 l0.9680226242318 l144469.4161901 7 l1446.0232 T4518 l14661119 46718 l1 0743 m9 64118 l147.402m9 64118 l147.96919 46718 l113908022 T4518 l1132.4161901 7 8 l1139080226242318 l147.9691137.861 l147.402m.201918 l1 0743 m.201918 l11466111137.861 l46.02326242318 l14*127.84213061eigital1.l14
pin is connected to its V
SENSE
B to J4-4
OUT
B to J4-12
OUT
C to J4-6
OUT
C to J4-14
OUT
D to J4-8
OUT
D to J4-16
OUT
OUT
pin.
3-8
3.6 Schematic
Schematic
The schematic diagram follows this page.
EVM Operation
3-9
1 2 3 4 56
A
B
C
D
6
54321
D
C
B
A
ti
12500 TI Boulevard. Dallas, Texas 75243
Title:
SHEET: OF:
FILE: SIZE:
DATE:
REV:
12-Feb-2004
Drawn By:
Engineer:
Revision History
REV ECN Number Approved
DAC7574 Rev A.Sch
DOCUMENTCONTROL #
C1
0.1µF
+5VA
SCLK
R6
10K
VSS
2
3
6
4
71
5
U2
Op Amp
VCC
C10
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