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Resistor
Network
8
14
Data
Buffer A
DAC
Register A
Data
Buffer D
DAC
Register D
DAC A
DAC D
Buffer
Control
Register
Control
Power-Down
Control Logic
V
OUT
A
V
OUT
B
V
OUT
C
V
OUT
D
A0 A1 GND
I2C
Block
SCL
SDA
V
DD
QUAD, 8-BIT, LOW-POWER, VOLTAGE OUTPUT,
I2C INTERFACE DIGITAL-TO-ANALOG CONVERTER
FEATURES DESCRIPTION
• Micropower Operation: 500 µA at 3 V V
• Fast Update Rate: 188 kSPS
• Per-channel Power-down Capability
• Power-On Reset to Zero
• 2.7-V to 5.5-V Analog Power Supply
• 8-bit Monotonic
• I2C™ Interface Up to 3.4 Mbps
• Data Transmit Capability
• On-Chip Output Buffer Amplifier, Rail-to-Rail
Operation
• Double-Buffered Input Register
• Address Support for up to Four DAC5574s
• Synchronous Update Support for up to 16
Channels
• Operation From –40 ° C to 105 ° C
• Small 10 Lead MSOP Package
APPLICATIONS
• Process Control
• Data Acquisition Systems
• Closed-Loop Servo Control
• PC Peripherals
• Portable Instrumentation
DAC5574
SLAS407 – DECEMBER 2003
DD
The DAC5574 is a low-power, quad channel, 8-bit
buffered voltage output DAC. Its on-chip precision
output amplifier allows rail-to-rail output swing to be
achieved. The DAC5574 utilizes an I2C compatible
two wire serial interface supporting high-speed
interface mode with address support of up to four
DAC5574s for a total of 16 channels on the bus.
The DAC5574 uses V
and GND to set the output
DD
range of the DAC. The DAC5574 incorporates a
power-on-reset circuit that ensures that the DAC
output powers up at zero volts and remains there until
a valid write takes place to the device. The DAC5574
contains a per-channel power-down feature, accessed via the internal control register, reducing the
current consumption of the device to 200 nA at 5 V.
The low power consumption of this part in normal
operation makes it ideally suited to portable battery
operated equipment. The power consumption is less
than 3mW at V
= 5 V reducing to 1 µW in
DD
power-down mode.
TI offers a variety of data converters with I2C
interface. See DACx57x family of 16/12/10/8 bit,
single and quad channel DACs. Also see ADS7823
and ADS1100, 12-bit octal channel and 16-bit single
channel ADCs.
I2C is a trademark of Philips Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2003, Texas Instruments Incorporated
www.ti.com
A1
A0
1
2
3
4
5 6
7
8
10
9
V
OUT
A
V
OUT
B
GND
V
OUT
C
V
OUT
D
V
DD
SDA
SCL
DAC5574
.
DAC5574
SLAS407 – DECEMBER 2003
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT PACKAGE PACKAGE SPECIFICATION PACKAGE ORDERING TRANSPORT MEDIA
DAC5574 10-MSOP DGS –40 °C TO +105 °C D574 DAC5574IDGS 80 Piece Tube
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com .
DGS PACKAGE
DRAWING TEMPERATURE MARKING NUMBER
NUMBER RANGE
(TOPVIEW)
PIN NAME DESCRIPTION
1 V
OUT
2 V
OUT
3 GND
4 V
OUT
5 V
OUT
6 SCL Serial clock input
7 SDA Serial data input and output
8 V
9 A0 Device address select - I2C
10 A1 Device address select - I2C
(1)
DAC5574IDGSR 2500 Piece Tape and Reel
PIN DESCRIPTIONS
A Analog output voltage from DAC A
B Analog output voltage from DAC B
Ground reference point for all circuitry on the
part
C Analog output voltage from DAC C
D Analog output voltage from DAC D
Analog voltage supply input
DD
ABSOLUTE MAXIMUM RATINGS
V
to GND –0.3 V to +6 V
DD
Digital input voltage to GND –0.3 V to V
V
OUT
Operating temperature range –40 °C to +105 °C
Storage temperature range –65 °C to +150 °C
Junction temperature range (T
Power dissipation: Thermal impedance ( ΘJA) 270 °C/W
Lead temperature, soldering: Vapor phase (60s) 215 °C
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2
(1)
to GND –0.3 V to V
max) +150 °C
J
Thermal impedance ( ΘJC) 77 °C/W
Infrared (15s) 220 °C
+ 0.3 V
DD
+ 0.3 V
DD
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DAC5574
SLAS407 – DECEMBER 2003
ELECTRICAL CHARACTERISTICS
V
= 2.7 V to 5.5 V, RL= 2 k Ω to GND; CL= 200 pF to GND; all specifications –40 ° C to +105 ° C, unless otherwise specified.
DD
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
STATIC PERFORMANCE
Resolution 8 Bits
Relative accuracy ± 0.15 ± 0.5 LSB
Differential nonlinearity Specified monotonic by design ± 0.02 ± 0.25 LSB
Zero-scale error 5 20 mV
Full-scale error -0.15 ± 1.0 % of FSR
Gain error ± 1.0 % of FSR
Zero code error drift ± 7 µV/ °C
Gain temperature coefficient ± 3 ppm of
OUTPUT CHARACTERISTICS
Output voltage range 0 V
Output voltage settling time (full scale) RL= ∞ ; 0 pF < CL< 200 pF 6 8 µs
Slew rate 1 V/ µs
dc crosstalk (channel-to-channel) 0.0025 LSB
ac crosstalk (channel-to-channel) 1 kHz Sine Wave -100 dB
Capacitive load stability RL= ∞ 470 pF
Digital-to-analog glitch impulse 1 LSB change around major carry 12 nV-s
Digital feedthrough 0.3 nV-s
dc output impedance 1 Ω
Short-circuit current VDD= 5 V 50 mA
Power-up time Coming out of power-down mode, 2.5 µs
LOGIC INPUTS
(2)
Input current ± 1 µA
V
, Input low voltage 0.3xV
IN_L
V
, Input high voltage VDD= 3 V 0.7xV
IN_H
Pin Capacitance 3 pF
POWER REQUIREMENTS
V
DD
IDD(normal operation), including reference current Excluding load current
IDD@ VDD=+3.6V to +5.5V VIH= V
IDD@ V
IDD(all power-down modes)
IDD@ VDD=+3.6V to +5.5V VIH= V
IDD@ V
POWER EFFICIENCY
I
/I
OUT
DD
TEMPERATURE RANGE
Specified performance -40 +105 °C
(1) Linearity tested using a reduced code range of 48 to 4047; output unloaded.
(2) Specified by design and characterization, not production tested.
(1)
(2)
Coming out of power-down mode, 5 µs
=+2.7V to +3.6V VIH= V
DD
=+2.7V to +3.6V VIH= V
DD
DD
RL= ∞ ; CL= 500 pF 12 µs
RL= 2 k Ω 1000 pF
VDD= 3 V 20 mA
VDD= +5 V
VDD= +3 V
DD
DD
2.7 5.5 V
and VIL=GND 600 900 µA
DD
and VIL=GND 500 750 µA
DD
and VIL=GND 0.2 1 µA
DD
and VIL=GND 0.05 1 µA
DD
I
= 2 mA, VDD= +5 V 93%
LOAD
FSR/ °C
V
V
V
3
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DAC5574
SLAS407 – DECEMBER 2003
TIMING CHARACTERISTICS
V
= 2.7 V to 5.5 V, RL= 2 k Ω to GND; all specifications –40 ° C to +105 ° C, unless otherwise specified.
DD
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Standard mode 100 kHz
Fast mode 400 kHz
Standard mode 4.7 µs
Fast mode 1.3 µs
Standard mode 4.0 µs
Fast mode 600 ns
High-speed mode 160 ns
Standard mode 4.7 µs
Fast mode 1.3 µs
Standard mode 4.0 µs
Fast mode 600 ns
Standard mode 4.7 µs
Fast mode 600 ns
High-speed mode 160 ns
Standard mode 250 ns
High-speed mode 10 ns
Standard mode 0 3.45 µs
Fast mode 0 0.9 µs
Standard mode 1000 ns
Fast mode 20 + 0.1C
B
Standard mode 1000 ns
Fast mode 20 + 0.1C
B
Standard mode 300 ns
Fast mode 20 + 0.1C
B
Standard mode 1000 ns
Fast mode 20 + 0.1C
B
tHD; t
tSU; t
tSU; t
tHD; t
f
SCL
SCL clock frequency
High-Speed Mode, CB= 100 pF max 3.4 MHz
High-speed mode, CB= 400 pF max 1.7 MHz
t
BUF
STA
t
LOW
Bus free time between a
STOP and START condition
Hold time (repeated) START
condition
LOW period of the SCL clock
High-speed mode, CB= 100 pF max 160 ns
High-speed mode, CB= 400 pF max 320 ns
t
HIGH
HIGH period of the SCL clock
High-Speed Mode, CB= 100 pF max 60 ns
High-speed mode, CB= 400 pF max 120 ns
STA
DAT
DAT
Setup time for a repeated
START condition
Data setup time Fast mode 100 ns
Data hold time
High-speed mode, CB= 100 pF max 0 70 ns
High-speed mode, CB= 400 pF max 0 150 ns
t
RCL
Rise time of SCL signal
High-speed mode, CB= 100 pF max 10 40 ns
High-speed mode, CB= 400 pF max 20 80 ns
Rise time of SCL signal after
t
RCL1
t
FCL
a repeated START condition
and after an acknowledge
Fall time of SCL signal
BIT
High-speed mode, CB= 100 pF max 10 80 ns
High-speed mode, CB= 400 pF max 20 160 ns
High-speed mode, CB= 100 pF max 10 40 ns
High-speed mode, CB= 400 pF max 20 80 ns
t
RDA
Rise time of SDA signal
High-speed mode, CB= 100 pF max 10 80 ns
High-speed mode, CB= 400 pF max 20 160 ns
300 ns
300 ns
300 ns
300 ns
4
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−1
−0.5
0
0.5
1
−0.5
−0.25
0
0.25
0.5
0 32 64 96 128 160 192 224
Digital Input Code
Channel AChannel A VDD = 5 V
255
LE − LSBDLE − LSB
−1
−0.5
0
0.5
1
−0.5
−0.25
0
0.25
0.5
0 32 64 96 128 160 192 224
Digital Input Code
Channel B VDD = 5 V
255
LE − LSBDLE − LSB
TIMING CHARACTERISTICS (continued)
V
= 2.7 V to 5.5 V, RL= 2 k Ω to GND; all specifications –40 ° C to +105 ° C, unless otherwise specified.
DD
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Standard mode 300 ns
tSU; t
t
FDA
Fall time of SDA signal
High-speed mode, CB= 100 pF max 10 80 ns
Fast mode 20 + 0.1C
High-speed mode, CB= 400 pF max 20 160 ns
Standard mode 4.0 µs
STO
Setup time for STOP con-
dition
Fast mode 600 ns
High-speed mode 160 ns
C
B
t
SP
V
NH
V
NL
Capacitive load for SDA and
SCL
Pulse width of spike sup-
pressed
Noise margin at the HIGH
Fast mode 50 ns
High-speed mode 10 ns
Standard mode
level for each connected de- Fast mode 0.2 V
vice (including hysteresis)
Noise margin at the LOW
High-speed mode
Standard mode
level for each connected de- Fast mode 0.1 V
vice (including hysteresis)
High-speed mode
B
DD
DD
DAC5574
SLAS407 – DECEMBER 2003
300 ns
400 pF
V
V
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR vs DIGITAL INPUT CODE
TYPICAL CHARACTERISTICS
At TA= +25 ° C, unless otherwise noted.
Figure 1. Figure 2.
5
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−1
−0.5
0
0.5
1
LE − LSB
−0.5
−0.25
0
0.25
0.5
0 32 64 96 128 160 192 224
Digital Input Code
DLE − LSB
255
Channel D
VDD = 5 V
−1
−0.5
0
0.5
1
LE − LSB
−0.5
−0.25
0
0.25
0.5
0 32 64 96 128 160 192 224
Digital Input Code
DLE − LSB
255
Channel C VDD = 5 V
−1
−0.5
0
0.5
1
−0.5
−0.25
0
0.25
0.5
0 32 64 96 128 160 192 224
Digital Input Code
255
LE − LSBDLE − LSB
Channel A
VDD = 2.7 V
−1
−0.5
0
0.5
1
LE − LSB
−0.5
−0.25
0
0.25
0.5
0 32 64 96 128 160 192 224
Digital Input Code
DLE − LSB
255
Channel B
VDD = 2.7 V
−1
−0.5
0
0.5
1
−0.5
−0.25
0
0.25
0.5
0 32 64 96 128 160 192 224
Digital Input Code
255
LE − LSBDLE − LSB
Channel D
VDD = 2.7 V
−1
−0.5
0
0.5
1
−0.5
−0.25
0
0.25
0.5
0 32 64 96 128 160 192 224
Digital Input Code
255
LE − LSBDLE − LSB
Channel C
VDD = 2.7 V
DAC5574
SLAS407 – DECEMBER 2003
TYPICAL CHARACTERISTICS (continued)
At TA= +25 ° C, unless otherwise noted.
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR vs DIGITAL INPUT CODE
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR vs DIGITAL INPUT CODE
Figure 3. Figure 4.
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR vs DIGITAL INPUT CODE
6
Figure 5. Figure 6.
Figure 7. Figure 8.
www.ti.com
5
10
15
20
−40 −10 20 50 80
TA − Free−Air T emperature − °C
Zero-Scale Error − mV
VDD = 5 V
CH A
CH B
CH C
CH D
0
5
10
15
−40 −10 20 50 80
TA − Free−Air T emperature − °C
Zero-Scale Error − mV
VDD = 2.7 V
CH A
CH B
CH C
CH D
0
5
10
15
20
25
30
−40 −10 20 50 80
CH A
CH B
CH D
T
A
− Free−Air T emperature − °C
Full-Scale Error − mV
VDD = 5 V
CH C
0
5
10
15
20
−40 −10 20 50 80
TA − Free−Air T emperature − °C
Full-Scale Error − mV
VDD = 2.7 V
CH A
CH B
CH C
CH D
0.000
0.025
0.050
0.075
0.100
0.125
0.150
0 1 2 3 4 5
I
SINK
− Sink Current − mA
V
OUT
− Output Voltage − V
VDD = 2.7 V
VDD = 5.5 V
DAC Loaded With 00
H
Typical For All Channels
5.30
5.35
5.40
5.45
5.50
0 1 2 3 4 5
I
SOURCE
− Source Current − mA
V
OUT
− Output Voltage − V
DAC Loaded With FF
H
VDD = 5.5 V
Typical For All Channels
TYPICAL CHARACTERISTICS (continued)
At TA= +25 ° C, unless otherwise noted.
ZERO-SCALE ERROR ZERO-SCALE ERROR
FULL-SCALE ERROR FULL-SCALE ERROR
DAC5574
SLAS407 – DECEMBER 2003
vs TEMPERATURE vs TEMPERATURE
Figure 9. Figure 10.
vs TEMPERATURE vs TEMPERATURE
Figure 11. Figure 12.
SINK CURRENT CAPABILITY SOURCE CURRENT CAPABILITY
AT NEGATIVE RAIL AT POSITIVE RAIL
Figure 13. Figure 14.
7
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2.3
2.4
2.5
2.6
2.7
0 1 2 3 4 5
I
SOURCE
− Source Current − mA
V
OUT
− Output Voltage − V
DAC Loaded With FF
H
VDD = 2.7 V
Typical For All Channels
Digital Input Code
0
100
200
300
400
500
600
700
800
0 32 64 96 128 160 192 224
I
DD
− Supply Current − µA
VDD = 2.7 V
VDD = 5.5 V
All Channels Powered, No Load
255
TA − Free−Air T emperature − °C
0
100
200
300
400
500
600
700
−40 −10 20 50 80 110
I
DD
− Supply Current − µA
VDD = 2.7 V
VDD = 5.5 V
All Channels Powered, No Load
VDD − Supply Voltage − V
200
250
300
350
400
450
500
550
600
650
700
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
I
DD
− Supply Current − µA
All DACs Powered, No Load
IDD − Current Consumption − µA
0
500
1000
1500
2000
500 520 540 560 580 600 620 640 660 680 700 720 740
VDD = 5 V
Frequency
V
Logic
− Logic Input Voltage − V
200
400
600
800
1000
1200
0 1 2 3 4 5
I
DD
− Supply Current − µA
TA = 25°C
A0 Input (All Other Inputs = GND)
VDD = 2.7 V
VDD = 5.5 V
DAC5574
SLAS407 – DECEMBER 2003
TYPICAL CHARACTERISTICS (continued)
At TA= +25 ° C, unless otherwise noted.
SOURCE CURRENT CAPABILITY SUPPLY CURRENT
AT POSITIVE RAIL vs DIGITAL INPUT CODE
Figure 15. Figure 16.
SUPPLY CURRENT SUPPLY CURRENT
vs TEMPERATURE vs SUPPLY VOLTAGE
SUPPLY CURRENT HISTOGRAM
vs LOGIC INPUT VOLTAGE OF CURRENT CONSUMPTION
8
Figure 17. Figure 18.
Figure 19. Figure 20.
www.ti.com
−1
0
1
2
3
4
5
6
Time (2 µs/div)
V
OUT
− Output Voltage − V
VDD = 5 V
Powerup to Code 250
IDD − Current Consumption − µA
0
500
1000
1500
2000
400 420 440 460 480 500 520 540 560 580 600 620
VDD = 2.7 V
Frequency
0
1
2
3
4
5
Time (25 µs/div)
V
OUT
− Output Voltage − V
VDD = 5 V
Output Loaded with
200 pF to GND
10% to 90% FSR
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Time (25 µs/div)
V
OUT
− Output Voltage − V
VDD = 2.7 V
Output Loaded with
200 pF to GND
10% to 90% FSR
0
4
8
12
16
20
24
0 32 64 96 128 160 192 224
Digital Input Code
Output Error (mV)
255
Channel A Output
Channel D Output
Channel B Output
Channel C Output
VDD = 5 V, TA = 25°C
−6
−2
2
6
10
14
18
0 32 64 96 128 160 192 224 255
Channel A Output
VDD = 2.7 V, TA = 25°C
Channel D Output
Channel C Output
Channel B Output
Digital Input Code
Output Error (mV)
TYPICAL CHARACTERISTICS (continued)
At TA= +25 ° C, unless otherwise noted.
DAC5574
SLAS407 – DECEMBER 2003
OF CURRENT CONSUMPTION POWER-DOWN MODE
HISTOGRAM EXITING
Figure 21. Figure 22.
LARGE SIGNAL LARGE SIGNAL
SETTLING TIME SETTLING TIME
ABSOLUTE ERROR
†
linearity.
Absolute error is the deviation from ideal DAC characteristics. It includes affects of offset, gain, and integral
Figure 23. Figure 24.
†
ABSOLUTE ERROR
Figure 25. Figure 26.
†
9
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_ +Resistor String
Ref+
Ref-
DAC Register
V
OUT
50 k 50 k
V
DD
GND
70 k
OUT
V
DD
D
256
V
DD
To Output
Amplifier
R
R R
R
GND
DAC5574
SLAS407 – DECEMBER 2003
THEORY OF OPERATION
D/A SECTION
The architecture of the DAC5574 consists of a string DAC followed by an output buffer amplifier. Figure 27
shows a generalized block diagram of the DAC architecture.
Figure 27. R-String DAC Architecture
The input coding to the DAC5574 is unsigned binary, which gives the ideal output voltage as:
Where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 255.
RESISTOR STRING
The resistor string section is shown in Figure 28 . It is basically a divide-by-2 resistor, followed by a string of
resistors, each of value R. The code loaded into the DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the
amplifier. Because the architecture consists of a string of resistors, it is specified monotonic.
Figure 28. Typical Resistor String
Output Amplifier
The output buffer is a gain-of-2 noninverting amplifiers, capable of generating rail-to-rail voltages on its output,
which gives an output range of 0V to V
. It is capable of driving a load of 2 k Ω in parallel with 1000 pF to GND.
DD
The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is 1 V/ µs
with a half-scale settling time of 6 µs with the output unloaded.
I2C Interface
I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus
is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through
open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor,
controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also
generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or
transmits data on the bus under control of the master device.
10
www.ti.com
Start
Condition
SDA
Stop
Condition
SDA
SCL
S P
SCL
DAC5574
SLAS407 – DECEMBER 2003
THEORY OF OPERATION (continued)
The DAC5574 works as a slave and supports the following data transfer modes, as defined in the I2C-Bus
Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (3.4 Mbps). The data
transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/S-mode in
this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as
H/S-mode. The DAC5574 supports 7-bit addressing; 10-bit addressing and general call address are not
supported.
F/S-Mode Protocol
• The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 29 . All I2C-compatible devices should
recognize a start condition.
• The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit
R/ W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 30 ). All devices
recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave
device with a matching address generates an acknowledge (see Figure 31 ) by pulling the SDA line low
during the entire high period of the 9
communication link with a slave has been established.
• The master generates further SCL cycles to either transmit data to the slave (R/ W bit 1) or receive data from
the slave (R/ W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary.
• To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 29 ). This releases the bus and stops the communication link
with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and they wait for a start condition followed by a
matching address.
th
SCL cycle. Upon detecting this acknowledge, the master knows that
H/S-Mode Protocol
• When the bus is idle, both SDA and SCL lines are pulled high by the pullup devices.
• The master generates a start condition followed by a valid serial byte containing H/S master code
00001XXX. This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to
acknowledge the H/S master code, but all devices must recognize it and switch their internal setting to
support 3.4 Mbps operation.
• The master then generates a repeated start condition (a repeated start condition has the same timing as the
start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that
transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the H/S-mode and switches all the
internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated
start conditions should be used to secure the bus in H/S-mode.
Figure 29. START and STOP Conditions
11
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Change of Data Allowed
Data Line
Stable;
Data Valid
SDA
SCL
Not Acknowledge
Acknowledge
1 2 8 9
Clock Pulse for
Acknowledgement
S
START
Condition
Data Output
by Transmitter
Data Output
by Receiver
SCL From
Master
Recognize START or
REPEATED START
Condition
Recognize STOP or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
Acknowledgement
Signal From Slave
SDA
SCL
MSB
P
Sr
Sr
or
P
S
or
Sr
START or
Repeated START
Condition
STOP or
Repeated START
Condition
Clock Line Held Low While
Interrupts are Serviced
1 2 7 8 9
ACK
1 2 3 - 8 9
ACK
Address
R/W
DAC5574
SLAS407 – DECEMBER 2003
THEORY OF OPERATION (continued)
Figure 30. Bit Transfer on the I2C Bus
12
Figure 31. Acknowledge on the I2C Bus
Figure 32. Bus Protocol
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DAC5574
SLAS407 – DECEMBER 2003
DAC5574 I2C Update Sequence
The DAC5574 requires a start condition, a valid I2C address, a control byte, an MSB byte, and an LSB byte for a
single update. After the receipt of each byte, DAC5574 acknowledges by pulling the SDA line low during the high
period of a single clock pulse. A valid I2C address selects the DAC5574. The control byte sets the operational
mode of the selected DAC5574. Once the operational mode is selected by the control byte, DAC5574 expects an
MSB byte followed by an LSB byte for data update to occur. DAC5574 performs an update on the falling edge of
the acknowledge signal that follows the LSB byte.
Control byte needs not to be resent until a change in operational mode is required. The bits of the control byte
continuously determine the type of update performed. Thus, for the first update, DAC5574 requires a start
condition, a valid I2C address, a control byte, an MSB byte and an LSB byte. For all consecutive updates,
DAC5574 needs an MSB byte and an LSB byte as long as the control command remains the same.
Using the I2C high-speed mode (f
the first update can be done within 18 clock cycles (MSB byte, acknowledge signal, LSB byte, acknowledge
signal), at 188.88 KSPS. Using the fast mode (f
rate is limited to 22.22 KSPS. Once a stop condition is received DAC5574 releases the I2C bus and awaits a new
start condition.
Address Byte
MSB LSB
1 0 0 1 1 A1 A0 R/ W
= 3.4 MHz), the clock running at 3.4 MHz, each 8-bit DAC update other than
scl
= 400 kHz), clock running at 400 kHz, maximum DAC update
scl
The address byte is the first byte received following the START condition from the master device. The first five
bits (MSBs) of the address are factory preset to 10011. The next two bits of the address are the device select
bits A1 and A0. The A1, A0 address inputs can be connected to V
or digital GND, or can be actively driven by
DD
TTL/CMOS logic levels. The device address is set by the state of these pins during the power-up sequence of
the DAC5574. Up to 4 devices (DAC5574) can still be connected to the same I2C-Bus.
Broadcast Address Byte
MSB LSB
1 0 0 1 0 0 0 0
Broadcast addressing is also supported by DAC5574. Broadcast addressing can be used for synchronously
updating or powering down multiple DAC5574 devices. DAC5574 is designed to work with other members of the
DAC857x and DAC757x families to support multichannel synchronous update. Using the broadcast address,
DAC5574 responds regardless of the states of the address pins. Broadcast is supported only in write mode
(Master writes to DAC5574).
13
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DAC5574
SLAS407 – DECEMBER 2003
Control Byte
MSB LSB
0 0 L1 L0 X Sel1 Sel0 PD0
Table 1. Control Register Bit Descriptions
Bit Name Bit Number/Description
L1 Load1 (Mode Select) Bit
L2 Load0 (Mode Select) Bit
00 Store I2C data. The contents of MS-BYTE and LS-BYTE (or power down information) are stored in the
temporary register of a selected channel. This mode does not change the DAC output of the selected
channel.
01 Update selected DAC with I2C data. Most commonly utilized mode. The contents of MS-BYTE and
LS-BYTE (or power down information) are stored in the temporary register and in the DAC register of
the selected channel. This mode changes the DAC output of the selected channel with the new data.
10 4-Channel synchronous update. The contents of MS-BYTE and LS-BYTE (or power down information)
are stored in the temporary register and in the DAC register of the selected channel. Simultaneously,
the other three channels get updated with previously stored data from the temporary register. This
mode updates all four channels together.
11 Broadcast update mode. This mode has two functions. In broadcast mode, DAC5574 responds
regardless of local address matching, and channel selection becomes irrelevant as all channels update.
This mode is intended to enable up to 16 channels simultaneous update, if used with the I2C broadcast
address (1001 0000).
If Sel1=0 All four channels are updated with the contents of their temporary register
If Sel1=1 All four channels are updated with the MS-BYTE and LS-BYTE data or
Sel1 Buff Sel1 Bit
Sel0 Buff Sel0 Bit
00 Channel A
01 Channel B
10 Channel C
11 Channel D
PD0 Power Down Flag
0 Normal operation
1 Power-down flag (MSB7 and MSB6 indicate a power-down operation, as shown in Table 2 ).
Are used for selecting the update mode.
data.
powerdown.
Channel Select Bits
14
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SLAS407 – DECEMBER 2003
Table 2. Control Byte
C7 C6 C5 C4 C3 C2 C1 C0 MSB7 MSB6 MSB5...
0 0 Load1 Load0 Ch Sel 1 Ch Sel 0 PD0
(Address
Select)
0 0 X 0 0 0 Data register A (TRA) with
0 0 X 0 1 0 Data register B (TRB) with
0 0 X 1 0 0 Data register C (TRC) with
0 0 X 1 1 0 Data register D (TRD) with
0 0 X 1 see Table 8 0
0 1 X 0 Data by C2 &C1 and load
0 1 X 1 see Table 8 0 (selected by C2 and
1 0 X 0 Data by C2 &C1 w/ data and
1 0 X 1 see Table 8 0 (selected by C2 and
Broadcast Modes (controls up to 4 devices on a single serial bus)
X X 1 1 X 0 X X X devices with previously
X X 1 1 X 1 X 0 Data devices with MSB[7:0]
X X 1 1 X 1 X 1 see Table 8 0
Don't MSB MSB-1 MSB-2
Care (PD1) (PD2) ...LSB DESCRIPTION
Write to temporary
data
Write to temporary
data
Write to temporary
data
Write to temporary
data
(00, 01, 10, or 11) Write to TRx (selected
by C2 &C1
w/Powerdown Command
(00, 01, 10, or 11) Write to TRx (selected
DACx w/data
(00, 01, 10, or 11) Power-down DACx
C1)
(00, 01, 10, or 11) Write to TRx (selected
load all DACs
(00, 01, 10, or 11) Power-down DACx
C1) & load all DACs
Update all DACs, all
stored TRx data
Update all DACs, all
and LSB[7:0] data
Power-down all DACs,
all devices
DAC5574
Most Significant Byte
Most significant byte MSB[7:0] consists of eight most significant bits of 8-bit unsigned binary D/A conversion
data. If C0=1, MSB[7], MSB[6] indicate a powerdown operation as shown in Table 8 .
Least Significant Byte
Least significant byte LSB[7:0] consists of 8 don't care bits. DAC5574 updates at the falling edge of the
acknowledge signal that follows the LSB[0] bit. Therefore, LSB [7:0] is needed for the update to occur.
Default Readback Condition
If the user initiates a readback of a specified channel without first writing data to that specified channel, the
default readback is all zeros, since the readback register is initialized to 0 during the power on reset phase.
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SLAVE ADDRESS R/W A Ctrl-Byte A MS-Byte A LS-Byte A/A P
0 (write)
Data Transferred
(n* Words + Acknowledge)
Word = 16 Bit
From Master to DAC5574
From DAC5574 to Master
A = Acknowledge (SDA LOW)
A = Not Acknowledge (SDA HIGH)
S = START Condition
Sr = Repeated START Condition
P = STOP Condition
DAC5574 I2C-SLAVE ADDRESS:
1 0 0 1 1 A1 A0 R/W
MSB LSB
Factory Preset
A0 = I2C Address Pin
A1 = I2C Address Pin
S
0 = Write to DAC5574
1 = Read from DAC5574
DAC5574
SLAS407 – DECEMBER 2003
DAC5574 Registers
Table 3. DAC5574 Architecture Register Descriptions
REGISTER DESCRIPTION
CTRL[7:0] Stores 8-bit wide control byte sent by the master
MSB[7:0] Stores the 8 most significant bits of unsigned binary data sent by the master. Can also store 2-bit power-down data.
TRA[9:0], TRB[9:0], 10-bit temporary storage registers assigned to each channel. Two MSBs store power-down information, 8 LSBs
TRC[9:0], TRD[9:0] store data.
DRA[9:0], DRB[9:0], 10-bit DAC registers for each channel. Two MSBs store power-down information, 8 LSBs store DAC data. An
DRC[9:0], DRD[9:0] update of this register means a DAC update with data or power down.
DAC5574 as a Slave Receiver - Standard and Fast Mode
Figure 33 shows the standard and fast mode master transmitter addressing a DAC5574 Slave Receiver with a
7-bit address.
Figure 33. Standard and Fast Mode: Slave Receiver
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HS-Master Code R/W A Ctrl-Byte A MS-Byte A LS-Byte A/A P
0 (write)
Data Transferred
(n* Words + Acknowledge)
Word = 16 Bit
S A Sr Slave Address
HS-Mode Continues
F/S-Mode HS-Mode F/S-Mode
Sr Slave Address
0 0 0 0 1 X X R/W
MSB LSB
HS-Mode Master Code:
A3 A2 L1 L0 X Sel1 Sel2 PD0
MSB LSB
Control Byte:
A3 = Extended Address Bit
A2 = Extended Address Bit
L1 = Load1 (Mode Select) Bit
L0 = Load0 (Mode Select) Bit
Sel1 = Buff Sel1 (Channel) Select Bit
Sel0 = Buff Sel0 (Channel) Select Bit
PD0 = Power Down Flag
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
MS-Byte:
X X X X X X X X
MSB LSB
LS-Byte:
D11 − D0 = Data Bits
X = Don’t Care
SLAS407 – DECEMBER 2003
DAC5574 as a Slave Receiver - High-Speed Mode
Figure 34 shows the high-speed mode master transmitter addressing a DAC5574 Slave Receiver with a 7-bit
address.
DAC5574
Figure 34. High-Speed Mode: Slave Receiver
17
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DAC5574
SLAS407 – DECEMBER 2003
Master Transmitter Writing to a Slave Receiver (DAC5574) in Standard/Fast Modes
All write access sequences begin with the device address (with R/ W = 0) followed by the control byte. This
control byte specifies the operation mode of DAC5574 and determines which channel of DAC5574 is being
accessed in the subsequent read/write operation. The LSB of the control byte (PD0-Bit) determines if the
following data is power-down data or regular data.
With (PD0-Bit = 0) the DAC5574 expects to receive data in the following sequence HIGH-BYTE –LOW-BYTE –
HIGH-BYTE – LOW-BYTE..., until a STOP Condition or REPEATED START Condition on the I2C-Bus is
recognized (refer to the DATA INPUT MODE section of Table 4 ).
With (PD0-Bit = 1) the DAC5574 expects to receive 2 Bytes of power-down data (refer to the POWER DOWN
MODE section of Table 4 ).
Table 4. Write Sequence in F/S Mode
DATA INPUT MODE
Transmitter MSB 6 5 4 3 2 1 LSB Comment
Master Start Begin sequence
Master 1 0 0 1 1 A1 A0 R/ W Write addressing ( R/ W=0)
DAC5574 DAC5574 Acknowledges
Master 0 0 Load 1 Load 0 x Buff Sel 1 Buff Sel 0 PD0 Control byte ( PD0=0)
DAC5574 DAC5574 Acknowledges
Master D7 D6 D5 D4 D3 D2 D1 D0 Writing data word, high byte
DAC5574 DAC5574 Acknowledges
Master x x x x x x x x Writing data word, low byte
DAC5574 DAC5574 Acknowledges
Master Data or Stop or Repeated Start
POWER DOWN MODE
Transmitter MSB 6 5 4 3 2 1 LSB Comment
Master Start Begin sequence
Master 1 0 0 1 1 A1 A0 R/ W Write addressing (R/ W=0)
DAC5574 DAC5574 Acknowledges
Master 0 0 Load 1 Load 0 x Buff Sel 1 Buff Sel 0 PD0 Control byte ( PD0 = 1)
DAC5574 DAC5574 Acknowledges
Master PD1 PD2 0 0 0 0 0 0 Writing data word, high byte
DAC5574 DAC5574 Acknowledges
Master x x x x x x x x Writing data word, low byte
DAC5574 DAC5574 Acknowledges
Master Stop or Repeated Start
(1) Use repeated START to secure bus operation and loop back to the stage of write addressing for next Write.
(2) Once DAC5574 is properly addressed and control byte is sent, HIGH–BYTE–LOW–BYTE sequences can repeat until a STOP condition
or repeated START condition is received.
(1)
(1)
Data or done
Done
(2)
18
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DAC5574
SLAS407 – DECEMBER 2003
Master Transmitter Writing to a Slave Receiver (DAC5574) in HS Mode
When writing data to the DAC5574 in HS-mode, the master begins to transmit what is called the HS-Master
Code (0000 1XXX) in F/S-mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master
Code is followed by a NOT acknowledge.
The master then switches to HS-mode and issues a repeated start condition, followed by the address byte (with
R/ W = 0) after which the DAC5574 acknowledges by pulling SDA low. This address byte is usually followed by
the control byte, which is also acknowledged by the DAC5574. The LSB of the control byte (PD0-Bit) determines
if the following data is power-down data or regular data.
With (PD0-Bit = 0) the DAC5574 expects to receive data in the following sequence HIGH-BYTE – LOW-BYTE –
HIGH-BYTE – LOW-BYTE...., until a STOP condition or repeated start condition on the I2C-Bus is recognized
(refer to Table 5 HS-MODE WRITE SEQUENCE - DATA).
With (PD0-Bit = 1) the DAC5574 expects to receive 2 bytes of power-down data (refer to Table 5 HS-MODE
WRITE SEQUENCE - POWER DOWN).
Table 5. Master Transmitter Writes to Slave Receiver (DAC5574) in HS-Mode
HS MODE WRITE SEQUENCE - DATA
Transmitter MSB 6 5 4 3 2 1 LSB Comment
Master Start Begin sequence
Master 0 0 0 0 1 X X X HS Mode Master Code
NONE Not Acknowledge
Master Repeated Start
Master 1 0 0 1 1 A1 A0 R/ W Write addressing ( R/ W=0)
DAC5574 DAC5574 Acknowledges
Master 0 0 Load 1 Load 0 0 Buff Sel 1 Buff Sel 0 PD0 Control byte ( PD0=0)
DAC5574 DAC5574 Acknowledges
Master D7 D6 D5 D4 D3 D2 D1 D0 Writing data word, MSB
DAC5574 DAC5574 Acknowledges
Master x x x x x x x x Writing data word, LSB
DAC5574 DAC5574 Acknowledges
Master Data or Stop or Repeated Start
HS MODE WRITE SEQUENCE - POWER DOWN
Transmitter MSB 6 5 4 3 2 1 LSB Comment
Master Start Begin sequence
Master 0 0 0 0 1 X X X HS Mode Master Code
NONE Not Acknowledge
Master Repeated Start
Master 1 0 0 1 1 A1 A0 R/ W Write addressing ( R/ W = 0)
DAC5574 DAC5574 Acknowledges
Master 0 0 Load 1 Load 2 0 Buff Sel 1 Buff Sel 0 PD0 Control Byte ( PD0=1)
DAC5574 DAC5574 Acknowledges
Master PD1 PD2 0 0 0 0 0 0 Writing data word, high byte
DAC5574 DAC5574 Acknowledges
Master x x x x x x x x Writing data word, low byte
DAC5574 DAC5574 Acknowledges
Master Stop or repeated start
(1) Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write.
(2) Once DAC5574 is properly addressed and control byte is sent, high-byte-low-byte sequences can repeat until a stop or repeated start
condition is received.
(1)
(1)
No device may acknowledge HS master code
Data or done
No device may acknowledge HS master code
Done
(2)
19
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SLAVE ADDRESS R/W A Ctrl <7:1> A MS-Byte A LS-Byte A P
0 (write)
Data Transferred
(2 Bytes + Acknowledge)
PDN-Byte:
PD1 PD2 1 1 1 1 1 1
MSB LSB
S
PD0 Sr Slave Address R/W A
1 (read)
0 = (Normal Mode)
A PDN-Byte A LS-Byte A PPD0 Sr Slave Address R/W A MS-Byte A
(DAC5574) (MASTER) (MASTER)
1 = (Power Down Flag)
Data Transferred
(3 Bytes + Acknowledge)
(DAC5574) (MASTER) (MASTER) (MASTER)
PD1 = Power−Down Bit
PD2 = Power−Down Bit
1 (read)
(DAC5574) (DAC5574)
Slave Address R/WACtrl <7:1> A MS-Byte A LS-Byte A P
0 (write)
Data Transferred
(2 Bytes + Acknowledge)
PD0Sr Slave Address R/W A
1 (read)
0 = (Normal Mode)
A PDN-Byte A LS-Byte A PPD0 Sr Slave Address R/W A MS-Byte A
(DAC5574) (DAC5574) (DAC5574) (MASTER) (MASTER)
1 = (Power −Down Flag)
Data Transferred
(3 Bytes + Acknowledge)
(DAC5574) (MASTER) (MASTER) (MASTER)
Sr
HS-Mode
AS
F/S-Mode
1 (read)
HS-Master Code
DAC5574
SLAS407 – DECEMBER 2003
DAC5574 as a Slave Transmitter - Standard and Fast Mode
Figure 35 shows the standard and fast mode master transmitter addressing a DAC5574 Slave Transmitter with a
7-bit address.
Figure 35. Standard and Fast Mode: Slave Transmitter
DAC5574 as a Slave Transmitter - High-Speed Mode
Figure 36 shows an I2C-Master addressing DAC5574 in high-speed mode (with a 7-bit address), as a Slave
Transmitter.
20
Figure 36. High-Speed Mode: Slave Transmitter
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DAC5574
SLAS407 – DECEMBER 2003
Master Receiver Reading From a Slave Transmitter (DAC5574) in Standard/Fast Modes
When reading data back from the DAC5574, the user begins with an address byte (with R/ W = 0) after which the
DAC5574 will acknowledge by pulling SDA low. This address byte is usually followed by the Control Byte, which
is also acknowledged by the DAC5574. Following this there is a REPEATED START condition by the Master and
the address is resent with (R/ W = 1). This is acknowledged by the DAC5574, indicating that it is prepared to
transmit data. Two or three bytes of data are then read back from the DAC5574, depending on the (PD0-Bit).
The value of Buff-Sel1 and Buff-Sel0 determines, which channel data is read back. A STOP Condition follows.
With the (PD0-Bit = 0) the DAC5574 transmits 2 bytes of data, HIGH-BYTE followed by the LOW-BYTE (refer to
Table 2. Data Readback Mode - 2 bytes).
With the (PD0-Bit = 1) the DAC5574 transmits 3 bytes of data, POWER-DOWN-BYTE followed by the
HIGH-BYTE followed by the LOW-BYTE (refer to Table 2. Data Readback Mode - 3 bytes).
Table 6. Read Sequence in F/S Mode
DATA READBACK MODE - 2 BYTES
Transmitter MSB 6 5 4 3 2 1 LSB Comment
Master Start Begin sequence
Master 1 0 0 1 1 A1 A0 R/ W Write addressing ( R/ W=0)
DAC5574 DAC5574 Acknowledges
Master 0 0 Load 1 Load 0 x Buff Sel 1 Buff Sel 0 PD0 Control byte ( PD0=0)
DAC5574 DAC5574 Acknowledges
Master Repeated Start
Master 1 0 0 1 1 A1 A0 R/ W Read addressing ( R/ W = 1)
DAC5574 DAC5574 Acknowledges
DAC5574 D7 D6 D5 D4 D3 D2 D1 D0 Reading data word, high byte
Master Master Acknowledges
DAC5574 x x x x x x x x Reading data word, low byte
Master Master Not Acknowledges Master signal end of read
Master Stop or Repeated Start
DATA READBACK MODE - 3 BYTES
Transmitter MSB 6 5 4 3 2 1 LSB Comment
Master Start Begin sequence
Master 1 0 0 1 1 A1 A0 R/ W Write addressing ( R/ W=0)
DAC5574 DAC5574 Acknowledges
Master 0 0 Load 1 Load 0 x Buff Sel 1 Buff Sel 0 PD0 Control byte ( PD0=1)
DAC5574 DAC5574 Acknowledges
Master Repeated Start
Master 1 0 0 1 1 A1 A0 R/ W Read addressing ( R/ W = 1)
DAC5574 DAC5574 Acknowledges
DAC5574 PD1 PD2 1 1 1 1 1 1 Read power down byte
Master Master Acknowledges
DAC5574 D7 D6 D5 D4 D3 D2 D1 D0 Reading data word, high byte
Master Master Acknowledges
DAC5574 x x x x x x x x Reading data word, low byte
Master Master Not Acknowledges Master signal end of read
Master Stop or Repeated Start
(1) Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write.
(1)
(1)
Done
Done
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DAC5574
SLAS407 – DECEMBER 2003
Master Receiver Reading From a Slave Transmitter (DAC5574) in HS-Mode
When reading data to the DAC5574 in HS-MODE, the master begins to transmit, what is called the HS-Master
Code (0000 1XXX) in F/S-mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master
Code is followed by a NOT acknowledge.
The Master then switches to HS-mode and issues a REPEATED START condition, followed by the address byte
(with R/ W = 0) after which the DAC5574 acknowledges by pulling SDA low. This address byte is usually followed
by the control byte, which is also acknowledged by the DAC5574.
Then there is a REPEATED START condition initiated by the master and the address is resent with (R/ W = 1).
This is acknowledged by the DAC5574, indicating that it is prepared to transmit data. Two or Three bytes of data
are then read back from the DAC5574, depending on the (PD0-Bit). The value of Buff-Sel1 and Buff-Sel0
determines, which channel data is read back. A STOP condition follows.
With the (PD0-Bit = 0) the DAC5574 transmits 2 bytes of data, HIGH-BYTE followed by LOW-BYTE (refer to
Table 7 HS-Mode Readback Sequence).
With the (PD0-Bit = 1) the DAC5574 transmits 3 bytes of data, POWER-DOWN-BYTE followed by the
HIGH-BYTE followed by the LOW-BYTE (refer to Table 7 HS-Mode Readback Sequence).
Table 7. Master Receiver Reading Slave Transmitter (DAC5574) in HS-Mode
HS MODE READBACK SEQUENCE
Transmitter MSB 6 5 4 3 2 1 LSB Comment
Master Start Begin sequence
Master 0 0 0 0 1 X X X HS Mode Master Code
NONE Not Acknowledge
Master Repeated Start
Master 1 0 0 1 1 A1 A0 R/ W Write addressing ( R/ W=0)
DAC5574 DAC5574 Acknowledges
Master 0 0 Load 1 Load 0 X Buff Sel 1 Buff Sel 0 PD0 Control byte ( PD0 = 1)
DAC5574 DAC5574 Acknowledges
Master Repeated Start
Master 1 0 0 1 1 A1 A0 R/ W Read addressing ( R/ W=1)
DAC5574 DAC5574 Acknowledges
DAC5574 PD1 PD2 1 1 1 1 1 1 Power-down byte
Master Master Acknowledges
DAC5574 D7 D6 D5 D4 D3 D2 D1 D0 Reading data word, high byte
Master Master Acknowledges
DAC5574 x x x x x x x x Reading data word, low byte
Master Master Not Acknowledges Master signal end of read
Master Stop or Repeated Start Done
No device may acknowledge HS
master code
Power-On Reset
The DAC5574 contains a power-on-reset circuit that controls the output voltage during power up. On power up,
the DAC register is filled with zeros and the output voltage is 0 V; it remains there until a valid write sequence is
made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC
while it is in the process of powering up. No device pin should be brought high before supply is applied.
Power-Down Modes
The DAC5574 contains four separate power-down modes of operation. The modes are programmable via two
most significant bits of the MSB byte, while (CTRL[0] = PD0 = 1). Table 8 shows how the state of these bits
correspond to the mode of operation of the device.
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Resistor
String DAC
Powerdown
Circuitry
V
OUT
Amplifier
Resistor
Network
DAC5574
SLAS407 – DECEMBER 2003
Table 8. Power-Down Modes of Operation for the DAC5574
CTRL[0] MSB[7] MSB[6] OPERATING MODE
1 0 0 High Impedance Output
1 0 1 1 k Ω to GND
1 1 0 100 k Ω to GND
1 1 1 High Impedance
When (CTRL[0] = PD0 = 0), the device works normally with its normal power consumption of 150 µA at 5 V per
channel. However, for the power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only
does the supply current fall but also the output stage is also internally switched from the output of the amplifier to
a resistor network of known values. This has the advantage that the output impedance of the device is known
while in power-down mode. There are three different options: The output is connected internally to GND through
a 1-k Ω resistor, a 100-k Ω resistor or left open-circuit (high impedance). The output stage is illustrated in
Figure 37 .
Figure 37. Output Stage During Power Down
All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time to exit power down is typically 2.5 µs for V
µs for V
= 3 V. (See the Typical Curves section for additional information.)
DD
= 5 V and 5
DD
The DAC5574 offers a flexible power-down interface based on channel register operation. A channel consists of
a single 8-bit DAC with power-down circuitry, a temporary storage register (TR) and a DAC register (DR). TR and
DR are both 10 bits wide. Two MSBs represent the power-down condition and the 8 LSBs represent data for TR
and DR. By using bits 9 and 8 of TR and DR, a power-down condition can be temporarily stored and used just
like data. Internal circuits ensure that MSB[7] and MSB[6] get transferred to TR[9] and TR[8] (DR[9] and DR[8])
when the power-down flag (CTRL[0] = PD0) is set. Therefore, DAC5574 treats power-down conditions like data
and all the operational modes are still valid for power down. It is possible to broadcast a power-down condition to
all the DAC5574s in the system, or it is possible to simultaneously power down a channel while updating data on
other channels.
CURRENT CONSUMPTION
The DAC5574 typically consumes 150 µA at V
reference current consumption. Additional current consumption can occur at the digital inputs if V
most efficient power operation, CMOS logic levels are recommended at the digital inputs to the DAC. In
power-down mode, typical current consumption is 200 nA.
= 5 V and 125 µA at V
DD
= 3 V for each active channel, including
DD
<< V
IH
. For
DD
DRIVING RESISTIVE AND CAPACITIVE LOADS
The DAC5574 output stage is capable of driving loads of up to 1000 pF while remaining stable. Within the offset
and gain error margins, the DAC5574 can operate rail-to-rail when driving a capacitive load. Resistive loads of 2
k Ω can be driven by the DAC5574 while achieving a good load regulation. When the outputs of the DAC are
driven to the positive rail under resistive loading, the PMOS transistor of each Class-AB output stage can enter
into the linear region. When this occurs, the added IR voltage drop deteriorates the linearity performance of the
DAC. This only occurs within approximately the top 20 mV of the DAC's digital input-to-voltage output transfer
characteristic.
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DAC5574
SLAS407 – DECEMBER 2003
CROSSTALK
The DAC5574 architecture uses separate resistor strings for each DAC channel in order to achieve ultra-low
crosstalk performance. DC crosstalk seen at one channel during a full-scale change on the neighboring channel
is typically less than 0.0025 LSBs. The ac crosstalk measured (for a full-scale, 1 kHz sine wave output generated
at one channel, and measured at the remaining output channel) is typically under –100 dB.
OUTPUT VOLTAGE STABILITY
The DAC5574 exhibits excellent temperature stability of ±3 ppm/ °C typical output voltage drift over the specified
temperature range of the device. This enables the output voltage of each channel to stay within a ±25 µV window
for a ±1 °C ambient temperature change. Combined with good dc noise performance and true 8-bit differential
linearity, the DAC5574 becomes a perfect choice for closed-loop control applications.
SETTLING TIME AND OUTPUT GLITCH PERFORMANCE
Settling time to within the 8-bit accurate range of the DAC5574 is achievable within 6 µs for a full-scale code
change at the input. Worst case settling times between consecutive code changes is typically less than 2 µs. The
high-speed serial interface of the DAC5574 is designed in order to support up to 188 kSPS update rate. For
full-scale output swings, the output stage of each DAC5574 channel typically exhibits less than 100 mV of
overshoot and undershoot when driving a 200 pF capacitive load. Code-to-code change glitches are extremely
low (~10 µV) given that the code-to-code transition does not cross an Nx16 code boundary. Due to internal
segmentation of the DAC5574, code-to-code glitches occur at each crossing of an Nx16 code boundary. These
glitches can approach 100 mVs for N = 15, but settle out within ~2 µs. Sufficient bypass capacitance is required
to ensure 10 µs settling under capacitive loading. To observe the settling performance under resistive load
conditions, the power supply (hence DAC5574 reference supply) must settle quicker than the DAC5574.
24
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4
5
1
2
3
6
8
7
10
9
DAC5574
V
OUT
A
V
OUT
B
V
DD
V
OUT
C
GND
V
OUT
D
A1
A0
SDA
SCL
SDA
SCL
I2C Pullup Resistors
1 kΩ to 10 kΩ (typical)
V
DD
Microcontroller or
Microprocessor With
I2C Port
NOTE: DAC5574 power and input/output connections are omitted for clarity, except IC Inputs.
DAC5574
SLAS407 – DECEMBER 2003
APPLICATION INFORMATION
The following sections give example circuits and tips for using the DAC5574 in various applications. For more
information, contact your local TI representative, or visit the Texas Instruments website at http://www.ti.com.
BASIC CONNNECTIONS
For many applications, connecting the DAC5574 is extremely simple. A basic connection diagram for the
DAC5574 is shown in Figure 38 . The 0.1 µF bypass capacitors help provide the momentary bursts of extra
current needed from the supplies.
The DAC5574 interfaces directly to standard mode, fast mode and high-speed mode I2C controllers. Any
microcontroller's I2C peripheral, including master-only and non-multiple-master I2C peripherals, work with the
DAC5574. The DAC5574 does not perform clock-stretching (i.e., it never pulls the clock line low), so it is not
necessary to provide for this unless other devices are on the same I2C bus.
Pullup resistors are necessary on both the SDA and SCL lines because I2C bus drivers are open-drain. The size
of the these resistors depend on the bus operating speed and capacitance on the bus lines. Higher-value
resistors consume less power, but increase the transition times on the bus, limiting the bus speed. Lower-value
resistors allow higher speed at the expense of higher power consumption. Long bus lines have higher
capacitance and require smaller pullup resistors to compensate. If the pullup resistors are too small the bus
drivers may not be able to pull the bus line low.
USING GPIO PORTS FOR I2C
Most microcontrollers have programmable input/output pins that can be set in software to act as inputs or
outputs. If an I2C controller is not available, the DAC5574 can be connected to GPIO pins, and the I2C bus
protocol simulated, or bit-banged, in software. An example of this for a single DAC5574 is shown in Figure 39 .
Figure 38. Typical DAC5574 Connections
25
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1
2
3
6
8
7
10
9
DAC5574
V
OUT
A
V
OUT
B
V
DD
GND
V
OUT
C
V
OUT
D
A1
A0
SDA
SCL
GPIO-2
GPIO-1
V
DD
Microcontroller or
Microprocessor
NOTE: DAC5574 power and input/output connections are omitted for clarity, except IC Inputs.
4
5
DAC5574
SLAS407 – DECEMBER 2003
APPLICATION INFORMATION (continued)
Bit-banging I2C with GPIO pins can be done by setting the GPIO line to zero and toggling it between input and
output modes to apply the proper bus states. To drive the line low, the pin is set to output a zero; to let the line
go high, the pin is set to input. When the pin is set to input, the state of the pin can be read; if another device is
pulling the line low, this reads as a zero in the port's input register.
Note that no pullup resistor is shown on the SCL line. In this simple case the resistor is not needed. The
microcontroller can simply leave the line on output, and set it to one or zero as appropriate. It can do this
because the DAC5574 never drives its clock line low. This technique can also be used with multiple devices, and
has the advantage of lower current consumption due to the absence of a resistive pullup.
If there are any devices on the bus that may drive their clock lines low, the above method should not be used.
The SCL line should be high-Z or zero, and a pullup resistor provided as usual. Note also that this cannot be
done on the SDA line in any case, because the DAC5574 drives the SDA line low from time to time, as all I2C
devices do.
Some microcontrollers have selectable strong pullup circuits built in to their GPIO ports. In some cases, these
can be switched on and used in place of an external pullup resistor. Weak pullups are also provided on some
microcontrollers, but usually these are too weak for I2C communication. Test any circuit before committing it to
production.
POWER SUPPLY REJECTION
The positive reference voltage input of DAC5574 is internally tied to the power supply pin of the device. This
increases I2C system flexibility, creating room for an extra I2C address pin in a low pin-count package. To
eliminate the supply noise appearing at the DAC output, the user must pay close attention to how DAC5574 is
powered. The supply to DAC5574 must be clean and well regulated. For best performance, use of a precision
voltage reference is recommended to supply power to DAC5574. This is equivalent to providing a precision
Figure 39. Using GPIO With a Single DAC5574
26
www.ti.com
REF02
15 V
5 V
1.6 mA
V
DD
SCL
SDA
I2C
Interface
V
OUT
= 0 V to 5 V
DAC5574
DAC5574
SLAS407 – DECEMBER 2003
APPLICATION INFORMATION (continued)
external reference to the device. Due to low power consumption of DAC5574, load regulation errors are
negligible. In order to avoid excess power consumption at the Schmitt-triggered inputs of DAC5574, the precision
reference voltage should be close to the I2C bus pullup voltage. For 3-V, 3.3-V and 5-V I2C bus pullup voltages,
REF2930, REF2933 and REF02 precision voltage references are recommended respectively. These precision
voltage references can be used to supply power for multiple devices on a system.
USING REF02 AS A POWER SUPPLY FOR DAC5574
Due to the extremely low supply current required by the DAC5574, a possible configuration is to use a REF02
+5 V precision voltage reference to supply the required voltage to the DAC5574's supply input as well as the
reference input, as shown in Figure 40 . This is especially useful if the power supply is quite noisy or if the system
supply voltages are at some value other than 5 V. The REF02 outputs a steady supply voltage for the DAC5574.
If the REF02 is used, the current it needs to supply to the DAC5574 is 600 µA typical and 900 µA max for
V
= 5 V. When a DAC output is loaded, the REF02 also needs to supply the current to the load. The total
DD
typical current required (with a 5-k Ω load on a single DAC output) is:
600 µA + (5 V / 5 k Ω) = 1.6 mA
The load regulation of the REF02 is typically 0.005%/mA, which results in an error of 400 µV for 1.6-mA of current
drawn from it. This corresponds to a 0.02 LSB error for a 0 V to 5 V output range.
Figure 40. REF02 Power Supply
LAYOUT
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power
supplies.
The power applied to V
converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital
components can create similar high-frequency spikes as their internal logic switches states. This noise can easily
couple into the DAC output voltage through various paths between the power connections and analog output.
As with the GND connection, V
from the connection for digital logic until they are connected at the power-entry point. In addition, a 1- µF to 10- µF
capacitor in parallel with a 0.1- µF bypass capacitor is strongly recommended. In some situations, additional
bypassing may be required, such as a 100- µF electrolytic capacitor or even a Pi filter made up of inductors and
capacitors—all designed to essentially low-pass filter the –5 V supply, removing the high-frequency noise.
should be well-regulated and low noise. Switching power supplies and dc/dc
DD
should be connected to a positive power-supply plane or trace that is separate
DD
27
PACKAGE OPTION ADDENDUM
www.ti.com
7-Aug-2007
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
DAC5574IDGS ACTIVE MSOP DGS 10 80 Green (RoHS &
no Sb/Br)
DAC5574IDGSG4 ACTIVE MSOP DGS 10 80 Green (RoHS &
no Sb/Br)
DAC5574IDGSR ACTIVE MSOP DGS 10 2500 Green (RoHS &
no Sb/Br)
DAC5574IDGSRG4 ACTIVE MSOP DGS 10 2500 Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
(3)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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