Datasheet DAC5571IDBVTG4, DAC5571 Datasheet (Texas Instruments)

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SCLA0

GND

Output

Buffer

Power-Down

Control Logic

Resistor Network

Ref (+) Ref(−)

8-Bit DAC

I2C

Control

Logic

DAC

Power-On

Reset

OUT

SDA

+2.7 V to +5.5 V, I2C INTERFACE, VOLTAGE OUTPUT,

8-BIT DIGITAL-TO-ANALOG CONVERTER

FEATURES DESCRIPTION

• Micropower Operation: 125 µA @ 3 V

• Fast Update Rate: 188 KSPS

• Power-On Reset to Zero

• +2.7-V to +5.5-V Power Supply

• Specified Monotonic by Design

• I2C™ Interface up to 3.4 Mbps

• On-Chip Output Buffer Amplifier, Rail-to-Rail

Operation

• Double-Buffered Input Register

• Address Support for up to Two DAC5571s

• Small 6 Lead SOT 23 Package

• Operation From –40 °C to 105 °C

APPLICATIONS

• Process Control

• Data Acquistion Systems

• Closed-Loop Servo Control

• PC Peripherals power-down mode.

• Portable Instrumentation

The DAC5571 is a low-power, single-channel, 8-bit buffered voltage output DAC. Its on-chip precision output amplifier allows rail-to-rail output swing to be achieved. The DAC5571 utilizes an I2C-compatible, two-wire serial interface that operates at clock rates up to 3.4 Mbps with address support of up to two DAC5571s on the same data bus.

The output voltage range of the DAC is 0 V to V The DAC5571 incorporates a power-on-reset circuit that ensures that the DAC output powers up at zero volts and remains there until a valid write to the device takes place. The DAC5571 contains a power-down feature, accessed via the internal control register, that reduces the current consumption of the device to 50 nA at 5 V.

The low-power consumption of this part in normal operation makes it ideally suited for portable battery operated equipment. The power consumption is less than 0.7 mW at V

DAC7571/6571/5571 are 12/10/8-bit, single-channel I2C DACs from the same family. DAC7574/6574/5574 and DAC7573/6573/5573 are 12/10/8-bit quad-channel I2C DACs. Also see DAC8571/8574 for single/quad-channel, 16-bit I2C DACs.

DAC5571

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

= 5 V reducing to 1 µW in

I2C is a trademark of Philips Corporation.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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A0 SCL SDA

6 5 4

1 2 3

OUT

GND

D571

1 2 3

6 5 4

YMLL

(TOP VIEW)

(BOTTOM VIEW)

Lot Trace Code

DAC5571

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION

PRODUCT PACKAGE DESIG- TRANSPORT MEDIA

PACKAGE

NATOR

DAC5571 SOT23-6 DBV –40°C to +105°C D571

SPECIFIED TEM- PACKAGE ORDERING NUM-

PERATURE RANGE MARKING BER

DAC5571IDBVT 250-Piece Small Tape and Reel DAC5571IDBVR 3000-Piece Tape and Reel

PIN CONFIGURATIONS

PIN NAME DESCRIPTION

1 V 2 GND 3 V

4 SDA Serial Data Input 5 SCL Serial Clock Input 6 A0 Device Address Select

LOT Year (3 = 2003); M onth (1–9 = JAN–SEP; A=OCT,

TRACE B=NOV, C=DEC); LL– Random code generated

CODE: when assembly is requested

PIN DESCRIPTION (SOT23-6)

OUT

Analog output voltage from DAC Ground reference point for all

circuitry Analog Voltage Supply Input

ABSOLUTE MAXIMUM RATINGS

to GND – 0.3 V to +6 V

Digital input voltage to GND –0.3 V to +V V

to GND – 0.3 V to +V

OUT

Operating temperature range –40 °C to +105 °C Storage temperature range –65 °C to +150 °C Junction temperature range (T Power dissipation (TJmax - TA)R Thermal impedance, R Lead temperature, soldering Vapor phase (60s) 215 °C

(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute

maximum conditions for extended periods may affect device reliability.

ΘJA

max) +150 °C

(1)

UNITS

Infrared (15s) 220 °C

+0.3 V

ΘJA

240 °C/W

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DAC5571

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

ELECTRICAL CHARACTERISTICS

= +2.7 V to +5.5 V; RL= 2 k Ω to GND; CL= 200 pF to GND; all specifications –40°C to +105°C unless otherwise noted.

PARAMETER CONDITIONS UNITS

STATIC PERFORMANCE

(1)

Resolution 8 Bits Relative accuracy ±0.5 LSB Differential nonlinearity Assured monotonic by design ±0.25 LSB Zero code error 5 20 mV Full-scale error All ones loaded to DAC register -0.15 -1.25 % of FSR Gain error ±1.25 % of FSR Zero code error drift ± 7 µV/°C Gain temperature coefficient ± 3 ppm of FSR/ °C

OUTPUT CHARACTERISTICS

(2)

Output voltage range 0 V Output voltage settling time 6 8 µs

1/4 Scale to 3/4 scale change (400

RL= ∞

to C00

) ;

Slew rate 1 V/µs

Capacitive load stability

RL= ∞ 470 pF

RL= 2 k Ω 1000 pF Code change glitch impulse 1 LSB Change around major carry 20 nV-s Digital feedthrough 0.5 nV-s DC output impedance 1 Ω

= +5 V 50 mA

Short-circuit current

Power-up time

LOGIC INPUTS

Coming out of power-down mode, V Coming out of power-down mode, V

(3)

= +3 V 20 mA

= +5 V 2.5 µs

= +3 V 5 µs

Input current ±1 µA VINL, Input low voltage V VINH, Input high voltage V

= +3 V 0.3×V

= +5 V 0.7×V

Pin capacitance 3 pF

POWER REQUIREMENTS

IDD(normal operation) DAC active and excluding load current

= +3.6 V to +5.5 V VIH= V

= +2.7 V to +3.6 V VIH= V

and VIL= GND 155 200 µA

and VIL= GND 125 160 µA

IDD(all power-down modes)

= +3.6 V to +5.5 V VIH= V

= +2.7 V to +3.6 V VIH= V

and VIL= GND 0.2 1 µA

and VIL= GND 0.05 1 µA

POWER EFFICIENCY

OUT

= 2 mA, V

LOAD

= +5 V 93 %

(1) Linearity calculated using a reduced code range of 3 to 253; output unloaded. (2) Specified by design and characterization, not production tested. (3) Specified by design and characterization, not production tested.

DAC5571

MIN TYP MAX

2.7 5.5 V

V V

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DAC5571

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

TIMING CHARACTERISTICS

SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

tHD; t

tSU; t

tHD; t

SCL

BUF

STA

LOW

HIGH

STA

DAT

RCL

RCL1

FCL

RDA

FDA

SCL Clock Frequency Standard mode 100 kHz

Fast mode 400 kHz High-speed mode, CB- 100 pF max 3.4 MHz High-Speed mode, CB- 400 pF max 1.7 MHz

Bus Free Time Between a STOP Standard mode 4.7 µs

and START Condition

Fast mode 1.3 µs

Hold Time (Repeated) START Standard mode 4.0 µs

Condition

Fast mode 600 ns

High-speed mode 160 ns

LOW Period of the SCL Clock Standard mode 4.7 µs

Fast mode 1.3 µs High-speed mode, CB- 100 pF max 160 ns High-speed mode, CB- 400 pF max 320 ns

HIGH Period of the SCL Clock Standard mode 4.0 µs

Fast mode 600 ns High-speed mode, CB- 100 pF max 60 ns High-speed mode, CB- 400 pF max 120 ns

Setup Time for a Repeated Standard mode 4.7 µs

START Condition

Fast mode 600 ns

High-speed mode 160 ns

Data Setup Time Standard mode 250 ns

Fast mode 100 ns

High-speed mode 10 ns

Data Hold Time Standard mode 0 3.45 µs

Fast mode 0 0.9 µs High-speed mode, CB- 100 pF max 0 70 ns High-speed mode, CB- 400 pF max 0 150 ns

Rise Time of SCL Signal Standard mode 1000 ns

Fast mode 20 + 0.1C

High-speed mode, CB- 100 pF max 10 40 ns High-speed mode, CB- 400 pF max 20 80 ns

Rise Time of SCL Signal After a Standard mode 1000 ns

Repeated START Condition and

After an Acknowledge BIT

Fast mode 20 + 0.1C

High-speed mode, CB- 100 pF max 10 80 ns High-speed mode, CB- 400 pF max 20 160 ns

Fall Time of SCL Signal Standard mode 300 ns

Fast mode 20 + 0.1C

High-speed mode, CB- 100 pF max 10 40 ns High-speed mode, CB- 400 pF max 20 80 ns

Rise Time of SDA Signal Standard mode 1000 ns

Fast mode 20 + 0.1C

High-speed mode, CB- 100 pF max 10 80 ns High-speed mode, CB- 400 pF max 20 160 ns

Fall Time of SDA Signal Standard mode 300 ns

Fast mode 20 + 0.1C

High-speed mode, CB- 100 pF max 10 80 ns High-speed mode, CB- 400 pF max 20 160 ns

300 ns

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−0.5

−0.4

−0.3

−0.2

−0.1

0.1

0.2

0.3

0.4

0.5

−0.25

−0.2

−0.15

−0.1

−0.05

0.05

0.1

0.15

0.2

0.25

0 32 64 96 128 160 192 224 256

Digital Input Code

VDD = 5 V at 25°C

LE − LSBDLE − LSB

−0.5

−0.4

−0.3

−0.2

−0.1

0.1

0.2

0.3

0.4

0.5

−0.25

−0.2

−0.15

−0.1

−0.05

0.05

0.1

0.15

0.2

0.25

0 32 64 96 128 160 192 224 256

VDD = 5 V at −40°C

Digital Input Code

LE − LSBDLE − LSB

−0.5

−0.4

−0.3

−0.2

−0.1

0.1

0.2

0.3

0.4

0.5

−0.25

−0.2

−0.15

−0.1

−0.05

0.05

0.1

0.15

0.2

0.25

0 32 64 96 128 160 192 224 256

Digital Input Code

VDD = 5 V at 105°C

LE − LSB

DLE − LSB

−16

−8

0 32 64 96 128 160 192 224 256

Digital Input Code

VDD = 5 V, T

= 25°C

Output Error − mV

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

TIMING CHARACTERISTICS (continued)

SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

tSU; t

Setup Time for STOP Condition Standard mode 4.0 µs

STO

Fast mode 600 ns

High-speed mode 160 ns

Capacitive Load for SDA and SCL 400 pF

Pulse Width of Spike Suppressed Fast mode 50 ns

High-speed mode 10 ns

Noise Margin at the HIGH Level Standard mode 0.2V

for Each Connected Device

(Including Hysteresis)

Fast mode

High-speed mode

Noise Margin at the LOW Level for Standard mode 0.1V

Each Connected Device

(Including Hysteresis)

Fast mode

High-speed mode

DAC5571

TYPICAL CHARACTERISTICS: V

At TA= +25°C, +V

= +5 V, unless otherwise noted.

= +5 V

LINEARITY ERROR AND LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR

vs vs

CODE (-40°C) CODE (+25°C )

Figure 1. Figure 2.

LINEARITY ERROR AND ABSOLUTE ERROR

DIFFERENTIAL LINEARITY ERROR

CODE (+105°C)

Figure 3. Figure 4.

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−30

−20

−10

−50−40−30−20 −10 0 10 20 30 40 50 60 70 80 90 100 110

VDD = 5 V

T − Temperature − C

Zero-Scale Error

−30

−20

−10

−50 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 100 110

VDD = 5 V

Full-Scale Error − mV

T − Temperature − C

500

1000

1500

2000

2500

100

110

120

130

140

150

160

170

180

190

200

VDD = 5 V

− Supply Current − A

f − Frequency − Hz

OUT

(V)

SOURCE/SINK

(mA)

5 10 15

DAC Loaded with FF

DAC Loaded with 00

100

200

300

400

500

0 2 32 64 96 128 160 192 224 252 255

Code

VDD = 5 V

Aµ − Supply Current −

100

150

200

250

300

−50 −40−30 −20−10 0 10 20 30 40 50 60 70 80 90 100 110

VDD = 5 V

− Supply Current − I

Aµ

T − Temperature − C

DAC5571

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

TYPICAL CHARACTERISTICS: V

At TA= +25°C, +V

= +5 V, unless otherwise noted.

ZERO-SCALE ERROR FULL-SCALE ERROR

vs vs

TEMPERATURE TEMPERATURE

Figure 5. Figure 6.

IDDHISTOGRAM SOURCE AND SINK CURRENT CAPABILITY

= +5 V (continued)

SUPPLY CURRENT SUPPLY CURRENT

Figure 7. Figure 8.

vs vs

CODE TEMPERATURE

Figure 9. Figure 10.

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100

150

200

250

300

2.7 3.2 3.7 4.2 4.7 5.2 5.7

− Supply Current − I

Aµ

VDD − Supply Voltage − V

2.7

(nA)

VDD (V)

3.2 3.7 4.2 4.7 5.2 5.7

100

90 80 70 60 50 40 30 20 10

+25°C

–40°C

+105°C

CLK (5V/div)

OUT

(1V/div)

Time (1µs/div)

Full−Scale Code Change

00Hto FF

Output Loaded with

2k and200pF to GNDΩ

(µA)

LOGIC

(V)

1 2 3 4 5

2500

2000

1500

1000

500

DAC5571

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

TYPICAL CHARACTERISTICS: V

At TA= +25°C, +V

= +5 V, unless otherwise noted.

SUPPLY CURRENT POWER-DOWN CURRENT

vs vs

SUPPLY VOLTAGE SUPPLY VOLTAGE

Figure 11. Figure 12.

SUPPLY CURRENT FULL-SCALE SETTLING TIME

LOGIC INPUT VOLTAGE

= +5 V (continued)

Figure 13. Figure 14.

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Time (1 s/div)

CLK (5V/div)

OUT

(1V/div)

Full−Scale Code Change

FFHto 00

Output Loaded with

2k and 200pF to GNDΩ

Time (1 s/div)

CLK (5V/div)

OUT

(1V/div)

Half−Scale Code Change

40Hto C0

Output Loaded with

2k and 200 pFto GNDΩ

Time ( s/div)

CLK (5V/div)

OUT

(1V /div)

Half−Scale C ode Change

C0Hto 40

Output Load ed with

2kΩ and 200pF to GND

1µ

Time (20µs/div)

Loaded with 2kΩ to VDD.

VDD (1V/div)

OUT

(1V/div)

Time (0.5 s/div)

Loaded with 2k and 200pF to G ND.

Code C ha nge:

80Hto 7F

OUT

(20mV/div)

Ω

Time (5µs/div)

CLK (5V/div)

OUT

(1V/div)

DAC5571

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

TYPICAL CHARACTERISTICS: V

At TA= +25°C, +V

= +5 V, unless otherwise noted.

FULL-SCALE SETTLING TIME HALF-SCALE SETTLING TIME

Figure 15. Figure 16.

HALF-SCALE SETTLING TIME POWER-ON RESET TO 0V

= +5 V (continued)

Figure 17. Figure 18.

EXITING POWER DOWN CODE CHANGE GLITCH

(80

Loaded)

Figure 19. Figure 20.

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−0.5

−0.4

−0.3

−0.2

−0.1

0.1

0.2

0.3

0.4

0.5

−0.25

−0.2

−0.15

−0.1

−0.05

0.05

0.1

0.15

0.2

0.25

0 32 64 96 128 160 192 224 256

Digital Input Code

VDD = 2.7 V at −40°C

LE − LSBDLE − LSB

−0.5

−0.4

−0.3

−0.2

−0.1

0.1

0.2

0.3

0.4

0.5

−0.25

−0.2

−0.15

−0.1

−0.05

0.05

0.1

0.15

0.2

0.25

0 32 64 96 128 160 192 224 256

Digital Input Code

LE − LSB

DLE − LSB

VDD = 2.7 V at 25°C

−0.5

−0.4

−0.3

−0.2

−0.1

0.1

0.2

0.3

0.4

0.5

−0.25

−0.2

−0.15

−0.1

−0.05

0.05

0.1

0.15

0.2

0.25

0 32 64 96 128 160 192 224 256

Digital Input Code

VDD = 2.7 V at 105°C

LE − LSBDLE − LSB

−16

−8

32 64 96 128 160 192 224 256

Digital Input Code

Output Error − mV

VDD = 2.7 V TA = 25°C

−50 −30 −10 10 30 50 70 90 110

−30

−20

−10

VDD = 5 V

VDD = 2.7 V

Full-Scale Error − mV

T − Temperature − C

−30

−20

−10

−50 −30 −10 10 30 50 70 90 110

VDD = 2.7 V

Zero-ScalenError − mV

T − Temperature − C

DAC5571

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

TYPICAL CHARACTERISTICS: V

At TA= +25°C, +V

= +2.7 V, unless otherwise noted.

= +2.7 V

LINEARITY ERROR AND LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR

vs vs

CODE (-40°C) CODE (+25°C)

Figure 21. Figure 22.

LINEARITY ERROR AND ABSOLUTE ERRORS

DIFFERENTIAL LINEARITY ERROR

CODE (+105°C)

Figure 23. Figure 24.

ZERO-SCALE ERROR FULL-SCALE ERROR

TEMPERATURE TEMPERATURE

Figure 25. Figure 26.

vs vs

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500

1000

1500

2000

2500

100

110

120

130

140

150

160

170

180

190

200

VDD = 2.7 V

− Supply Current − A

f − Frequency − Hz

OUT

(V)

SO U RC E /S INK

(mA)

5 1 0 15

DAC Load ed with FF

DAC Loaded with 00

VDD= +3V

100

200

300

400

500

0 2 32 64 96 128 160 192 224 252 255

VDD = 2.7 V

Code

Aµ − Supply Current −

100

150

200

250

300

−50 −30 −10 10 30 50 70 90 110

VDD = 2.7 V

− Supply Current −I DD

Aµ

T − Temperature − C

Time (1 s/d iv)

CLK (2.7V/div)

OUT

(1V /div)

Full−Scale Code Chan ge

00Hto FF

Output Load ed w ith

2k and 200pF to GNDΩ

(µA)

LOGIC

(V)

1 2 3 4 5

2500

2000

1500

1000

500

DAC5571

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

TYPICAL CHARACTERISTICS: V

At TA= +25°C, +V

= +2.7 V, unless otherwise noted.

IDDHISTOGRAM SOURCE AND SINK CURRENT CAPABILITY

Figure 27. Figure 28.

SUPPLY CURRENT SUPPLY CURRENT

vs vs

CODE TEMPERATURE

= +2.7 V (continued)

SUPPLY CURRENT FULL SCALE SETTLING TIME

LOGIC INPUT VOLTAGE

Figure 29. Figure 30.

Figure 31. Figure 32.

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Time (1 s/div)

CLK (2.7V/div)

OUT

(1V/div)

Full−Scale Code Change

FFHto 00

Output Loaded with

2k and 200pF to GNDΩ

Time (1s/div)

CLK (2.7V/div)

OUT

(1V/div)

Half−Scale Code Change

40Hto C0

Output Loaded with

Ω

and 200pFto GND

Time (1 s/div)

CLK (2.7V/div)

OUT

(1V/d iv)

Half−Scale Code Change

C0Hto 40

Ou tput Loaded w ith

2k and 200pF to G NDΩ

POWER-ON RESET to 0V

Time (20µs/div)

Time (0.5s/div)

Loaded with 2k



and 200pF to GND. Code Change :

80Hto 7FH.

OUT

(20mV/div)

Time (5µs/div)

CLK (2.7V/div)

OUT

(1V/div)

DAC5571

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

TYPICAL CHARACTERISTICS: V

At TA= +25°C, +V

= +2.7 V, unless otherwise noted.

FULL-SCALE SETTLING TIME HALF-SCALE SETTLING TIME

Figure 33. Figure 34.

HALF-SCALE SETTLING TIME POWER-ON RESET 0 V

= +2.7 V (continued)

Figure 35. Figure 36.

EXITING-POWER DOWN (80

Figure 37. Figure 38.

Loaded) CODE CHANGE GLITCH

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REF (+)

REF (-)

Resistor

String

Output Amplifier

OUT

GND

DAC Register

OUT

 





To Output Amplifier

R R

GND

DAC5571

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

THEORY OF OPERATION

D/A SECTION

The architecture of the DAC5571 consists of a string DAC followed by an output buffer amplifier. Figure 39 shows a block diagram of the DAC architecture.

Figure 39. R-String DAC Architecture

The input coding to the DAC5571 is unsigned binary, which gives the ideal output voltage as:

where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 255.

RESISTOR STRING

The resistor string section is shown in Figure 40 . It is basically a divide-by-2 resistor, followed by a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier. Because the architecture consists of a string of resistors, it is specified monotonic.

Figure 40. Resistor String

OUTPUT AMPLIFIER

The output buffer amplifier is a gain-of-2 amplifier, capable of generating rail-to-rail voltages on its output, which gives an output range of 0 V to V

. It is capable of driving a load of 2 k Ω in parallel with 1000 pF to GND. The

source and sink capabilities of the output amplifier can be seen in the typical characteristics curves. The slew rate is 1 V/µs with a half-scale settling time of 7 µs with the output unloaded.

I2C Interface

I2C is a two-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device.

The DAC5571 works as a slave and supports the following data transfer modes, as defined in the I2C-Bus

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Start

Condition

SDA

Stop

Condition

SDA

SCL

S P

SCL

DAC5571

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

THEORY OF OPERATION (continued)

Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (3.4 Mbps). The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as HS-mode. The DAC5571 supports 7-bit addressing; 10-bit addressing and general call address are not supported.

F/S-Mode Protocol

• The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 41 . All I2C-compatible devices should recognize a start condition.

• The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit R/ W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 42 ). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 43 ) by pulling the SDA line low during the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a communication link with a slave has been established.

• The master generates further SCL cycles to either transmit data to the slave (R/ W bit 1) or receive data from the slave (R/ W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary.

• To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 41 ). This releases the bus and stops the communication link with the addressed slave. All I2C compatible devices must recognize the stop condition. On the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address.

HS-Mode Protocol

• When the bus is idle, both SDA and SCL lines are pulled high by the pullup devices.

• The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX.

This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS master code, but all devices must recognize it and switch their internal setting to support 3.4 Mbps operation.

• The master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be used to secure the bus in HS-mode.

Figure 41. START and STOP Conditions

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Change of Data Allowed

Data Line

Stable;

Data Valid

SDA

SCL

Not Acknowledge

Acknowledge

1 2 8 9

Clock Pulse for

Acknowledgement

START

Condition

Data Output

by Transmitter

Data Output by Receiver

SCL From

Master

Recognize START or

REPEATED START

Condition

Recognize STOP or

REPEATED START

Condition

Generate ACKNOWLEDGE

Signal

Acknowledgement Signal From Slave

SDA

SCL

MSB

START or

Repeated START

Condition

STOP or

Repeated START

Condition

Clock Line Held Low While

Interrupts are Serviced

1 2 7 8 9

ACK

1 2 3 - 8 9

ACK

Address

R/W

DAC5571

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

THEORY OF OPERATION (continued)

Figure 42. Bit Transfer on the I2C Bus

Figure 43. Acknowledge on the I2C Bus

Figure 44. Bus Protocol

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DAC5571

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

THEORY OF OPERATION (continued)

DAC5571 I2C Update Sequence

The DAC5571 requires a start condition, a valid I2C address, a control-MSB byte, and an LSB byte for a single update. After the receipt of each byte, DAC5571 acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid I2C address selects the DAC5571. The CTRL/MSB byte sets the operational mode of the DAC5571, and the four most significant bits. The DAC5571 then receives the LSB byte containing four least significant data bits followed by four don't care bits. DAC5571 performs an update on the falling edge of the acknowledge signal that follows the LSB byte.

For the first update, DAC5571 requires a start condition, a valid I2C address, a CTRL/MSB byte, an LSB byte. For all consecutive updates, DAC5571 needs a CTRL/MSB byte, and an LSB byte.

Using the I2C high-speed mode (f the first update can be done within 18 clock cycles (CTRL/MSB byte, acknowledge signal, LSB byte, acknowledge signal), at 188.88 KSPS. Using the fast mode (f DAC update rate is limited to 22.22 KSPS. Once a stop condition is received, DAC5571 releases the I2C bus and awaits a new start condition.

Address Byte

MSB LSB

1 0 0 1 1 0 A0 0

= 3.4 MHz), the clock running at 3.4 MHz, each 8-bit DAC update other than

scl

= 400 kHz), clock running at 400 kHz, maximum

scl

The address byte is the first byte received following the START condition from the master device. The first six bits (MSBs) of the address are factory preset to 100110. The next bit of the address is the device select bit A0. The A0 address input can be connected to V

or digital GND, or can be actively driven by TTL/CMOS logic

levels. The device address is set by the state of this pin during the power-up sequence of the DAC5571. Up to two devices (DAC5571) can be connected to the same I2C-Bus without requiring additional glue logic.

Broadcast Address Byte

MSB LSB

1 0 0 1 0 0 0 0

Broadcast addressing is also supported by DAC5571. Broadcast addressing can be used for synchronously updating or powering down multiple DAC5571 devices. Using the broadcast address, DAC5571 responds regardless of the state of the address pin A0.

Control - Most Significant Byte

Most Significant Byte CTRL/MSB[7:0] consists of two zeros, two power-down bits, and four most significant bits of 8-bit unsigned binary D/A conversion data.

Least Significant Byte

Least Significant Byte LSB[7:0] consists of the four least significant bits of the 8-bit unsigned binary D/A conversion data, followed by four don't care bits. DAC5571 updates at the falling edge of the acknowledge signal that follows the LSB[0] bit.

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SLAVE ADDRESS R/W A Ctrl/MS-Byte A LS-Byte A/A P

”0” (write)

Data Transferred

(n* Words + Acknowledge)

Word = 16 Bit

From Master to DAC5571 From DAC5571 to Master

A = Acknowledge (SDA LOW) A = Not Acknowledge (SDA HIGH) S = START Condition Sr = Repeated START Condition P = STOP Condition

DAC5571 I2C-SLAVE ADDRESS:

1 0 0 1 1 0 A0 R/W

MSB LSB

Factory Preset

A0 = I2C Address Pin

Standard- and Fast-Mode:

HS-Master Code R/W A Ctrl/MS-Byte A LS-Byte A/A P

”0” (write)

Data Transferred

(n* Words + Acknowledge)

Word = 16 Bit

High-Speed Mode (HS Mode):

S A Sr Slave Address

HS Mode Continues

F/S-Mode HS Mode F/S Mode

Sr Slave Address

0 0 0 0 1 X X R/W

MSB LSB

HS-Mode Master Code:

0 0 PD1 PD0 D7 D6 D5 D4

MSB LSB

Ctrl/MS-Byte:

D3 D2 D1 D0 X X X X

MSB LSB

LS-Byte:

D7 − D0 = Data Bits

’0’ = Write to DAC5571

DAC5571

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

Figure 45. Master Transmitter Addressing DAC5571 as a Slave Receiver With a 7-Bit Address

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Resistor

String DAC

Power-Down

OUT

Amplifier

Resistor Network

Circuitry

DAC5571

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

POWER-ON RESET

The DAC5571 contains a power-on reset circuit that controls the output voltage during power up. On power up, the DAC register is filled with zeros and the output voltage is 0 V. It remains at a zero-code output until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the DAC output while it is in the process of powering up.

POWER-DOWN MODES

The DAC5571 contains four separate modes of operation. These modes are programmable via two bits (PD1 and PD0). Table 1 shows how the state of these bits correspond to the mode of operation.

Table 1. Modes of Operation for the DAC5571

PD1 PD0 OPERATING MODE

0 0 Normal Operation 0 1 1k Ω to AGND, PWD 1 0 100 k Ω to AGND, PWD 1 1 High Impedance, PWD

When both bits are set to zero, the device works normally with normal power consumption of 150 µA at 5 V. However, for the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only does the supply current fall but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the device is known while in power-down mode. There are three different options: The output is connected internally to AGND through a 1-k Ω resistor, a 100-k Ω resistor, or it is left open-circuited (high impedance). The output stage is illustrated in

Figure 46 .

Figure 46. Output Stage During Power Down

All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC register are unaffected when in power down. The time required to exit power down is typically 2.5 µs for AV 5 V and 5 µs for AV

= 3 V. See the Typical Characteristics section for more information.

CURRENT CONSUMPTION

The DAC5571 typically consumes 150 µA at V can occur due to the digital inputs if V

recommended at the digital inputs to the DAC. In power-down mode, typical current consumption is 200 nA.

= 5 V and 120 µA at V

<< V

. For most efficient power operation, CMOS logic levels are

= 3 V. Additional current consumption

DRIVING RESISTIVE AND CAPACITIVE LOADS

The DAC5571 output stage is capable of driving loads of up to 1000 pF while remaining stable. Within the offset and gain error margins, the DAC5571 can operate rail-to-rail when driving a capacitive load. When the outputs of the DAC are driven to the positive rail under resistive loading, the PMOS transistor of each Class-AB output stage can enter into the linear region. When this occurs, the added IR voltage drop deteriorates the linearity performance of the DAC. This may occur within approximately the top 20 mV of the DAC's digital input-to-voltage output transfer characteristic.

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REF02

15 V

5 V

1.14 mA

SCL

SDA

I2C

Interface

OUT

= 0 V to 5 V

DAC5571

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

OUTPUT VOLTAGE STABILITY

The DAC5571 exhibits excellent temperature stability of 5 ppm/ °C typical output voltage drift over the specified temperature range of the device. This enables the output voltage to stay within a ±25- µV window for a ±1 °C ambient temperature change. Combined with good dc noise performance and true 8-bit differential linearity, the DAC5571 becomes a perfect choice for closed-loop control applications.

APPLICATIONS

USING REF02 AS A POWER SUPPLY FOR THE DAC5571

Due to the extremely low supply current required by the DAC5571, a possible configuration is to use a REF02 +5-V precision voltage reference to supply the required voltage to the DAC5571's supply input as well as the reference input, as shown in Figure 47 . This is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 V. The REF02 outputs a steady supply voltage for the DAC5571. If the REF02 is used, the current it needs to supply to the DAC5571 is 140 µA typical. When a DAC output is loaded, the REF02 also needs to supply the current to the load. The total typical current required (with a 5-mW load on a given DAC output) is: 140 µA + (5 mW/5 V) = 1.14 mA.

The load regulation of the REF02 is typically (0.005% ×V

1.14-mA current drawn from it. This corresponds to a 0.015 LSB error for a 0-V to 5-V output range.

)/mA, which results in an error of 0.285 mV for the

Figure 47. REF02 as Power Supply to DAC5571

LAYOUT

A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies.

The power applied to V converters often has high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output.

As with the GND connection, V from the connection for digital logic until they are connected at the power entry point. In addition, the 1- µF to 10- µF and 0.1- µF bypass capacitors are strongly recommended. In some situations, additional bypassing may be required, such as a 100- µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—all designed to essentially low-pass filter the +5-V supply, removing the high-frequency noise.

should be well regulated and low noise. Switching power supplies and dc/dc

should be connected to a +5-V power supply plane or trace that is separate

PACKAGE OPTION ADDENDUM

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20-Jun-2006

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

DAC5571IDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS &

no Sb/Br)

DAC5571IDBVRG4 ACTIVE SOT-23 DBV 6 3000 Green(RoHS &

no Sb/Br)

DAC5571IDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS &

no Sb/Br)

DAC5571IDBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

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Datasheet DAC5571IDBVTG4, DAC5571 Datasheet (Texas Instruments)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES DESCRIPTION

APPLICATIONS

PIN CONFIGURATIONS

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

TIMING CHARACTERISTICS

Output Amplifier

THEORY OF OPERATION

D/A SECTION

RESISTOR STRING

I2C Interface

F/S-Mode Protocol

HS-Mode Protocol

DAC5571 I2C Update Sequence

POWER-ON RESET

POWER-DOWN MODES

CURRENT CONSUMPTION

DRIVING RESISTIVE AND CAPACITIVE LOADS

OUTPUT VOLTAGE STABILITY

APPLICATIONS

USING REF02 AS A POWER SUPPLY FOR THE DAC5571

LAYOUT