Texas Instruments DAC5571IDBVTG4, DAC5571 Datasheet

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SCLA0

GND

Output

Buffer

Power-Down

Control Logic

Resistor Network

Ref (+) Ref(−)

8-Bit DAC

I2C

Control

Logic

DAC

Power-On

Reset

OUT

SDA

+2.7 V to +5.5 V, I2C INTERFACE, VOLTAGE OUTPUT,

8-BIT DIGITAL-TO-ANALOG CONVERTER

FEATURES DESCRIPTION

• Micropower Operation: 125 µA @ 3 V

• Fast Update Rate: 188 KSPS

• Power-On Reset to Zero

• +2.7-V to +5.5-V Power Supply

• Specified Monotonic by Design

• I2C™ Interface up to 3.4 Mbps

• On-Chip Output Buffer Amplifier, Rail-to-Rail

Operation

• Double-Buffered Input Register

• Address Support for up to Two DAC5571s

• Small 6 Lead SOT 23 Package

• Operation From –40 °C to 105 °C

APPLICATIONS

• Process Control

• Data Acquistion Systems

• Closed-Loop Servo Control

• PC Peripherals power-down mode.

• Portable Instrumentation

The DAC5571 is a low-power, single-channel, 8-bit buffered voltage output DAC. Its on-chip precision output amplifier allows rail-to-rail output swing to be achieved. The DAC5571 utilizes an I2C-compatible, two-wire serial interface that operates at clock rates up to 3.4 Mbps with address support of up to two DAC5571s on the same data bus.

The output voltage range of the DAC is 0 V to V The DAC5571 incorporates a power-on-reset circuit that ensures that the DAC output powers up at zero volts and remains there until a valid write to the device takes place. The DAC5571 contains a power-down feature, accessed via the internal control register, that reduces the current consumption of the device to 50 nA at 5 V.

The low-power consumption of this part in normal operation makes it ideally suited for portable battery operated equipment. The power consumption is less than 0.7 mW at V

DAC7571/6571/5571 are 12/10/8-bit, single-channel I2C DACs from the same family. DAC7574/6574/5574 and DAC7573/6573/5573 are 12/10/8-bit quad-channel I2C DACs. Also see DAC8571/8574 for single/quad-channel, 16-bit I2C DACs.

DAC5571

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

= 5 V reducing to 1 µW in

I2C is a trademark of Philips Corporation.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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A0 SCL SDA

6 5 4

1 2 3

OUT

GND

D571

1 2 3

6 5 4

YMLL

(TOP VIEW)

(BOTTOM VIEW)

Lot Trace Code

DAC5571

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION

PRODUCT PACKAGE DESIG- TRANSPORT MEDIA

PACKAGE

NATOR

DAC5571 SOT23-6 DBV –40°C to +105°C D571

SPECIFIED TEM- PACKAGE ORDERING NUM-

PERATURE RANGE MARKING BER

DAC5571IDBVT 250-Piece Small Tape and Reel DAC5571IDBVR 3000-Piece Tape and Reel

PIN CONFIGURATIONS

PIN NAME DESCRIPTION

1 V 2 GND 3 V

4 SDA Serial Data Input 5 SCL Serial Clock Input 6 A0 Device Address Select

LOT Year (3 = 2003); M onth (1–9 = JAN–SEP; A=OCT,

TRACE B=NOV, C=DEC); LL– Random code generated

CODE: when assembly is requested

PIN DESCRIPTION (SOT23-6)

OUT

Analog output voltage from DAC Ground reference point for all

circuitry Analog Voltage Supply Input

ABSOLUTE MAXIMUM RATINGS

to GND – 0.3 V to +6 V

Digital input voltage to GND –0.3 V to +V V

to GND – 0.3 V to +V

OUT

Operating temperature range –40 °C to +105 °C Storage temperature range –65 °C to +150 °C Junction temperature range (T Power dissipation (TJmax - TA)R Thermal impedance, R Lead temperature, soldering Vapor phase (60s) 215 °C

(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute

maximum conditions for extended periods may affect device reliability.

ΘJA

max) +150 °C

(1)

UNITS

Infrared (15s) 220 °C

+0.3 V

ΘJA

240 °C/W

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DAC5571

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

ELECTRICAL CHARACTERISTICS

= +2.7 V to +5.5 V; RL= 2 k Ω to GND; CL= 200 pF to GND; all specifications –40°C to +105°C unless otherwise noted.

PARAMETER CONDITIONS UNITS

STATIC PERFORMANCE

(1)

Resolution 8 Bits Relative accuracy ±0.5 LSB Differential nonlinearity Assured monotonic by design ±0.25 LSB Zero code error 5 20 mV Full-scale error All ones loaded to DAC register -0.15 -1.25 % of FSR Gain error ±1.25 % of FSR Zero code error drift ± 7 µV/°C Gain temperature coefficient ± 3 ppm of FSR/ °C

OUTPUT CHARACTERISTICS

(2)

Output voltage range 0 V Output voltage settling time 6 8 µs

1/4 Scale to 3/4 scale change (400

RL= ∞

to C00

) ;

Slew rate 1 V/µs

Capacitive load stability

RL= ∞ 470 pF

RL= 2 k Ω 1000 pF Code change glitch impulse 1 LSB Change around major carry 20 nV-s Digital feedthrough 0.5 nV-s DC output impedance 1 Ω

= +5 V 50 mA

Short-circuit current

Power-up time

LOGIC INPUTS

Coming out of power-down mode, V Coming out of power-down mode, V

(3)

= +3 V 20 mA

= +5 V 2.5 µs

= +3 V 5 µs

Input current ±1 µA VINL, Input low voltage V VINH, Input high voltage V

= +3 V 0.3×V

= +5 V 0.7×V

Pin capacitance 3 pF

POWER REQUIREMENTS

IDD(normal operation) DAC active and excluding load current

= +3.6 V to +5.5 V VIH= V

= +2.7 V to +3.6 V VIH= V

and VIL= GND 155 200 µA

and VIL= GND 125 160 µA

IDD(all power-down modes)

= +3.6 V to +5.5 V VIH= V

= +2.7 V to +3.6 V VIH= V

and VIL= GND 0.2 1 µA

and VIL= GND 0.05 1 µA

POWER EFFICIENCY

OUT

= 2 mA, V

LOAD

= +5 V 93 %

(1) Linearity calculated using a reduced code range of 3 to 253; output unloaded. (2) Specified by design and characterization, not production tested. (3) Specified by design and characterization, not production tested.

DAC5571

MIN TYP MAX

2.7 5.5 V

V V

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DAC5571

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

TIMING CHARACTERISTICS

SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

tHD; t

tSU; t

tHD; t

SCL

BUF

STA

LOW

HIGH

STA

DAT

RCL

RCL1

FCL

RDA

FDA

SCL Clock Frequency Standard mode 100 kHz

Fast mode 400 kHz High-speed mode, CB- 100 pF max 3.4 MHz High-Speed mode, CB- 400 pF max 1.7 MHz

Bus Free Time Between a STOP Standard mode 4.7 µs

and START Condition

Fast mode 1.3 µs

Hold Time (Repeated) START Standard mode 4.0 µs

Condition

Fast mode 600 ns

High-speed mode 160 ns

LOW Period of the SCL Clock Standard mode 4.7 µs

Fast mode 1.3 µs High-speed mode, CB- 100 pF max 160 ns High-speed mode, CB- 400 pF max 320 ns

HIGH Period of the SCL Clock Standard mode 4.0 µs

Fast mode 600 ns High-speed mode, CB- 100 pF max 60 ns High-speed mode, CB- 400 pF max 120 ns

Setup Time for a Repeated Standard mode 4.7 µs

START Condition

Fast mode 600 ns

High-speed mode 160 ns

Data Setup Time Standard mode 250 ns

Fast mode 100 ns

High-speed mode 10 ns

Data Hold Time Standard mode 0 3.45 µs

Fast mode 0 0.9 µs High-speed mode, CB- 100 pF max 0 70 ns High-speed mode, CB- 400 pF max 0 150 ns

Rise Time of SCL Signal Standard mode 1000 ns

Fast mode 20 + 0.1C

High-speed mode, CB- 100 pF max 10 40 ns High-speed mode, CB- 400 pF max 20 80 ns

Rise Time of SCL Signal After a Standard mode 1000 ns

Repeated START Condition and

After an Acknowledge BIT

Fast mode 20 + 0.1C

High-speed mode, CB- 100 pF max 10 80 ns High-speed mode, CB- 400 pF max 20 160 ns

Fall Time of SCL Signal Standard mode 300 ns

Fast mode 20 + 0.1C

High-speed mode, CB- 100 pF max 10 40 ns High-speed mode, CB- 400 pF max 20 80 ns

Rise Time of SDA Signal Standard mode 1000 ns

Fast mode 20 + 0.1C

High-speed mode, CB- 100 pF max 10 80 ns High-speed mode, CB- 400 pF max 20 160 ns

Fall Time of SDA Signal Standard mode 300 ns

Fast mode 20 + 0.1C

High-speed mode, CB- 100 pF max 10 80 ns High-speed mode, CB- 400 pF max 20 160 ns

300 ns

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−0.5

−0.4

−0.3

−0.2

−0.1

0.1

0.2

0.3

0.4

0.5

−0.25

−0.2

−0.15

−0.1

−0.05

0.05

0.1

0.15

0.2

0.25

0 32 64 96 128 160 192 224 256

Digital Input Code

VDD = 5 V at 25°C

LE − LSBDLE − LSB

−0.5

−0.4

−0.3

−0.2

−0.1

0.1

0.2

0.3

0.4

0.5

−0.25

−0.2

−0.15

−0.1

−0.05

0.05

0.1

0.15

0.2

0.25

0 32 64 96 128 160 192 224 256

VDD = 5 V at −40°C

Digital Input Code

LE − LSBDLE − LSB

−0.5

−0.4

−0.3

−0.2

−0.1

0.1

0.2

0.3

0.4

0.5

−0.25

−0.2

−0.15

−0.1

−0.05

0.05

0.1

0.15

0.2

0.25

0 32 64 96 128 160 192 224 256

Digital Input Code

VDD = 5 V at 105°C

LE − LSB

DLE − LSB

−16

−8

0 32 64 96 128 160 192 224 256

Digital Input Code

VDD = 5 V, T

= 25°C

Output Error − mV

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

TIMING CHARACTERISTICS (continued)

SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

tSU; t

Setup Time for STOP Condition Standard mode 4.0 µs

STO

Fast mode 600 ns

High-speed mode 160 ns

Capacitive Load for SDA and SCL 400 pF

Pulse Width of Spike Suppressed Fast mode 50 ns

High-speed mode 10 ns

Noise Margin at the HIGH Level Standard mode 0.2V

for Each Connected Device

(Including Hysteresis)

Fast mode

High-speed mode

Noise Margin at the LOW Level for Standard mode 0.1V

Each Connected Device

(Including Hysteresis)

Fast mode

High-speed mode

DAC5571

TYPICAL CHARACTERISTICS: V

At TA= +25°C, +V

= +5 V, unless otherwise noted.

= +5 V

LINEARITY ERROR AND LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR

vs vs

CODE (-40°C) CODE (+25°C )

Figure 1. Figure 2.

LINEARITY ERROR AND ABSOLUTE ERROR

DIFFERENTIAL LINEARITY ERROR

CODE (+105°C)

Figure 3. Figure 4.

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−30

−20

−10

−50−40−30−20 −10 0 10 20 30 40 50 60 70 80 90 100 110

VDD = 5 V

T − Temperature − C

Zero-Scale Error

−30

−20

−10

−50 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 100 110

VDD = 5 V

Full-Scale Error − mV

T − Temperature − C

500

1000

1500

2000

2500

100

110

120

130

140

150

160

170

180

190

200

VDD = 5 V

− Supply Current − A

f − Frequency − Hz

OUT

(V)

SOURCE/SINK

(mA)

5 10 15

DAC Loaded with FF

DAC Loaded with 00

100

200

300

400

500

0 2 32 64 96 128 160 192 224 252 255

Code

VDD = 5 V

Aµ − Supply Current −

100

150

200

250

300

−50 −40−30 −20−10 0 10 20 30 40 50 60 70 80 90 100 110

VDD = 5 V

− Supply Current − I

Aµ

T − Temperature − C

DAC5571

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

TYPICAL CHARACTERISTICS: V

At TA= +25°C, +V

= +5 V, unless otherwise noted.

ZERO-SCALE ERROR FULL-SCALE ERROR

vs vs

TEMPERATURE TEMPERATURE

Figure 5. Figure 6.

IDDHISTOGRAM SOURCE AND SINK CURRENT CAPABILITY

= +5 V (continued)

SUPPLY CURRENT SUPPLY CURRENT

Figure 7. Figure 8.

vs vs

CODE TEMPERATURE

Figure 9. Figure 10.

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100

150

200

250

300

2.7 3.2 3.7 4.2 4.7 5.2 5.7

− Supply Current − I

Aµ

VDD − Supply Voltage − V

2.7

(nA)

VDD (V)

3.2 3.7 4.2 4.7 5.2 5.7

100

90 80 70 60 50 40 30 20 10

+25°C

–40°C

+105°C

CLK (5V/div)

OUT

(1V/div)

Time (1µs/div)

Full−Scale Code Change

00Hto FF

Output Loaded with

2k and200pF to GNDΩ

(µA)

LOGIC

(V)

1 2 3 4 5

2500

2000

1500

1000

500

DAC5571

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

TYPICAL CHARACTERISTICS: V

At TA= +25°C, +V

= +5 V, unless otherwise noted.

SUPPLY CURRENT POWER-DOWN CURRENT

vs vs

SUPPLY VOLTAGE SUPPLY VOLTAGE

Figure 11. Figure 12.

SUPPLY CURRENT FULL-SCALE SETTLING TIME

LOGIC INPUT VOLTAGE

= +5 V (continued)

Figure 13. Figure 14.

+ 14 hidden pages

Texas Instruments DAC5571IDBVTG4, DAC5571 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES DESCRIPTION

APPLICATIONS

PIN CONFIGURATIONS

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

TIMING CHARACTERISTICS