TEXAS INSTRUMENTS CY54FCT841T Technical data
CY54FCT841T, CY74FCT841T
10-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001
D
Function, Pinout, and Drive Compatible
With FCT, F, and AM29841 Logic
D
Reduced VOH (Typically = 3.3 V) Versions of
Equivalent FCT Functions
D
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D
I
Supports Partial-Power-Down Mode
off
Operation
D
Matched Rise and Fall Times
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D
Fully Compatible With TTL Input and
Output Logic Levels
D
High-Speed Parallel Latches
D
Buffered Common Latch-Enable Input
D
3-State Outputs
D
CY54FCT841T
– 32-mA Output Sink Current
– 12-mA Output Source Current
D
CY74FCT841T
– 64-mA Output Sink Current
– 32-mA Output Source Current
CY54FCT841T ...D PACKAGE
CY74FCT841T ...P, Q, OR SO PACKAGE
OE
D
D
D
D
D
D
D
D
D
D
GND
(TOP VIEW)
1
2
0
3
1
4
2
5
3
6
4
7
5
8
6
9
7
10
8
11
9
12
24
23
22
21
20
19
18
17
16
15
14
13
V
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
LE
CC
0
1
2
3
4
5
6
7
8
9
description
The ’FCT841T bus-interface latches are designed to eliminate additional packages required to buffer existing
latches and provide additional data width for wider address/data paths or buses carrying parity . The ’FCT841T
devices are buffered 10-bit-wide versions of the FCT373 function.
The ’FCT841T devices’ high-performance interface is designed for high-capacitance-load drive capability , while
providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance
bus loading in the high-impedance state.
These devices are fully specified for partial-power-down applications using I
outputs, preventing damaging current backflow through the device when it is powered down.
PIN DESCRIPTION
NAME
D I Latch data inputs
LE I
Y O 3-state latch outputs
OE I
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I/O DESCRIPTION
Latch-enable input. The latches are transparent when LE is high.
Input data is latched on the high-to-low transition.
Output-enable control. When OE is low, the outputs are enabled.
When OE
is high, the outputs are in the high-impedance (off) state.
. The I
off
circuitry disables the
off
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2001, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
CY54FCT841T, CY74FCT841T
SOIC
SO
FCT841C
40°C to 85°C
SOIC
SO
FCT841A
Transparent
10-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001
ORDERING INFORMATION
T
A
°
–
–55°C to 125°C CDIP – D Tube 10 CY54FCT841ATDMB
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
°
PACKAGE
QSOP – Q Tape and reel 5.5 CY74FCT841CTQCT FCT841C
–
DIP – P Tube 6.5 CY74FCT841BTPC CY74FCT841BTPC
–
OE LE D O Y
H = High logic level, L = Low logic level, X = Don’t care,
NC = No change, Z = High-impedance state
Tube 5.5 CY74FCT841CTSOC
Tape and reel 5.5 CY74FCT841CTSOCT
Tube 9 CY74FCT841ATSOC
Tape and reel 9 CY74FCT841ATSOCT
INPUTS
H X X X Z
H HLLZZ
H HHHZ
H L X NC Z Latched (Z)
L H L L L
L HHHH
L L X NC NC Latched
†
FUNCTION TABLE
SPEED
(ns)
INTERNAL
OUTPUTS
ORDERABLE
PART NUMBER
FUNCTION
p
TOP-SIDE
MARKING
logic diagram (positive logic)
OE
LE
D
0
1
13
2
LE
Q
D
To Nine Other Channels
23
Y
0
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
CY54FCT841T, CY74FCT841T
10-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range to ground potential –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC input voltage range –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC output voltage range –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC output current (maximum sink current/pin) 120 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 1): P package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
(see Note 2): Q package 61°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): SO package 46°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient temperature range with power applied, T
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The package thermal impedance is calculated in accordance with JESD 51-3.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
–65°C to 135°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
recommended operating conditions (see Note 3)
CY54FCT841T CY74FCT841T
MIN NOM MAX MIN NOM MAX
V
Supply voltage 4.5 5 5.5 4.75 5 5.25 V
CC
V
High-level input voltage 2 2 V
IH
V
Low-level input voltage 0.8 0.8 V
IL
I
High-level output current –12 –32 mA
OH
I
Low-level output current 32 64 mA
OL
T
Operating free-air temperature –55 125 –40 85 °C
A
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
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