Texas Instruments CY29FCT52CTSOCT, CY29FCT52CTSOC, CY29FCT52CTQCT, CY29FCT52CTQC Datasheet
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Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY29FCT52T
SCCS010 - May 1994 - Revised February 2000
Features
• Function, pinout, and drive compatible with FCT,
F Logic and AM2952
• FCT-C speed at 6.3 ns max. (Com’l)
• Reduced V
FCT functions
(typically = 3.3V) versions of equivalent
OH
• Edge-rate control circuitry for significantly improved
noise characteristics
• ESD > 2000V
• Power-off disable feature
• Matched rise and fall times
Logic Block Diagram
CPA
CEA
OEA
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
CE CP
CE CP
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
8-Bit Registered Transceive
• Fully compatible with TTL input and output logic levels
• Sink Current 64 mA (Com’l)
Source Current 32 mA (Com’l)
Functional Description
The CY29FCT52T has two 8-bit back-to-back registers that
store data flowing in both directions between two bidirectional
buses. Separate clock, clock enable, and three-state output
enable signals are provided for each register. Both A outputs
and B outputs are specified to sink 64 mA.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Pin Configurations
OEB
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
CPB
CEB
OEB
CPA
CEA
GND
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
SOIC/QSOP
Top View
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
OEA
CPB
CEB
]
Function Table
[1]
Inputs
Internal Q FunctionD CP CE
X X H NC Hold Data
L
H
Note:
1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care
L
L
L
Load Data
H
Output Control
OE Internal Q Y-Outputs Function
H X Z Disable Outputs
L
L
L
H
L
Enable Outputs
H
Copyright © 2000, Texas Instruments Incorporated
CY29FCT52T
Pin Description
Name Description
A A register inputs or B register outputs.
B B register inputs or A register outputs.
CPA Clockforthe A register.When CEA is LOW,data is entered into the A register on the LOW-to-HIGHtransition of the
CEA ClockEnable fortheAregister.When CEAisLOW,data is entered into theAregisteron the LOW-to-HIGHtransition
OEA OutputEnable for the A register.When OEAis LOW,theAregisteroutputsare enabledontotheB lines.WhenOEA
CPB Clockforthe B register.When CEB is LOW,data is entered into the B register on the LOW-to-HIGHtransition of the
CEB ClockEnable fortheBregister.When CEBisLOW,data is entered into theBregisteron the LOW-to-HIGHtransition
OEB OutputEnable for the B register.When OEBis LOW,theBregisteroutputsare enabledontotheA lines.WhenOEB
CPA signal.
of the CPA signal. When
CEA is HIGH, the A register holds its contents regardless of CPA signal transitions.
is HIGH, the A outputs are in the high impedance state.
CPB signal.
of the CPB signal. When
CEB is HIGH, the B register holds its contents regardless of CPA signal transitions.
is HIGH, the B outputs are in the high impedance state.
Maximum Ratings
[2, 3]
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
DC Output Current (Maximum Sink Current/Pin) ......120 mA
Power Dissipation..........................................................0.5W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Operating Range
Power Applied.............................................–65°C to +135°C
Supply Voltage to Ground Potential...............–0.5V to +7.0V
DC Input Voltage............................................–0.5V to +7.0V
Range Range
Commercial All –40°C to +85°C 5V ± 5%
DC Output Voltage.........................................–0.5V to +7.0V
Notes:
2. Unless otherwise noted, these limits are over the operating free-air temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V
4. TA is the “instant on” case temperature.
or ground.
CC
Ambient
Temperature V
CC
2
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Typ.
V
V
V
V
V
V
I
I
I
IH
I
IL
I
OS
I
OFF
OH
OL
IH
IL
H
IK
Output HIGH Voltage VCC=Min., IOH=–32 mA Com’l 2.0 V
VCC=Min., IOH=–15 mA Com’l 2.4 3.3 V
Output LOW Voltage VCC=Min., IOL=64 mA Com’l 0.3 0.55 V
Input HIGH Voltage 2.0 V
Input LOW Voltage 0.8 V
Hysteresis
[6]
All inputs 0.2 V
Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 –1.2 V
Input HIGH Current VCC=Max., VIN=V
CC
Input HIGH Current VCC=Max., VIN=2.7V ±1 µA
Input LOW Current VCC=Max., VIN=0.5V ±1 µA
Output Short Circuit Current
Power-Off Disable VCC=0V, V
[7]
VCC=Max., V
=0.0V –60 –120 –225 mA
OUT
=4.5V ±1 µA
OUT
CY29FCT52T
[5]
Max. Unit
5 µA
Capacitance
Parameter Description Typ.
C
IN
C
OUT
Notes:
5. Typical values are at V
6. This parameter is specified but not tested.
7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatusand/or sample
and hold techniques are preferablein order to minimize internal chipheating and more accurately reflect operational values. Otherwise prolonged shortingof
a high output may raise the chip temperature well abovenormal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, I
[6]
Input Capacitance 5 10 pF
Output Capacitance 9 12 pF
=5.0V, TA=+25˚C ambient.
CC
tests should be performed last.
OS
[5]
Max. Unit
3
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