Texas Instruments CY29FCT520ATSOC, CY29FCT520ATPC, CY29FCT520CTSOCT, CY29FCT520CTSOC, CY29FCT520BTSOCT Datasheet

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.

CY29FCT520T

SCCS011A - May 1994 - Revised April 2000

Features

• Function, pinout, and drive compatible with FCT, F

Logic, and AM29520

• FCT-C speed at 6.0 ns max. (Com’l),

FCT-B speed at 7.5 ns max. (Com’l),
FCT-A speed at 14.0 ns max. (Com’l)

• Reduced V

FCT functions

• Edge-rate control circuitry for significantly improved

noise characteristics

• Power-Off disable feature

• Matched rise and fall times

• Fully compatible with TTL input and output logic levels

• ESD > 2000V

• Sink current 64 mA (Com’l), 32 mA (Mil)
Source current 32 mA (Com’l), 12 mA (Mil)

• Single and dual pipeline operation modes

• Multiplexed data inputs and outputs

Logic Block Diagram Pin Configurations

(typically = 3.3V) versions of equivalent

OH

D

0–D7

8

Multi-Level Pipeline Register

Functional Description

The CY29FCT520T devices are multilevel 8-bit-wide pipeline
registers. The devices consist of four registers, A1, A2, B1,
and B2, which are configured by the instruction inputs I
a single 4-level pipeline or as two two-level pipelines. The
contents of any register may be read at the multiplexed out­put at any time by using the mux-selection controls S
S

.

1

The pipeline registers are positive edge triggered and data is
shifted by the rising edge of the clock input. Instruction I=0
selects the four-level pipeline mode. Instruction I=1 selects the
two-level B pipeline while I=2 selects the two-level A pipeline.
I=3 is the HOLD instruction; no shifting is performed by the
clock in this mode.

In the two-level operation mode, data is shifted from level 1 to
level 2 and new data is loaded into level 1.

The outputs are designed with a power-off disable feature to
allow for liv e insertion of boards.

DIP, SOIC, QSOP, CDIP

INSTRUCTION

I

0

I

1

CLOCK

MUX S

SEL S

REGISTER
CONTROLS

0

1

OCTAL REG

A1

OCTAL REG

A2

MUX

MUX

OCTAL REG

B1

OCTAL REG

B2

D
D
D
D
D
D
D
D

CLK

GND

I

0

I

1
0

1
2
3
4
5
6
7

Top View

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15

14
13

V
S

S
Y

Y
Y

Y
Y
Y
Y
Y
OE

as

0,I1

and

0

CC
0

1
0

1
2

3
4
5
6
7

OE

8

Y0–Y

7

Pipeline Instruction Table

I = 0 I = 1 I = 2 I = 3

= 0 I0 = 0 I1 = 0 I0 = 1 I1 = 1 I0 = 0 I1 = 1 I0 = 1

I

1

A1

A2

B1

B2

A1

A2

B1

B2

A1

A2

Single four-level Dual two-level Hold

B1

B2

A1

A2

B1

B2

Copyright © 2000, Texas Instruments Incorporated

CY29FCT520T

Output Selection Mux Table

Inputs.

S

Maximum Ratings

(Above which the useful life may be impaired. For user
guidelines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

S

1

1
1
0
0

Output

0

1
0
1
0

A1
A2
B1
B2

[1, 2]

Supply Voltage to Ground Potential............... –0.5V to +7.0V

DC Input Voltage ........................................... –0.5V to +7.0V

DC Output Voltage......................................... –0.5V to +7.0V

DC Output Current (Maximum Sink Current/Pin) ......120 mA

Power Dissipation..........................................................0.5W

Static Discharge Voltage............................................>2001V

(per MIL-STD-883, Method 3015)

Operating Range

Range

Temperature

Commercial –40°C to +85°C 5V ± 5%
Military –55°C to +125°C 5V ± 10%

Ambient

[3]

Power Applied.............................................–65°C to +135°C

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Typ.

V

V

V
V
V
V
I

I

I

IH

I

IL

I

OZH

I

OZL

I

OS

I

OFF

OH

OL

IH
IL
H
IK

Output HIGH Voltage VCC=Min., IOH=–32 mA Com’l 2.0 V

VCC=Min., IOH=–15 mA Com’l 2.4 3.3 V
VCC=Min., IOH=–12 mA Mil 2.4 3.3 V

Output LOW Voltage VCC=Min., IOL=64 mA Com’l 0.3 0.55 V

VCC=Min., IOL=32 mA Mil 0.3 0.55 V
Input HIGH Voltage 2.0 V
Input LOW Voltage 0.8 V
Hysteresis

[5]

All inputs 0.2 V
Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 –1.2 V
Input HIGH Current VCC=Max., VIN=V

CC

Input HIGH Current VCC=Max., VIN=2.7V ±1 µA
Input LOW Current VCC=Max., VIN=0.5V ±1 µA
Off State HIGH-Level Output Current V
Off State LOW-Level

Output Current
Output Short Circuit Current

[6]

Power-Off Disable VCC=0V, V

Max., V

CC=

VCC=Max., V

VCC=Max., V

OUT

=2.7V 10 µA

OUT

= 0.5V –10 µA

OUT

=0.0V –60 –120 –225 mA

OUT

=4.5V ±1 µA

[4]

Max. Unit

V

CC

5 µA

Capacitance

Parameter Description Test Conditions Typ.

C

IN

C

OUT

Notes:

1. Unless otherwise noted, these limits are over the operating free-air temperature range.

2. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V
is the “instant on” case temperature.

3. T

A

4. Typical values are at V

5. This parameter is specified but not tested.

6. Not more than oneoutput should be shorted at a time. Durationof short should notexceed one second. The useofhigh-speed test apparatus and/or sample

and hold techniquesare preferable in order tominimize internal chip heating and more accuratelyreflect operational values. Otherwiseprolongedshorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, I

[5]

[4]

Max. Unit

Input Capacitance 5 10 pF
Output Capacitance 9 12 pF

or ground.

CC

=5.0V, TA=+25˚C ambient.

CC

tests should be performed last.

OS

2

Power Supply Characteristics

Parameter Description Test Conditions Typ.

I

CC

∆I

CC

I

CCD

I

C

Notes:

7. Per TTL driven input (V

8. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

9. I

C

IC=ICC+∆ICCDHNT+I
I

CC

∆I
D
N
I

CCD

f

0

f

1

N
All currents are in milliamps and all frequencies are in megahertz.

10. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.

Quiescent Power Supply Current VCC=Max., VIN<0.2V, VIN>VCC–0.2V 0.1 0.2 mA
Quiescent Power Supply Current

VCC=Max., VIN=3.4V, f1=0, Outputs Open

[7]

(TTL inputs HIGH)

[9]

[8]

VCC=Max.,One InputToggling,50%DutyCycle,
Outputs Open,
V

<0.2V or VIN>VCC–0.2V

IN

OE=GND,

VCC=Max., 50% Duty Cycle, Outputs Open,
f

=10 MHz, One Bit Toggling at f1=5 MHz,

0

OE=GND, VIN<0.2V or VIN>VCC–0.2V

Dynamic Power Supply Current

Total Power Supply Current

VCC=Max., 50% Duty Cycle, Outputs Open,
f

=10 MHz, One Bit Toggling at f1=5 MHz,

0

OE=GND, VIN=3.4V or VIN=GND
VCC=Max., 50% Duty Cycle, Outputs Open,

f

=10 MHz, Eight Bits Toggling at f1=5 MHz,

0

OE=GND, VIN<0.2V or VIN>VCC–0.2V
VCC=Max., 50% Duty Cycle, Outputs Open,

f

=10 MHz, Eight Bits Toggling at f1=5 MHz,

0

OE=GND, VIN=3.4V or VIN=GND

=3.4V); all other inputs at VCC or GND.

IN

=I

QUIESCENT

= Quiescent Current with CMOS input levels
= Power Supply Current for a TTL HIGH input (VIN=3.4V)

CC

= Duty Cycle for TTL inputs HIGH

H

= Number of TTL inputs at D

T

= Dynamic Current caused by an input transition pair (HLH or LHL)
= Clock frequency for registered devices, otherwise zero
= Input signal frequency
= Number of inputs changing at f

1

+ I

INPUTS

CCD(f0

+ I

DYNAMIC

/2 + f1N1)

H

1

CY29FCT520T

[4]

Max. Unit

0.5 2.0 mA

0.06 0.12 mA/MHz

0.7 1.4 mA

1.2 3.4 mA

2.8 5.6

5.1 14.3

[10]

[10]

mA

mA

3

CY29FCT520T

Switching Characteristics Over the Operating Range

CY29FCT520AT CY29FCT520BT

Military Commercial Military Commercial

Parameter Description

t

PLH

t

PHL

t

PLH

t

PHL

t

S

t

H

t

S

t

H

t

PHZ

t

PLZ

t

PZH

t

PZL

t

W

Propagation Delay
Clock to Data Output

Propagation Delay
S

, S1to Data Output

0

Set-Up Time Input Data
to Clock

Hold Time Input Data to Clock 2.0 2.0 2.0 2.0 ns 4
Set-Up Time Instruction

(Reg. Enable) to Clock
Hold Time Instruction

(Reg. Enable) to Clock
Output Disable Time 1.5 13.0 1.5 12.0 1.5 7.5 1.5 7.0 ns 1, 7, 8

Output Enable Time 1.5 16.0 1.5 15.0 1.5 8.0 1.5 7.5 ns 1, 7, 8

Clock Pulse Width,

[5]

HIGH or LOW

Min Max. Min Max. Min. Max. Min. Max.

2.0 16.0 2.0 14.0 2.0 8.0 2.0 7.5 ns 1, 5

2.0 15.0 2.0 13.0 2.0 8.0 2.0 7.5 ns 1, 5

6.0 5.0 2.8 2.5 ns 4

6.0 5.0 4.5 4.0 ns 4

2.0 2.0 2.0 2.0 ns 4

8.0 7.0 6.0 5.5 ns 5

[11]

Unit

Fig.

No.

[12]

Parameter Description

t

PLH

t

PHL

t

PLH

t

PHL

t

S

t

H

t

S

t

H

t

PHZ

t

PLZ

t

PZH

t

PZL

t

W

Notes:

11. Minimum limits are specified but not tested on Propagation Delays.

12. See “Parameter Measurement Information” in the General Information section.

Propagation Delay Clock to Data Output 2.0 6.0 ns 1, 5

Propagation Delay S0, S1to Data Output 2.0 6.0 ns 1, 5

Set-Up Time Input Data to Clock 2.5 ns 4
Hold Time Input Data to Clock 2.0 ns 4
Set-Up Time Instruction (Reg. Enable) to Clock 4.0 ns 4
Hold Time Instruction (Reg. Enable) to Clock 2.0 ns 4
Output Disable Time 1.5 6.0 ns 1, 7, 8

Output Enable Time 1.5 6.0 ns 1, 7, 8

Clock Pulse Width,

[5]

HIGH or LOW 5.5 ns 5

CY29FCT520CT

Commercial

Min. Max.

Unit Fig. No.

[12]

4

CY29FCT520T

Ordering Information

Speed

(ns) Ordering Code

6.0 CY29FCT520CTSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC Commercial

7.5 CY29FCT520BTSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC Commercial

8.0 5962-9220504MLA
(CY29FCT520BTDMB)

14.0 CY29FCT520ATPC P13/13A 24-Lead (300-Mil) Molded DIP Commercial
CY29FCT520ATSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC

16.0 5962-9220502MLA
(CY29FCT520ATDMB)

Package

Name Package Type

D14 24-Lead (300-Mil) CDIP Military

D14 24-Lead (300-Mil) CDIP Military

Operating

Range

5

Package Diagrams

CY29FCT520T

24-Lead (300-Mil) CDIP D14

MIL-STD-1835 D- 9 Config.A

24-Lead (300-Mil) Molded DIP P13/P13A

6

Package Diagrams (continued)

CY29FCT520T

24-Lead Quarter Size Outline Q13

24-Lead (300-Mil) Molded SOIC

S13

7

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Copyright  2000, Texas Instruments Incorporated