Texas Instruments CSD97374Q4M, FX021 Schematic

0 5 10 15 20 25

40

50

60

70

80

90

100

0

2

4

6

8

10

12

Output Current (A)

Efficiency (%)

Power Loss (W)

VGS = 5V VIN = 12V V

OUT

= 1.8V

L

OUT

= .29µH

f

S

W

= 500kHz

TA = 25ºC

G001

CSD97374Q4M

Not Recommended For New Designs

www.ti.com

SLPS382C –JANUARY 2013–REVISED JULY 2013

Synchronous Buck NexFET™ Power Stage

1

FEATURES APPLICATIONS

23

• Over 92% System Efficiency at 15A • Ultrabook/Notebook DC/DC Converters

• Max Rated Continuous Current 25A, Peak 60A • Multiphase Vcore and DDR Solutions

• High Frequency Operation (up to 2 MHz) • Point-of-Load Synchronous Buck in

• High Density - SON 3.5x4.5-mm Footprint

• Ultra Low Inductance Package

• System Optimized PCB Footprint

• Ultra Low Quiescent (ULQ) Current Mode

• 3.3V and 5V PWM Signal Compatible

• Diode Emulation Mode with FCCM

• Input Voltages up to 24V

• Three-State PWM Input

• Integrated Bootsrap Diode

• Shoot Through Protection

• RoHS Compliant – Lead Free Terminal Plating

• Halogen Free

Networking, Telecom, and Computing Systems

ORDERING INFORMATION

Device Package Media Qty Ship

CSD97374Q4M 2500

SON 3.5 × 4.5-mm 13-Inch Tape and

Plastic Package Reel Reel

DESCRIPTION

The CSD97374Q4M NexFET™ Power Stage is a highly optimized design for use in a high power, high density Synchronous Buck converter. This product integrates the driver IC and NexFET technology to complete the power stage switching function. The driver IC has a built-in selectable diode emulation function that enables DCM operation to improve light load efficiency. In addition, the driver IC supports ULQ mode that enables Connected Standby for Windows™ 8 . With the PWM input in tri-state, quiescent current is reduced to 130 µA, with immediate response. When SKIP# is held at tri-state, the current is reduced to 8 µA (typically 20 µs is required to resume switching). This combination produces a high current, high efficiency, and high speed switching device in a small 3.5 × 4.5-mm outline package. In addition, the PCB footprint has been optimized to help reduce design time and simplify the completion of the overall system design.

1

2NexFET is a trademark of Texas Instruments. 3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Figure 1. Application Diagram Figure 2. Efficiency and Power Loss

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

CSD97374Q4M

Not Recommended For New Designs

SLPS382C –JANUARY 2013–REVISED JULY 2013

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

www.ti.com

ABSOLUTE MAXIMUM RATINGS

(1)

TA= 25°C (unless otherwise noted)

VALUE

MIN MAX

VINto P

GND

VSWto P VSWto P VDDto P

, VINto V

GND

, VINto VSW(<10ns) -7 33 V

GND

PWM, SKIP# to P BOOT to P BOOT to P

GND

(<10ns) -2 38 V

GND

SW

GND

-0.3 30 V

–0.3 6 V –0.3 6 V –0.3 35 V

BOOT to BOOT_R –0.3 6 V

ESD Rating

Power Dissipation, P Operating Temperature Range, T Storage Temperature Range, T

Human Body Model (HBM) 2000 V Charged Device Model (CDM) 500 V

D

J

STG

-40 150 °C

–55 150 °C

8 W

(1) Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only

and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability.

UNIT

RECOMMENDED OPERATING CONDITIONS

TA= 25° (unless otherwise noted)

Parameter Conditions MIN MAX UNIT

Gate Drive Voltage, V Input Supply Voltage, V Continuous Output Current, I Peak Output Current, I Switching Frequency, f

DD

IN

OUT-PK

SW

OUT (2)

VIN= 12V, VDD= 5V, V fSW= 500kHz, L

C

= 0.1µF (min) 2000 kHz

BST

OUT

= 1.8V, 25 A

OUT

= 0.29µH

(1)

On Time Duty Cycle 85 % Minimum PWM On Time 40 ns Operating Temperature –40 125 °C

(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VINto P (2) System conditions as defined in Note 1. Peak Output Current is applied for tp= 10ms, duty cycle ≤ 1%

4.5 5.5 V 24 V

60 A

pins.

GND

THERMAL INFORMATION

TA= 25°C (unless otherwise noted)

R

θJC

R

θJB

(1) R (2) R

Thermal Resistance, Junction-to-Case (Top of package) Thermal Resistance, Junction-to-Board

is determined with the device mounted on a 1-inch² (6.45 -cm²), 2-oz (.071-mm thick) Cu pad on a 1.5-inch x 1.5-inch, 0.06-inch

θJC

(1.52-mm) thick FR4 board.

value based on hottest board temperature within 1mm of the package.

θJB

PARAMETER MIN TYP MAX UNIT

(1)

(2)

22.8 °C/W

2.5 °C/W

CSD97374Q4M

Not Recommended For New Designs

www.ti.com

ELECTRICAL CHARACTERISTICS

TA= 25°C, VDD= POR to 5.5V (unless otherwise noted)

PARAMETER CONDITIONS MIN TYP MAX UNIT

P

LOSS

Power Loss

V

IN

VINQuiescent Current, I

V

DD

(1)

(2)

Q

Standby Supply Current, I

Operating Supply Current, I

DD

VIN= 12V, VDD= 5V, V fSW= 500kHz, L

OUT

VIN= 19V, VDD= 5V, V fSW= 500kHz, L

OUT

VIN= 19V, VDD= 5V, V fSW= 500kHz, L

OUT

PWM=Floating, VDD= 5V, VIN= 24V 1 µA

PWM = Float, SKIP# = VDDor 0V 130 µA SKIP# = Float 8 µA PWM = 50% Duty cycle, fSW= 500kHz 8.2 mA

POWER-ON RESET AND UNDER VOLTAGE LOCKOUT

Power-On Reset, VDDRising 4.15 V UVLO, VDDFalling 3.7 V Hysteresis 0.2 mV

PWM and SKIP# I/O Specifications

Input Impedance, R

Logic Level High, V Logic Level Low, V Hysteresis, V

IH

Tri-State Voltage, V

I

IH

IL

TS

Pull Down (to GND) 800

Pull Up to V

DD

Tri-state Activation Time (falling) PWM, t

THOLD(off1)

Tri-state Activation Time (rising) PWM, t

THOLD(off2)

Tri-state Activation Time (falling) SKIP#, t

TSKF

Tri-state Activation Time (rising) SKIP#, t

TSKR

Tri-state Exit Time PWM, t Tri-state Exit Time SKIP#, t

3RD(PWM)

3RD(SKIP#)

(2)

BOOTSTRAP SWITCH

Forward Voltage, V Reverse Leakage, I

FBST RLEAK

(2)

IF= 10mA 120 240 mV V

– VDD= 25V 2 µA

BST

= 1.8V, I

OUT

= 0.29µH , TJ= 25°C

= 1.8V, I

OUT

= 0.29µH , TJ= 25°C

= 1.8V, I

OUT

= 0.29µH , TJ= 125°C

SLPS382C –JANUARY 2013–REVISED JULY 2013

= 15A,

2.3 W

2.5 W

2.8 W

1700

2.65

0.2

1.3 2 60

60

1

0.6

100 ns

50 µs

kΩ

V

ns

µs

(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VINto P (2) Specified by design

GND

pins.

0 400 800 1200 1600 2000 2400

0.95

1

1.05

1.1

1.15

1.2

1.25

1.3

1.35

1.4

1.45

−0.9

0.0

0.9

1.8

2.7

3.5

4.4

5.3

6.2

7.1

8.0

Switching Frequency (kHz)

Power Loss, Normalized

SOA Temperature Adj (ºC)

VIN = 12V VDD = 5V V

OUT

= 1.8V

L

OUT

= 0.29µH

I

OUT

= 25A

G001

3 5 7 9 11 13 15 17 19 21 23

0.95

1

1.05

1.1

1.15

1.2

1.25

−0.9

0.0

0.9

1.8

2.7

3.5

4.4

Input Voltage (V)

Power Loss, Normalized

SOA Temperature Adj (ºC)

VDD = 5V V

OUT

= 1.8V

L

OUT

= 0.29µH fSW = 500kHz I

OUT

= 25A

G001

0

5

10

15

20

25

30

0

10 20 30 40 50 60 70 80 90

Ambient Temperature (ºC)

Output Current (A)

400LFM 200LFM 100LFM Nat Conv

VIN = 12V VGS = 5V V

OUT

= 1.8V

f

S

W

= 500kHz

L

OUT

= 0.29µH

G001

0

5

10

15

20

25

30

0

20 40 60 80 100 120 140

Board Temperature (ºC)

Output Current (A)

Typ Max

VIN = 12V VDD = 5V V

OUT

= 1.8V

f

S

W

= 500kHz

L

OUT

= 0.29µH

G001

0

1

2

3

4

5

6

7

8

9

1

3 5 7 9 11 13 15 17 19 21 23 25

Output Current (A)

Power Loss (W)

Typ Max

VIN = 12V VDD = 5V V

OUT

= 1.8V fSW = 500kHz L

OUT

= 0.29µH

G001

0.5

0.6

0.7

0.8

0.9

1

1.1

1.2

−75

−50 −25 0 25 50 75 100 125 150 Junction Temperature (ºC)

Power Loss, Normalized

VIN = 12V VGS = 5V V

OUT

= 1.8V fSW = 500kHz L

OUT

= 0.29µH

G001

CSD97374Q4M

Not Recommended For New Designs

SLPS382C –JANUARY 2013–REVISED JULY 2013

Figure 3. Power Loss vs Output Current Figure 4. Power Loss vs Temperature

www.ti.com

TYPICAL CHARACTERISTICS

TJ= 125°C, unless stated otherwise.

Figure 5. Safe Operating Area – PCB Horizontal Mount

Figure 7. Normalized Power Loss vs Frequency Figure 8. Normalized Power Loss vs Input Voltage

(1)

Figure 6. Typical Safe Operating Area

(1)

0

5

10

15

20

25

30

35

40

45

0

400 800 1200 1600 2000 2400

Switching Frequency (kHz)

Driver Current (mA)

VIN = 12V VDD = 5V V

OUT

= 1.8V L

OUT

= 0.29µH I

OUT

= 25A

G000

8.5

9

9.5

10

10.5

11

−75

−50 −25 0 25 50 75 100 125 150 Junction Temperature (°C)

Driver Current (mA)

VIN = 12V VDD = 5V V

OUT

= 1.8V

L

OUT

= 0.29µH

I

OUT

= 25A

G000

0 0.5 1 1.5 2 2.5 3 3.5 4

0.6

0.7

0.8

0.9

1

1.1

1.2

1.3

1.4

1.5

−7.2

−5.4

−3.6

−1.8

0

1.8

3.6

5.4

7.2

9

Output Voltage (V)

Power Loss, Normalized

SOA Temperature Adj (ºC)

VIN = 12V VDD = 5V fSW = 500kHz L

OUT

= 0.29µH

I

OUT

= 25A

G001

0 100 200 300 400 500 600 700 800 900 10001100

0.9

0.95

1

1.05

1.1

1.15

1.2

1.25

−1.8

−0.9

0

0.9

1.8

2.7

3.5

4.4

Output Inductance (nH)

Power Loss, Normalized

SOA Temperature Adj (ºC)

VIN = 12V VDD = 5V V

OUT

= 1.8V fSW = 500kHz I

OUT

= 25A

G001

www.ti.com

Not Recommended For New Designs

TJ= 125°C, unless stated otherwise.

Figure 9. Normalized Power Loss vs Output Voltage Figure 10. Normalized Power Loss vs Output Inductance

CSD97374Q4M

SLPS382C –JANUARY 2013–REVISED JULY 2013

TYPICAL CHARACTERISTICS (continued)

Figure 11. Driver Current vs Frequency Figure 12. Driver Current vs Temperature

1. The Typical CSD97374Q4M System Characteristic curves are based on measurements made on a PCB design with dimensions of 4.0" (W) x 3.5" (L) x 0.062" (T) and 6 copper layers of 1 oz. copper thickness. See the Application

Information section for detailed explanation.

PWM

8

7

6

5

4

9

P

GND

1

V

IN

SKIP#

V

SW

V

DD

P

GND

BOOT

BOOT_R

2

3

CSD97374Q4M

Not Recommended For New Designs

SLPS382C –JANUARY 2013–REVISED JULY 2013

PIN CONFIGURATION

Figure 13. Top View

PIN DESCRIPTION

NO. NAME

1 SKIP# This pin enables the Diode Emulation function. When this pin is held Low, Diode Emulation Mode is enabled for the

Sync FET. When SKIP# is High, the CSD97374Q4M operates in Forced Continuous Conduction Mode. A tri-state voltage on SKIP# puts the driver into a very low power state.

2 V

DD

3 P

GND

4 V

SW

5 V

IN

6 BOOT_R 7 BOOT

Supply Voltage to Gate Drivers and internal circuitry. Power Ground, Needs to be connected to Pin 9 and PCB Voltage Switching Node – pin connection to the output inductor. Input Voltage Pin. Connect input capacitors close to this pin.

Bootstrap capacitor connection. Connect a minimum 0.1µF 16V X5R, ceramic cap from BOOT to BOOT_R pins. The bootstrap capacitor provides the charge to turn on the Control FET. The bootstrap diode is integrated.

8 PWM Pulse Width modulated 3-state input from external controller. Logic Low sets Control FET gate low and Sync FET gate

high. Logic High sets Control FET gate high and Sync FET gate Low. Open or High Z sets both MOSFET gates low if greater than the 3-State Shutdown Hold-off Time (t

9 P

GND

Power Ground

DESCRIPTION

)

3HT

www.ti.com

UDG-12218

V

UVLO_H

V

UVLO_L

V

VDD

Driver On

www.ti.com

Not Recommended For New Designs

CSD97374Q4M

SLPS382C –JANUARY 2013–REVISED JULY 2013

Figure 14. Functional Block Diagram

FUNCTIONAL DESCRIPTION

POWERING CSD97374Q4M AND GATE DRIVERS

An external VDDvoltage is required to supply the integrated gate driver IC and provide the necessary gate drive power for the MOSFETS. A 1µF 10V X5R or higher ceramic capacitor is recommended to bypass VDDpin to P

. A bootstrap circuit to provide gate drive power for the Control FET is also included. The bootstrap supply

GND

to drive the Control FET is generated by connecting a 100nF 16V X5R ceramic capacitor between BOOT and BOOT_R pins. An optional R

resistor can be used to slow down the turn on speed of the Control FET and

BOOT

reduce voltage spikes on the VSWnode. A typical 1Ω to 4.7Ω value is a compromise between switching loss and VSWspike amplitude.

Undervoltage Lockout Protection (UVLO)

The undervoltage lockout (UVLO) comparator evaluates the VDD voltage level. As V FET and Sync FET gates hold actively low at all times until V

reaches the higher UVLO threshold (V

VDD

Then the driver becomes operational and responds to PWM and SKIP# commands. If VDD falls below the lower UVLO threshold (V

UVLO_L

= V

UVLO_H

– Hysteresis), the device disables the driver and drives the outputs of the

Control FET and Sync FET gates actively low. Figure 15 shows this function.

CAUTION

Do not start the driver in the very low power mode (SKIP# = Tri-state).

rises, both the Control

VDD

UVLO_H

).,

Figure 15. UVLO Operation

Texas Instruments CSD97374Q4M, FX021 Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES APPLICATIONS

DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

THERMAL INFORMATION

ELECTRICAL CHARACTERISTICS

TYPICAL CHARACTERISTICS

PIN CONFIGURATION

FUNCTIONAL DESCRIPTION

POWERING CSD97374Q4M AND GATE DRIVERS

Undervoltage Lockout Protection (UVLO)