Texas Instruments CSD95375Q4M Schematic [ru]
V
CC
PWM1
+I
s1
-I
s2
+NTC
-NTC
+I
s2
-I
s2
PWM2
V
OUT
SS
RT
V
CC
V
OUT
V
OUT
V
IN
Multi-Phase
Controller
CSD95375
CSD95375
P
GND
0 5 10 15 20 25
30
40
50
60
70
80
90
100
0
1
2
3
4
5
6
7
Output Current (A)
Efficiency (%)
Power Loss (W)
VDD = 5V
VIN = 12V
V
OUT
= 1.8V
L
OUT
= .29µH
fSW = 500kHz
TA = 25ºC
G001
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CSD95375Q4M
SLPS430A –AUGUST 2013–REVISED AUGUST 2014
CSD95375Q4M Synchronous Buck NexFET™ Power Stage
1 Features 2 Applications
1
• 93% System Efficiency at 15 A
• Max Rated Continuous Current 25 A, Peak 60 A • Multiphase Vcore and DDR Solutions
• High Frequency Operation (up to 2 MHz) • Point of Load Synchronous Buck in Networking,
• High Density - SON 3.5 × 4.5-mm Footprint
• Ultra-Low Inductance Package
• System Optimized PCB Footprint
• Ultra-Low Quiescent (ULQ) Current Mode
• 3.3 V and 5 V PWM Signal Compatible
• Diode Emulation Mode with FCCM
• Tri-State PWM Input
• Integrated Bootstrap Diode
• Shoot Through Protection
• RoHS Compliant – Lead-Free Terminal Plating
• Halogen Free
• Ultrabook/Notebook DC/DC Converters
Telecom, and Computing Systems
3 Description
The CSD95375Q4M NexFET™ Power Stage is a
highly optimized design for use in a high power, high
density Synchronous Buck converter. This product
integrates the driver IC and NexFET technology to
complete the power stage switching function. The
driver IC has a built-in selectable diode emulation
function that enables DCM operation to improve light
load efficiency. In addition, the driver IC supports
ULQ mode that enables Connected Standby for
Windows™ 8. With the PWM input in tri-state,
quiescent current is reduced to 130 µA, with
immediate response. When SKIP# is held at tri-state,
the current is reduced to 8 µA (typically 20 µs is
required to resume switching). This combination
produces a high current, high efficiency, and high
speed switching device in a small 3.5 × 4.5-mm
outline package. In addition, the PCB footprint has
been optimized to help reduce design time and
simplify the completion of the overall system design.
SPACER
Application Diagram Typical Power Stage Efficiency and Power Loss
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Device Information
Device Media Qty Package Ship
CSD95375Q4M 13-Inch Reel 2500
CSD95375Q4MT 7-Inch Reel 250
(1)
SON 3.5 × 4.5 mm Tape and
Plastic Package Reel
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
CSD95375Q4M
SLPS430A –AUGUST 2013–REVISED AUGUST 2014
www.ti.com
Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration................................................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 Recommended Operating Conditions....................... 4
6.3 Thermal Information.................................................. 4
6.4 Electrical Characteristics........................................... 5
6.5 Typical Characteristics.............................................. 6
7 Detailed Description .............................................. 8
7.1 Functional Block Diagram......................................... 8
7.2 Feature Description................................................... 8
7.3 Undervoltage Lockout Protection (UVLO)................. 8
7.4 PWM Pin................................................................... 9
7.5 SKIP# Pin.................................................................. 9
7.6 Integrated Boost-Switch.......................................... 10
8 Application and Implementation ........................ 11
8.1 Application Information............................................ 11
9 Layout ................................................................... 13
9.1 Layout Guidelines ................................................... 13
9.2 Layout Example ...................................................... 14
10 Device and Documentation Support................. 15
10.1 Trademarks........................................................... 15
10.2 Electrostatic Discharge Caution............................ 15
10.3 Glossary................................................................ 15
11 Mechanical, Packaging, and Orderable
Information........................................................... 16
11.1 Mechanical Drawing.............................................. 17
11.2 Recommended PCB Land Pattern........................ 18
11.3 Recommended Stencil Opening........................... 18
4 Revision History
Changes from Original (August 2013) to Revision A Page
• Added 7" inch reel information .............................................................................................................................................. 1
• Increased VINfrom 14.5 V to 16 V ......................................................................................................................................... 4
2 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated
PWM
8
7
6
5
4
9
P
GND
1
V
IN
SKIP#
V
SW
V
DD
P
GND
BOOT
BOOT_R
2
3
CSD95375Q4M
www.ti.com
SLPS430A –AUGUST 2013–REVISED AUGUST 2014
5 Pin Configuration
Pin Description
PIN
NO. NAME
1 SKIP# This pin enables the Diode Emulation function. When this pin is held Low, Diode Emulation Mode is enabled for the
Sync FET. When SKIP# is High, the CSD95375Q4M operates in Forced Continuous Conduction Mode. A tri-state
voltage on SKIP# puts the driver into a very low power state.
2 V
3 P
4 V
5 V
DD
GND
SW
IN
Supply Voltage to Gate Drivers and internal circuitry.
Power Ground, Needs to be connected to Pin 9 and PCB
Voltage Switching Node – pin connection to the output inductor.
Input Voltage Pin. Connect input capacitors close to this pin.
6 BOOT_R Bootstrap capacitor connection. Connect a minimum 0.1 µF 16 V X5R, ceramic cap from BOOT to BOOT_R pins. The
7 BOOT
bootstrap capacitor provides the charge to turn on the Control FET. The bootstrap diode is integrated. Boot_R is
internally connected to VSW.
8 PWM Pulse Width modulated tri-state input from external controller. Logic Low sets Control FET gate low and Sync FET
gate high. Logic High sets Control FET gate high and Sync FET gate Low. Open or High Z sets both MOSFET gates
low if greater than the Tri-State Shutdown Hold-off Time (t
9 P
GND
Power Ground
DESCRIPTION
)
3HT
Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 3
CSD95375Q4M
SLPS430A –AUGUST 2013–REVISED AUGUST 2014
6 Specifications
www.ti.com
6.1 Absolute Maximum Ratings
(1)
TA= 25°C (unless otherwise noted)
VALUE
MIN MAX
VINto P
GND
VSWto P
VSWto P
VDDto P
, VINto V
GND
, VINto VSW(<10 ns) –7 23 V
GND
GND
PWM, SKIP# to P
BOOT to P
BOOT to P
GND
(<10 ns) –2 28 V
GND
SW
GND
–0.3 20 V
–0.3 20 V
–0.3 6 V
–0.3 6 V
–0.3 25 V
BOOT to BOOT_R –0.3 6 V
BOOT to BOOT_R (duty cycle <0.2%)
ESD Rating
Power Dissipation, P
Operating Temperature Range, T
Storage Temperature Range, T
Human Body Model (HBM) 2000 V
Charged Device Model (CDM) 500 V
D
J
stg
–40 150 °C
–55 150 °C
8 W
(1) Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating
Conditions" is not implied. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability.
UNIT
6.2 Recommended Operating Conditions
TA= 25° (unless otherwise noted)
MIN MAX UNIT
Gate Drive Voltage, V
Input Supply Voltage, V
Continuous Output Current, I
Peak Output Current, I
Switching Frequency, ƒ
DD
IN
OUT-PK
SW
OUT
(2)
VIN= 12 V, VDD= 5 V, V
ƒSW= 500 kHz, L
C
= 0.1 µF (min) 2000 kHz
BST
OUT
= 1.8 V, 25 A
OUT
= 0.29 µH
(1)
On Time Duty Cycle 85%
Minimum PWM On Time 40 ns
Operating Temperature –40 125 °C
(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VINto P
(2) System conditions as defined in Note 1. Peak Output Current is applied for tp= 10 ms, duty cycle ≤1%
4.5 5.5 V
16 V
60 A
pins.
GND
6.3 Thermal Information
TA= 25°C (unless otherwise noted)
THERMAL METRIC MIN TYP MAX UNIT
R
θJC
R
θJB
(1) R
(2) R
Junction-to-Case Thermal Resistance (Top of package)
Junction-to-Board Thermal Resistance
is determined with the device mounted on a 1-inch² (6.45 -cm²), 2-oz (.071-mm thick) Cu pad on a 1.5-inches × 1.5-inches,
θJC
0.06-inch (1.52-mm) thick FR4 board.
value based on hottest board temperature within 1-mm of the package.
θJB
(2)
4 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated
(1)
22.8
2.5
°C/W
CSD95375Q4M
www.ti.com
SLPS430A –AUGUST 2013–REVISED AUGUST 2014
6.4 Electrical Characteristics
TA= 25°C, VDD= POR to 5.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
P
LOSS
Power Loss
Power Loss
V
IN
VINQuiescent Current, I
V
DD
(1)
(2)
Q
Standby Supply Current, I
Operating Supply Current, I
DD
DD
VIN= 12 V, VDD= 5 V, V
ƒSW= 500 kHz, L
OUT
VIN= 12 V, VDD= 5 V, V
ƒSW= 500 kHz, L
OUT
PWM=Floating, VDD= 5 V, VIN= 14.5 V 1 µA
PWM = Float, SKIP# = VDDor 0 V 130 µA
SKIP# = Float 8 µA
PWM = 50% Duty cycle, ƒSW= 500 kHz 6.4 mA
POWER-ON RESET AND UNDER VOLTAGE LOCKOUT
Power-On Reset, VDDRising 4.15 V
UVLO, VDDFalling 3.7 V
Hysteresis 0.2 mV
PWM and SKIP# I/O Specifications
Input Impedance, R
Logic Level High, V
Logic Level Low, V
Hysteresis, V
Tri-State Voltage, V
Tri-state Activation Time (falling) PWM,
t
THOLD(off1)
Tri-state Activation Time (rising) PWM,
t
THOLD(off2)
Tri-state Activation Time (falling) SKIP#,
t
TSKF
Tri-state Activation Time (rising) SKIP#,
t
TSKR
(2)
(2)
(2)
(2)
Tri-state Exit Time PWM, t
Tri-state Exit Time SKIP#, t
I
IH
IL
IH
TS
3RD(SKIP#)
(2)
(2)
3RD(PWM)
Pull Up to V
Pull Down (to GND) 800
DD
BOOTSTRAP SWITCH
Forward Voltage, V
Reverse Leakage, I
FBST
RLEAK
IF= 10 mA 120 240 mV
V
– VDD= 25 V 2 µA
BST
(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VINto P
(2) Specified by design
OUT
= 1.8 V, I
OUT
= 15 A,
= 0.29 µH , TJ= 25°C
OUT
= 1.8 V, I
OUT
= 15 A,
= 0.29 µH , TJ= 125°C
2.2 W
2.6 W
1700
2.65
0.2
1.3 2
60
60
1
1
0.6
100 ns
50 µs
pins.
GND
kΩ
V
ns
µs
Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 5
0 400 800 1200 1600 2000 2400
0.95
1
1.05
1.1
1.15
1.2
1.25
1.3
1.35
−0.8
0.0
0.8
1.6
2.5
3.3
4.1
4.9
5.7
Switching Frequency (kHz)
Power Loss, Normalized
SOA Temperature Adj (ºC)
VIN = 12V
VDD = 5V
V
OUT
= 1.8V
L
OUT
= 0.29µH
I
OUT
= 25A
G001
4 6 8 10 12 14 16
0.98
0.99
1
1.01
1.02
1.03
1.04
1.05
1.06
1.07
1.08
−0.3
−0.2
0.0
0.2
0.3
0.5
0.7
0.8
1.0
1.2
1.3
Input Voltage (V)
Power Loss, Normalized
SOA Temperature Adj (ºC)
VDD = 5V
V
OUT
= 1.8V
L
OUT
= 0.29µH
fSW = 500kHz
I
OUT
= 25A
G001
0
5
10
15
20
25
30
0 10 20 30 40 50 60 70 80 90
Ambient Temperature (ºC)
Output Current (A)
400LFM
200LFM
100LFM
Nat Conv
VIN = 12V
VDD = 5V
V
OUT
= 1.8V
fSW = 500kHz
L
OUT
= 0.29µH
G001
0
5
10
15
20
25
30
0 20 40 60 80 100 120 140
Board Temperature (ºC)
Output Current (A)
Min
Typ
VIN = 12V
VDD = 5V
V
OUT
= 1.8V
fSW = 500kHz
L
OUT
= 0.29µH
G001
0
1
2
3
4
5
6
7
8
9
1 4 7 10 13 16 19 22 25
Output Current (A)
Power Loss (W)
Typ
Max
VIN = 12V
VDD = 5V
V
OUT
= 1.8V
fSW = 500kHz
L
OUT
= 0.29µH
G001
0.6
0.7
0.8
0.9
1
1.1
−50 −25 0 25 50 75 100 125 150
Junction Temperature (ºC)
Power Loss, Normalized
VIN = 12V
VDD = 5V
V
OUT
= 1.8V
fSW = 500kHz
L
OUT
= 0.29µH
G001
CSD95375Q4M
SLPS430A –AUGUST 2013–REVISED AUGUST 2014
6.5 Typical Characteristics
TJ= 125°C, unless stated otherwise.
Figure 2. Power Loss vs Output Current Figure 3. Power Loss vs Temperature
www.ti.com
Figure 4. Safe Operating Area (SOA) – PCB Horizontal Figure 5. Typical Safe Operating Area (SOA)
Mount
Figure 6. Normalized Power Loss vs Frequency Figure 7. Normalized Power Loss vs Input Voltage
6 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated
(1)
(1)
0
3
6
9
12
15
18
21
24
27
30
33
0 400 800 1200 1600 2000 2400
Switching Frequency (kHz)
Driver Current (mA)
VIN = 12V
VDD = 5V
V
OUT
= 1.8V
L
OUT
= 0.29µH
I
OUT
= 25A
G000
7.6
7.65
7.7
7.75
7.8
7.85
7.9
7.95
−50 −25 0 25 50 75 100 125 150
Junction Temperature (°C)
Driver Current (mA)
VIN = 12V
VDD = 5V
V
OUT
= 1.8V
fSW = 500kHz
L
OUT
= 0.29µH
I
OUT
= 25A
G000
0 0.5 1 1.5 2 2.5 3 3.5 4
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
−5
−3.3
−1.7
0
1.7
3.3
5
6.6
Output Voltage (V)
Power Loss, Normalized
SOA Temperature Adj (ºC)
VIN = 12V
VDD = 5V
fSW = 500kHz
L
OUT
= 0.29µH
I
OUT
= 25A
G001
0 200 400 600 800 1000 1200
0.9
0.92
0.94
0.96
0.98
1
1.02
1.04
−1.6
−1.3
−1
−0.7
−0.3
0
0.3
0.7
Output Inductance (nH)
Power Loss, Normalized
SOA Temperature Adj (ºC)
VIN = 12V
VDD = 5V
V
OUT
= 1.8V
fSW = 500kHz
I
OUT
= 25A
G001
www.ti.com
Typical Characteristics (continued)
TJ= 125°C, unless stated otherwise.
Figure 8. Normalized Power Loss vs Output Voltage Figure 9. Normalized Power Loss vs Output Inductance
CSD95375Q4M
SLPS430A –AUGUST 2013–REVISED AUGUST 2014
Figure 10. Driver Current vs Frequency Figure 11. Driver Current vs Temperature
1. The Typical CSD95375Q4M System Characteristic curves are based on measurements made on a PCB design with dimensions of 4"
(W) × 3.5" (L) × 0.062" (T) and 6 copper layers of 1 oz. copper thickness. See the Application Information section for detailed
explanation.
Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 7
UDG-12218
V
UVLO_H
V
UVLO_L
V
VDD
Driver On
7
1
8
9
SKIP#
PWM
PGND
BOOT
DRVH
VSW
VDD
4
+
+
+
+
Level Shift
DRVL
+
1 V
+
1 V
+
VDD
3-State
Logic
VDD
V
UVLO
3-State
Logic
VDD
800k
1.7Meg
800k
1.7Meg
2
Control
FET
Sync
FET
6 BOOT_R
DRVL
5 VIN
3PGND
CSD95375Q4M
SLPS430A –AUGUST 2013–REVISED AUGUST 2014
7 Detailed Description
7.1 Functional Block Diagram
7.2 Feature Description
www.ti.com
7.2.1 Powering CSD95375Q4M And Gate Drivers
An external VDDvoltage is required to supply the integrated gate driver IC and provide the necessary gate drive
power for the MOSFETS. A 1 µF 10 V X5R or higher ceramic capacitor is recommended to bypass VDDpin to
P
. A bootstrap circuit to provide gate drive power for the Control FET is also included. The bootstrap supply
GND
to drive the Control FET is generated by connecting a 100 nF 16 V X5R ceramic capacitor between BOOT and
BOOT_R pins. An optional R
resistor can be used to slow down the turn on speed of the Control FET and
BOOT
reduce voltage spikes on the VSWnode. A typical 1 Ω to 4.7 Ω value is a compromise between switching loss
and VSWspike amplitude.
7.3 Undervoltage Lockout Protection (UVLO)
The undervoltage lockout (UVLO) comparator evaluates the VDD voltage level. As V
FET and Sync FET gates hold actively low at all times until V
reaches the higher UVLO threshold (V
VDD
Then the driver becomes operational and responds to PWM and SKIP# commands. If VDD falls below the lower
UVLO threshold (V
UVLO_L
= V
UVLO_H
– Hysteresis), the device disables the driver and drives the outputs of the
Control FET and Sync FET gates actively low. Figure 12 shows this function.
CAUTION
Do not start the driver in the very low power mode (SKIP# = Tri-state).
rises, both the Control
VDD
UVLO_H
).,
8 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated
Figure 12. UVLO Operation
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