Texas Instruments CDCVF2510PWR, CDCVF2510PW Datasheet

CDCVF2510

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS638 – DECEMBER 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Designed to Meet and Exceed PC133
SDRAM Registered DIMM Specification
Rev. 1.1

D

Spread Spectrum Clock Compatible

D

Operating Frequency 50 MHz to 175 MHz

D

Static Phase Error Distribution at 66MHz to
166 MHz is ±125 ps

D

Jitter (cyc – cyc) at 66 MHz to 166 MHz Is
|70| ps

D

Advanced Deep Sub-Micron Process
Results in More Than 40% Lower Power
Consumption Versus Current Generation
PC133 Devices

D

Available in Plastic 24-Pin TSSOP

D

Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications

D

Distributes One Clock Input to One Bank of
Ten Outputs

D

External Feedback (FBIN) Terminal Is Used
to Synchronize the Outputs to the Clock
Input

D

25-Ω On-Chip Series Damping Resistors

D

No External RC Network Required

D

Operates at 3.3 V

description

The CDCVF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver . It uses a PLL
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
It is specifically designed for use with synchronous DRAMs. The CDCVF2510 operates at 3.3 V VCC. It also
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted
to 50%, independent of the duty cycle at CLK. Outputs are enabled or disabled via the control (G) input. When
the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs
are disabled to the logic-low state.

Unlike many products containing PLLs, the CDCVF2510 does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry , the CDCVF2510 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback
signals. The PLL can be bypassed for test purposes by strapping AV

CC

to ground.
The CDCVF2510 is characterized for operation from 0°C to 85°C.
For application information refer to application reports

High Speed Distribution Design Techniques for

CDC509/516/2509/2510/2516

(literature number SLMA003) and

Using CDC2509A/2510A PLL with Spread

Spectrum Clocking (SSC)

(literature number SCAA039).

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1999, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

CLK
AV

CC

V

CC

1Y9
1Y8
GND
GND
1Y7
1Y6
1Y5
V

CC

FBIN

1
2
3
4
5
6
7
8
9
10
11
12

AGND

V

CC

1Y0
1Y1

1Y2
GND
GND

1Y3

1Y4

V

CC

G

FBOUT

24
23
22
21
20
19
18
17
16
15
14
13

PW PACKAGE

(TOP VIEW)

CDCVF2510

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS638 – DECEMBER 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

INPUTS

OUTPUTS

G CLK

1Y

(0:9)

FBOUT

X L L L

L HLH

H H H H

functional block diagram

1Y2

1Y1

1Y0

PLL

FBIN

AV

CC

CLK

G

1Y7

1Y6

1Y5

1Y8

FBOUT

1Y3

1Y4

11

24

13

23

3

4

5

8

9

15

16

17

20

12

1Y9

21

AVAILABLE OPTIONS

PACKAGE

T

A

SMALL OUTLINE

(PW)

0°C to 85°C CDCVF2510PWR

CDCVF2510

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS638 – DECEMBER 1999

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

TYPE

DESCRIPTION

CLK 24 I

Clock input. CLK provides the clock signal to be distributed by the CDCVF2510 clock driver. CLK is used
to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must
have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered
up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the
feedback signal to its reference signal.

FBIN 13 I

Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally
zero phase error between CLK and FBIN.

G 11 I

Output bank enable. G is the output enable for outputs 1Y(0:9). When G is low, outputs 1Y(0:9) are
disabled to a logic-low state. When G is high, all outputs 1Y(0:9) are enabled and switch at the same
frequency as CLK.

FBOUT 12 O

Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK.
When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has an
integrated 25-Ω series-damping resistor.

1Y (0:9)

3, 4, 5, 8, 9,

15, 16, 17, 20,

21

O

Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:9) is enabled via the
G input. These outputs can be disabled to a logic-low state by deasserting the G control input. Each
output has an integrated 25-Ω series-damping resistor.

AV

CC

23 Power

Analog power supply . AVCC provides the power reference for the analog circuitry. In addition, A VCC can
be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and
CLK is buffered directly to the device outputs.

AGND 1 Ground Analog ground. AGND provides the ground reference for the analog circuitry.

V

CC

2, 10, 14, 22 Power Power supply

GND 6, 7, 18, 19 Ground Ground

CDCVF2510

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS638 – DECEMBER 1999

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, AVCC (see Note 1) AVCC < VCC +0.7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage range, VCC –0.5 V to 4.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I

(see Note 2) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high or low state,

VO (see Notes 2 and 3) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

IK

(V

I

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

OK

(V

O

< 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

O

(V

O

= 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum power dissipation at TA = 55°C (in still air) (see Note 4) 0.7 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. AVCC must not exceed VCC + 0.7 V.

2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

3. This value is limited to 4.6 V maximum.

4. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the

Package Thermal Considerations

application note in the

ABT Advanced BiCMOS T echnology Data

Book

, literature number SCBD002.

DISSIPATION RATING TABLE

BOARD

T

≤ 25°C DERATING FACTOR

‡

T

= 70°C T

= 85°C

PACKAGE

TYPE

†

R

θJA

A

POWER RATNG ABOVE TA = 25°CAPOWER RATINGAPOWER RATING

JEDEC low-K 114.5°C/W 920 mW 8.7 mW/°C 520 mW 390 mW

PW

JEDEC high-K 62.1°C/W 1690 mW 16.1 mW/°C 960 mW 720 mW

†

JECEC high-K board has better thermal performance due to multiple internal copper planes.

‡

This is the inverse of the traditional junction-to-ambient thermal resistance (R

θJA

).

recommended operating conditions (see Note 5)

MIN MAX UNIT

VCC, AVCCSupply voltage 3 3.6 V
V

IH

High-level input voltage 2 V

V

IL

Low-level input voltage 0.8 V

V

I

Input voltage 0 V

CC

V

I

OH

High-level output current –12 mA

I

OL

Low-level output current 12 mA

T

A

Operating free-air temperature 0 85 °C

NOTE 5: Unused inputs must be held high or low to prevent them from floating.

timing requirements over recommended ranges of supply voltage and operating free-air
temperature

MIN MAX UNIT

f

clk

Clock frequency 50 175 MHz
Input clock duty cycle 40% 60%
Stabilization time

†

1 ms

†

Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency , fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew ,
and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under
SSC application.