TEXAS INSTRUMENTS CDCV857A Technical data

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Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications

Spread Spectrum Clock Compatible

Operating Frequency: 60 to 180 MHz

Low Jitter (cyc–cyc): ±50 ps

Distributes One Differential Clock Input to Ten Differential Outputs

description

The CDCV857A is a high-performance, low-skew, low-jitter zero delay buf fer that distributes a differential clock input pair (CLK, CLK clock output (FBOUT, FBOUT clocks (FBIN, FBIN and frequency with CLK. When PWRDWN and the PLL is shut down (low power mode). The device also enters this low power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit will detect the low frequency condition and after applying a >20 MHz input signal this detection circuit turns on the PLL again and enables the outputs.

CDCV857A

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS667A – APRIL 2001 – REVISED AUGUST 2002

Three-State Outputs When the Input Differential Clocks Are <20 MHz

Operates From Dual 2.5-V Supplies

Available in a 48-Pin TSSOP Package or 56-Ball MicroStar Junior BGA Package

Consumes < 200-µA Quiescent Current

External Feedback PIN (FBIN, FBIN) Are Used to Synchronize the Outputs to the Input Clocks

) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback

). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback

), and the analog power input (A VDD). When PWRDWN is high, the outputs switch in phase

is low, all outputs are disabled to high impedance state (3-state),

When A V

is strapped low, the PLL is turned of f and bypassed for test purposes. The CDCV857A is also able

to track spread spectrum clocking for reduced EMI. Since the CDCV857A is based on PLL circuitry , it requires a stabilization time to achieve phase-lock of the PLL.

This stabilization time is required following power up. The CDCV857A is characterized for operation from 0°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

MicroStar Junior is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CDCV857A

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS667A – APRIL 2001 – REVISED AUGUST 2002

GND

Y0 Y0

DDQ

Y1 GND GND

DDQ

CLK CLK

DDQ

AGND

GND

DDQ

Y4 GND

DGG PACKAGE

(TOP VIEW)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

GND Y5 Y5 V

DDQ

Y6 Y6 GND GND Y7 Y7 V

DDQ

PWRDWN FBIN FBIN V

DDQ

FBOUT FBOUT GND Y8 Y8 V

DDQ

Y9 Y9 GND

Y1 Y1

GND GND

Y2 Y2

DDQ

CLK CLK

DDQ

AGND

GND

Y3 Y3

MicroStarJunior (GQL) Package

DDQVDDQ

(TOP VIEW)

GND

321

NC NC

GND

Y6 Y6

GND GND

Y7 Y7

PWRDN V

DDQ

FBIN FBIN

DDQ

FBOUT FBOUT

GND

Y8 Y8

DDQ

GND

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

GND

GND H L H L H L H Bypassed/Off GND H H L H L H L Bypassed/Off

X L L H Z Z Z Z Off X L H L Z Z Z Z Off

2.5 V (nom) H L H L H L H On

2.5 V (nom) H H L H L H L On

2.5 V (nom) X <20 MHz <20 MHz Z Z Z Z Off

functional block diagram

PWRDWN CLK CLK Y[0:9] Y[0:9] FBOUT FBOUT

INPUTS

CDCV857A

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS667A – APRIL 2001 – REVISED AUGUST 2002

FUNCTION TABLE (Select Functions)

OUTPUTS PLL

PWRDWN

CLK

CLK FBIN FBIN

Powerdown

and Test

Logic

PLL

FBOUT FBOUT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CDCV857A

DESCRIPTION

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS667A – APRIL 2001 – REVISED AUGUST 2002

Terminal Functions

TERMINAL

NAME DGG GQL

AGND 17 H1 Ground for 2.5-V analog supply AV

CLK, CLK 13, 14 F1, F2 I Differential clock input FBIN, FBIN 35, 36 F5, F6 I Feedback differential clock input FBOUT, FBOUT 32, 33 H6, G5 O Feedback dif ferential clock output GND 1, 7, 8, 18,

PWRDWN 37 E6 I Output enable for Y and Y V

DDQ

Y[0:9] 3, 5, 10,

Y[0:9] 2, 6, 9, 19,

16 G2 2.5-V Analog supply

24, 25, 31,

41, 42, 48

4, 11, 12,

15, 21, 28,

34, 38, 45

20, 22, 27, 29, 39, 44,

23, 26, 30,

40, 43, 47

A3, A4, C1, C2, C5, C6, H2, H5,

K3, K4

B3, B4, E1, E2, E5, G1,

G6, J3, J4

A1, B2, D1, J2, K1, A6, B5, D6,

J5, K6

A2, B1, D2, J1, K2, A5, B6, D5,

J6, K5

Ground

2.5-V Supply

O Buffered output copies of input clock, CLK

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range, V Input voltage range, V

Output voltage range, V Input clamp current, I

Output clamp current, I Continuous output current, I Continuous current to GND or V Package thermal impedance, θ

AVDD 0.5 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DDQ

(see Notes 1 and 2) –0.5 V to V

(VI < 0 or V

(VO < 0 or VO > V

> V

(VO = 0 to V

±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DDQ

(see Note 3): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DDQ

) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DDQ

) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

DDQ DDQ

0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GQL package 137.6°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This value is limited to 3.6 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Low level input voltage, V

High level input voltage, V

Differential input signal voltage, V

(see Note 6)

CDCV857A

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS667A – APRIL 2001 – REVISED AUGUST 2002

recommended operating conditions (see Note 4)

MIN TYP MAX UNIT

Supply voltage, V

DC input signal voltage (see Note 5) –0.3 V

Output differential cross-voltage, VOX (see Note 7) V Input differential pair cross-voltage, VIX (see Note 7) V High-level output current, I Low-level output current, I Input slew rate, SR 1 4 V/ns Operating free-air temperature, T

NOTES: 4. Unused inputs must be held high or low to prevent them from floating.

5. DC input signal voltage specifies the allowable dc execution of differential input.

6. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level and VCP is the complementary input level.

7. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be crossing.

DDQ,

2.3 2.7 V CLK, CLK, FBIN, FBIN V PWRDWN –0.3 0.7 CLK, CLK, FBIN, FBIN V PWRDWN 1.7 V

DC CLK, FBIN 0.36 V AC

CLK, FBIN 0.7 V

/2 + 0.18

DDQ

/2 – 0.2 V

DDQ

/2 – 0.2 V

DDQ

0 85 °C

DDQ

/2 V

DDQ

DDQ DDQ

/2 – 0.18

DDQ

DDQ DDQ

+ 0.3

DDQ

+ 0.6

+ 0.6 /2 + 0.2 V /2 + 0.2 V

–12 mA

12 mA

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CDCV857A

VOHHigh-level output voltage

VOLLow-level output voltage

Differential outputs are terminated with t

ith

IDDDynamic current on V

ith

AIDDSupply current on AV

180

MHz

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS667A – APRIL 2001 – REVISED AUGUST 2002

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

DDPD

†

All typical values are at respective nominal V

‡

The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120-Ω resistor, where VTR is the true input signal voltage and VCP is the complementary input signal voltage.

Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signals must be crossing.

Input voltage All inputs V

High-level output current V Low-level output current V Output voltage swing Output differential

cross-voltage Input current V High-impedance-state

output current Power down current on

DDQ

Input capacitance VCC = 2.5 V VI = VCC or GND 2 2.5 3 pF Output capacitance VCC = 2.5 V VO = VCC or GND 2.5 3 3.5 pF

+ AV

DDQ

= 2.3 V, II = –18 mA –1.2 V

DDQ

= min to max, IOH = –1 mA V

DDQ

= 2.3 V, IOH = –12 mA 1.7

DDQ

= min to max, IOL = 1 mA 0.1

DDQ

= 2.3 V, IOL = 12 mA 0.6

DDQ

= 2.3 V, VO = 1 V –18 –32 mA

DDQ

= 2.3 V, VO = 1.2 V 26 35 mA

DDQ

120 Ω

DDQ

CLK and CLK = 0 MHz; PWRDWN = Low; Σ of IDD and AI

Differential outputs

erminated w

120 Ω/CL = 14 pF Differential outputs

erminated w

120 Ω/CL = 0 pF fO = 180 MHz 10 12 fO = 167 MHz

DDQ

V = 2.7 V, VI = 0 V to 2.7 V ±10 µA = 2.7 V, VO= V

fO = 180 MHz 275 330 fO = 167 MHz 250 300 fO = 180 MHz 225 275 fO = 167 MHz 210 250

or GND ±10 µA

DDQ

/2 – 0.2 V

DDQ

– 0.1

1.1 V

†

/2 V

DDQ

100 200 µA

8 10

DDQ

MAX UNIT

– 0.4

/2 + 0.2

timing requirements over recomme nd ed ran ge s of supply voltage and operating free-air temperature

CLK

Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency , fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew , and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application.

Operating clock frequency Application clock frequency Input clock duty cycle 40% 60% Stabilization timeW (PLL mode) 10 µs

Stabilization timeW (Bypass mode) 30 ns

MIN MAX UNIT

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Jitter (period), See Figure 6

Jitter (cycle-to-cycle), See Figure 3

Half-period jitter, See Figure 7

y(j),

Static phase offset, See Figure 4(a)

CDCV857A

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS667A – APRIL 2001 – REVISED AUGUST 2002

switching characteristics

PARAMETER TEST CONDITIONS MIN

}

PLH

}

PHL

jit(per)

jit(cc)

jit(hper)

slr(i)

slr(o)

d(Ø)

(Ø)

tsk

(o)

tr, tf Output rise and fall times (20% – 80%) Load: 120 Ω/14 pF 650 900 ps

†

All typical values are at a respective nominal V

‡

Refers to transition of noninverting output.

This parameter is assured by design but can not be 100% production tested.

All differential output pins are terminated with 120 Ω/14 pF.

Low to high level propagation delay time Test mode/CLK to any output 4.5 ns High-to low level propagation delay time Test mode/CLK to any output 4.5 ns

Input clock slew rate, See Figure 8 1 4 V/ns Output clock slew rate, See Figure 8 1 2 V/ns

Dynamic phase offset (this includes jitter), See Figure 4(b)

Output skew, See Figure 5 75 ps

DDQ

66 MHz –55 55 ps 100/133/167/180 MHz –35 35 ps 66 MHz –60 60 100/133/167/180 MHz –50 50 66 MHz –100 100 100/133/167/180 MHz –75 75

66 MHz –180 180

SSC off

SSC on

66 MHz –150 150 100/133/167/180 MHz –100 100

100/133 MHz –130 130

167/180 MHz –90 90

66 MHz –230 230

100/133 MHz –170 170

167/180 MHz –100 100

TYP

{

MAX UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CDCV857A

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS667A – APRIL 2001 – REVISED AUGUST 2002

PARAMETER MEASUREMENT INFORMATION

(CLK)

R = 60 Ω

CDCV857

GND

(CLK)

R = 60 Ω

VDD/2

Figure 1. IBIS Model Output Load (used for slew rate measurement)

VDD/2

CDCV857A

Z = 60 Ω

C = 14 pF

R = 10 Ω

C = 14 pF

–VDD/2

Z = 50 ΩR = 10 Ω

Z = 50 Ω

SCOPE

(TT)

R = 50 Ω

–VDD/2

NOTE: V

(TT)

= GND

Figure 2. Output Load Test Circuit

Yx, FBOUT

c(n)

jit(cc)

= t

c(n)

– t

c(n+1)

Figure 3. Cycle-to-Cycle Jitter

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CDCV857A

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS667A – APRIL 2001 – REVISED AUGUST 2002

PARAMETER MEASUREMENT INFORMATION

CLK

FBIN

CLK

FBIN

( ) n

( )

(N is a large number of samples)

(a) Static Phase Offset

( )

(b)

Dynamic Phase Offset

n = N

∑

( ) n

( )

( ) n+1

( )

Figure 4. Phase Offset

Yx, FBOUT

sk(o)

Figure 5. Output Skew

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CDCV857A

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS667A – APRIL 2001 – REVISED AUGUST 2002

PARAMETER MEASUREMENT INFORMATION

Yx, FBOUT

Figure 6. Period Jitter

, FBOUT

jit(per)

c(n)

= tcn –

Yx, FBOUT

Clock Inputs and Outputs

(hper_n)

jit(hper)

= t

(hper_n) –

(hper_n+1)

2xf

Figure 7. Half-Period Jitter

80%

20%

slrr(i)

, t

slrr(o)

slrf(i)

Figure 8. Input and Output Slew Rates

80%

VID, V

20%

, t

slrf(o)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CDCV857A

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS667A – APRIL 2001 – REVISED AUGUST 2002

MECHANICAL DATA

DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0,50

1,20 MAX

0,27 0,17

0,15 0,05

0,08

8,30

6,20

7,90

6,00

Seating Plane

0,10

0,15 NOM

Gage Plane

0,25

0°–8°

0,75 0,50

DIM

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

PINS **

A MAX

A MIN

12,60

12,40

14,10

13,90

17,10

16,90

4040078/F 12/97

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CDCV857A

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS667A – APRIL 2001 – REVISED AUGUST 2002

MECHANICAL DATA

GQL (R-PBGA-N56) PLASTIC BALL GRID ARRAY

7,10 6,90

4,60 4,40

A1 Corner

3X Via Hole

Without

Ball

Missing Via

Hole Indicates

Pin A1

Quadrant

0,65

K J H G F E D C B A

123 645

Bottom View

3,25

0,325

0,65

5,85

0,325

1,00 MAX

0,45

56×∅

0,35

0,05

NOTES: A. All linear dimensions are in millimeters.

MicroStar Junior is a trademark of Texas Instruments.

B. This drawing is subject to change without notice. C. MicroStar Junior BGA configuration D. Falls within JEDEC MO-225 variation BA. E. This package is tin-lead (SnPb). Refer to the 56 ZQL package (drawing 4204437) for lead-free.

0,08

Seating Plane

0,25 0,15

4200583/D 06/2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

4-Mar-2005

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

CDCV857ADGG ACTIVE TSSOP DGG 48 40 Pb-Free

CDCV857ADGGR ACTIVE TSSOP DGG 48 2000 Pb-Free

CDCV857AGQLR ACTIVE VFBGA GQL 56 1000 None Call TI Level-2A-220C-4 WKS

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-250C-UNLIM

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

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TEXAS INSTRUMENTS CDCV857A Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual