TEXAS INSTRUMENTS CDCV857A Technical data

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D

Phase-Lock Loop Clock Driver for Double
Data-Rate Synchronous DRAM
Applications

D

Spread Spectrum Clock Compatible

D

Operating Frequency: 60 to 180 MHz

D

Low Jitter (cyc–cyc): ±50 ps

D

Distributes One Differential Clock Input to
Ten Differential Outputs

description

The CDCV857A is a high-performance, low-skew, low-jitter zero delay buf fer that distributes a differential clock
input pair (CLK, CLK
clock output (FBOUT, FBOUT
clocks (FBIN, FBIN
and frequency with CLK. When PWRDWN
and the PLL is shut down (low power mode). The device also enters this low power mode when the input
frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input
frequency detection circuit will detect the low frequency condition and after applying a >20 MHz input signal this
detection circuit turns on the PLL again and enables the outputs.

CDCV857A

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS667A – APRIL 2001 – REVISED AUGUST 2002

D

Three-State Outputs When the Input
Differential Clocks Are <20 MHz

D

Operates From Dual 2.5-V Supplies

D

Available in a 48-Pin TSSOP Package or
56-Ball MicroStar Junior BGA Package

D

Consumes < 200-µA Quiescent Current

D

External Feedback PIN (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Input Clocks

) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback

). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback

), and the analog power input (A VDD). When PWRDWN is high, the outputs switch in phase

is low, all outputs are disabled to high impedance state (3-state),

When A V

is strapped low, the PLL is turned of f and bypassed for test purposes. The CDCV857A is also able

DD

to track spread spectrum clocking for reduced EMI.
Since the CDCV857A is based on PLL circuitry , it requires a stabilization time to achieve phase-lock of the PLL.

This stabilization time is required following power up. The CDCV857A is characterized for operation from 0°C
to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

MicroStar Junior is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2002, Texas Instruments Incorporated

1

CDCV857A

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS667A – APRIL 2001 – REVISED AUGUST 2002

GND

Y0
Y0

V

DDQ

Y1

Y1
GND
GND

Y2

Y2

V

DDQ

V

DDQ

CLK
CLK

V

DDQ

AV

DD

AGND

GND

Y3

Y3

V

DDQ

Y4

Y4
GND

DGG PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

GND
Y5
Y5
V

DDQ

Y6
Y6
GND
GND
Y7
Y7
V

DDQ

PWRDWN
FBIN
FBIN
V

DDQ

FBOUT
FBOUT
GND
Y8
Y8
V

DDQ

Y9
Y9
GND

Y1
Y1

GND
GND

Y2
Y2

V

DDQ

V

DDQ

CLK
CLK

V

DDQ

AV

DD

AGND

GND

Y3
Y3

MicroStarJunior (GQL) Package

Y0

A

B

C

D

E

F

G

H

J

K

DDQVDDQ

V

Y0

(TOP VIEW)

GND

321

NC

NC

NC NC

NC NC

NC

GND

4

NC

NC

NC

NC

Y5

Y5

65

Y6
Y6

GND
GND

Y7
Y7

PWRDN
V

DDQ

FBIN
FBIN

V

DDQ

FBOUT
FBOUT

GND

Y8
Y8

Y4

Y4

DDQ

DDQ

GND

V

2

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GND

V

Y9

Y9

AV

DD

GND H L H L H L H Bypassed/Off
GND H H L H L H L Bypassed/Off

X L L H Z Z Z Z Off
X L H L Z Z Z Z Off

2.5 V (nom) H L H L H L H On

2.5 V (nom) H H L H L H L On

2.5 V (nom) X <20 MHz <20 MHz Z Z Z Z Off

functional block diagram

PWRDWN CLK CLK Y[0:9] Y[0:9] FBOUT FBOUT

INPUTS

CDCV857A

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS667A – APRIL 2001 – REVISED AUGUST 2002

FUNCTION TABLE
(Select Functions)

OUTPUTS PLL

Y0

Y0

PWRDWN

AV

DD

CLK

CLK
FBIN
FBIN

Powerdown

and Test

Logic

PLL

Y1

Y1

Y2

Y2

Y3

Y3

Y4

Y4

Y5

Y5

Y6

Y6

Y7

Y7

Y8

Y8

Y9

Y9

FBOUT
FBOUT

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CDCV857A

DESCRIPTION

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS667A – APRIL 2001 – REVISED AUGUST 2002

Terminal Functions

TERMINAL

NAME DGG GQL

AGND 17 H1 Ground for 2.5-V analog supply
AV

DD

CLK, CLK 13, 14 F1, F2 I Differential clock input
FBIN, FBIN 35, 36 F5, F6 I Feedback differential clock input
FBOUT, FBOUT 32, 33 H6, G5 O Feedback dif ferential clock output
GND 1, 7, 8, 18,

PWRDWN 37 E6 I Output enable for Y and Y
V

DDQ

Y[0:9] 3, 5, 10,

Y[0:9] 2, 6, 9, 19,

16 G2 2.5-V Analog supply

24, 25, 31,

41, 42, 48

4, 11, 12,

15, 21, 28,

34, 38, 45

20, 22, 27,
29, 39, 44,

46

23, 26, 30,

40, 43, 47

A3, A4,
C1, C2,
C5, C6,
H2, H5,

K3, K4

B3, B4,
E1, E2,
E5, G1,

G6, J3, J4

A1, B2,
D1, J2,
K1, A6,
B5, D6,

J5, K6

A2, B1,
D2, J1,
K2, A5,
B6, D5,

J6, K5

Ground

2.5-V Supply

O Buffered output copies of input clock, CLK

O Buffered output copies of input clock, CLK

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range, V
Input voltage range, V

I

Output voltage range, V
Input clamp current, I

IK

Output clamp current, I
Continuous output current, I
Continuous current to GND or V
Package thermal impedance, θ

AVDD 0.5 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

,

DDQ

(see Notes 1 and 2) –0.5 V to V

(see Notes 1 and 2) –0.5 V to V

O

(VI < 0 or V

(VO < 0 or VO > V

OK

O

> V

I

(VO = 0 to V

±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DDQ

(see Note 3): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DDQ

DDQ

) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DDQ

) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

DDQ
DDQ

0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GQL package 137.6°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This value is limited to 3.6 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Low level input voltage, V

V

High level input voltage, V

V

Differential input signal voltage, V

(see Note 6)

V

CDCV857A

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS667A – APRIL 2001 – REVISED AUGUST 2002

recommended operating conditions (see Note 4)

MIN TYP MAX UNIT

Supply voltage, V

p

p

DC input signal voltage (see Note 5) –0.3 V

p

Output differential cross-voltage, VOX (see Note 7) V
Input differential pair cross-voltage, VIX (see Note 7) V
High-level output current, I
Low-level output current, I
Input slew rate, SR 1 4 V/ns
Operating free-air temperature, T

NOTES: 4. Unused inputs must be held high or low to prevent them from floating.

5. DC input signal voltage specifies the allowable dc execution of differential input.

6. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level
and VCP is the complementary input level.

7. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be
crossing.

DDQ,

AV

IL

DD

IH

OH

OL

2.3 2.7 V
CLK, CLK, FBIN, FBIN V
PWRDWN –0.3 0.7
CLK, CLK, FBIN, FBIN V
PWRDWN 1.7 V

ID

A

DC CLK, FBIN 0.36 V
AC

CLK, FBIN 0.7 V

/2 + 0.18

DDQ

/2 – 0.2 V

DDQ

/2 – 0.2 V

DDQ

0 85 °C

DDQ

/2 V

DDQ

DDQ
DDQ

/2 – 0.18

DDQ

DDQ
DDQ

+ 0.3

DDQ

+ 0.6

+ 0.6
/2 + 0.2 V
/2 + 0.2 V

–12 mA

12 mA

V

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