TEXAS INSTRUMENTS CDCR83 Technical data

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CDCR83

DIRECT RAMBUS CLOCK GENERATOR

SCAS632A – APRIL 2001 – REVISED MARCH 2002

D 400-MHz Differential Clock Source for

Direct Rambus
800-MHz Data Transfer Rate



Memory Systems for an

D Synchronizes the Clock Domains of the

Rambus Channel With an External System
or Processor Clock

D Three Power Operating Modes to Minimize

Power for Mobile and Other
Power-Sensitive Applications

D Operates From a Single 3.3-V Supply and

120 mW at 300 MHz (Typ)

D Packaged in a Shrink Small-Outline

Package (DBQ)

D Supports Frequency Multipliers: 4, 6, 8,

16/3

D No External Components Required for PLL
D Supports Independent Channel Clocking
D Spread Spectrum Clocking Tracking

Capability to Reduce EMI

D Designed for Use With TI’s 133-MHz Clock

Synthesizers CDC924 and CDC921

description

D Cycle-Cycle Jitter Is Less Than 50 ps at

400 MHz

D Certified by Gigatest Labs to Exceed the

Rambus DRCG Validation Requirement

D Supports Industrial Temperature Range of

°

–40

C to 85°C

DBQ PACKAGE

(TOP VIEW)

VDDIR

REFCLK

V

GNDP

GNDI

PCLKM

SYNCLKN

GNDC

V

V

DD

STOPB

PWRDNB

NC – No internal connection

DD

DD

IPD

1
2

P

3
4
5
6
7
8

C

9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

S0
S1
V

O

DD

GNDO
CLK
NC
CLKB
GNDO
V

O

DD

MULT0
MULT1
S2

The Direct Rambus clock generator (DRCG) provides the necessary clock signals to support a Direct Rambus
memory subsystem. It includes signals to synchronize the Direct Rambus channel clock to an external system
or processor clock. It is designed to support Direct Rambus memory on a desktop, workstation, server, and
mobile PC motherboards. DRCG also provides an off-the-shelf solution for a broad range of Direct Rambus
memory applications.

The DRCG provides clock multiplication and phase alignment for a Direct Rambus memory subsystem to
enable synchronous communication between the Rambus channel and ASIC clock domains. In a Direct
Rambus memory subsystem, a system clock source provides the REFCLK and PCLK clock references to the
DRCG and memory controller, respectively. The DRCG multiplies REFCLK and drives a high-speed BUSCLK
to RDRAMs and the memory controller. Gear ratio logic in the memory controller divides the PCLK and BUSCLK
frequencies by ratios M and N such that PCLKM = SYNCLKN, where SYNCLK = BUSCLK/4. The DRCG detects
the phase difference between PCLKM and SYNCLKN and adjusts the phase of BUSCLK such that the skew
between PCLKM and SYNCLKN is minimized. This allows data to be transferred across the SYNCLK/PCLK
boundary without incurring additional latency.

User control is provided by multiply and mode selection terminals. The multiply terminals provide selection of
one of four clock frequency multiply ratios, generating BUSCLK frequencies ranging from 267 MHz to 400 MHz
with clock references ranging from 33 MHz to 100 MHz. The mode select terminals can be used to select a
bypass mode where the frequency multiplied reference clock is directly output to the Rambus channel for
systems where synchronization between the Rambus clock and a system clock is not required. T est modes are
provided to bypass the PLL and output REFCLK on the Rambus channel and to place the outputs in a
high-impedance state for board testing.

The CDCR83 is characterized for operation over free-air temperatures of –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Direct Rambus and Rambus are trademarks of Rambus Inc.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2002, Texas Instruments Incorporated

1

CDCR83

DIRECT RAMBUS CLOCK GENERATOR

SCAS632A – APRIL 2001 – REVISED MARCH 2002

functional block diagram

PWRDWNB S0 S1 S2 STOPB

Test MUX

PLLCLK

REFCLK

PLL

B

Phase

Aligner

Bypass MUX

ByPCLK

CLK
CLKB

A

φ

2

MULT0
MULT1

FUNCTION TABLE

MODE

Normal 0 0 0 Phase aligned clock Phase aligned clock B
Bypass 1 0 0 PLLCLK PLLCLKB
Test 1 1 0 REFCLK REFCLKB
Output test (OE) 0 1 X Hi-Z Hi-Z
Reserved 0 0 1 — —
Reserved 1 0 1 — —
Reserved 1 1 1 Hi-Z Hi-Z

†

X = don’t care, Hi-Z = high impedance

S0 S1 S2 CLK CLKB

PACLK

D

SYNCLKNPCLKM

†

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DIRECT RAMBUS CLOCK GENERATOR

Terminal Functions

CDCR83

SCAS632A – APRIL 2001 – REVISED MARCH 2002

TERMINAL

NAME NO.

CLK 20 O Output clock
CLKB 18 O Output clock (complement)
GNDC 8 GND for phase aligner
GNDI 5 GND for control inputs
GNDO 17, 21 GND for clock outputs
GNDP 4 GND for PLL
MULT0 15 I PLL multiplier select
MULT1 14 I PLL multiplier select
NC 19 Not used
PCLKM 6 I Phase detector input
PWRDNB 12 I Active low power down
REFCLK 2 I Reference clock
S0 24 I Mode control
S1 23 I Mode control
S2 13 I Mode control
STOPB 11 I Active low output disable
SYNCLKN 7 I Phase detector input
VDDC 9 VDD for phase aligner
VDDIPD 10 Reference voltage for phase detector inputs and STOPB
VDDIR 1 Reference voltage for REFCLK
VDDO 16, 22 VDD for clock outputs
VDDP 3 VDD for PLL

I/O

DESCRIPTION

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

CDCR83

DIRECT RAMBUS CLOCK GENERATOR

SCAS632A – APRIL 2001 – REVISED MARCH 2002

PLL divider selection

Table 1 lists the supported REFCLK and BUSCLK frequencies. Other REFCLK frequencies are permitted,
provided that (267 MHz < BUSCLK < 400 MHz) and (33 MHz < REFCLK < 100 MHz).

Table 1. REFCLK and BUSCLK Frequencies

MULT0 MULT1

0 0 67 4 267
0 1 50 6 300
0 1 67 6 400
1 1 33 8 267
1 1 50 8 400
1 0 67 16/3 356

REFCLK

(MHz)

MULTIPLY

RATIO

BUSCLK

(MHz)

Table 2. Clock Output Driver States

STATE PWRDNB STOPB CLK CLKB

Powerdown 0 X GND GND

CLK stop 1 0 VX,

Normal 1 1

†

Depending on the state of S0, S1, and S2

STOP

PACLK/PLLCLK/

REFCLK

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range, V
Output voltage range, V
Input voltage range,V

(see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DD

, at any output terminal –0.5 V to V

O

, at any input terminal –0.5 V to VDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

VX,

STOP

PACLKB/PLLCLKB/

REFCLKB

DD

†

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation see Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T
Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

–40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to the GND terminals.

DISSIPATION RATING TABLE

PACKAGE

DBQ 1400 mW 11 mW/°C 905 mW 740 mW

‡

This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.

4

TA ≤ 25°C

POWER RATING

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DERATING FACTOR

ABOVE TA = 25°C

‡

POWER RATING

TA = 70°C

TA = 85°C

POWER RATING