Texas Instruments CDCM6208V1F Datasheet

CDCM6208

Synthesizer

Mode

TMS320TCI6616/18

DSP

AIF ALT

CORE

SRIO

PCIePacket

Accel

DR

Base Band DSP

Clocking

Pico Cell Clocking

DPLL

CDCM6208

APLL

GPS receiver

IEEE1588

timing extract

Ethernet

SyncE

Ethernet

Timing

Server

1pps

Core

Packet

network

FBADC

RXADC

TXDAC

RF LO

Product Folder

Sample & Buy

Technical Documents

Tools & Software

Support & Community

CDCM6208V1F 2:8 Clock Generator, Jitter Cleaner with Fractional Dividers

1 Features 2 Applications

1

• Superior Performance with Low Power: – Low Noise Synthesizer (265 fs-rms Typical

Jitter) or Low Noise Jitter Cleaner (1.6 ps-rms

Typical Jitter) – 0.5 W Typical Power Consumption – High Channel-to-Channel Isolation and

Excellent PSRR – Device Performance Customizable Through

Flexible 1.8 V, 2.5 V and 3.3 V Power

Supplies, Allowing Mixed Output Voltages

• Flexible Frequency Planning: – 4x Integer Down-divided Differential Clock

Outputs Supporting LVPECL-like, CML, or LVDS-like Signaling

– 4x Fractional or Integer Divided Differential

Clock Outputs Supporting HCSL, LVDS-like Signaling, or Eight CMOS Outputs

– Fractional Output Divider Achieve 0 ppm to < 1

ppm Frequency Error and Eliminates need for Crystal Oscillators and Other Clock Generators

– Output frequencies up to 800 MHz

• Two Differential Inputs, XTAL Support, Ability for Smart Switching

• SPI, I2C™, and Pin Programmable

• Professional user GUI for Quick Design Turnaround

• 7 x 7 mm 48-QFN package (RGZ)

• -40 °C to 85 °C temperature range

• Base Band Clocking (Wireless Infrastructure)

• Networking and Data Communications

• Keystone C66x Multicore DSP Clocking

• Storage Server, Portable Test Equipment,

• Medical Imaging, High End A/V

3 Description

The CDCM6208V1F is a highly versatile, low jitter, low-power frequency synthesizer that can generate eight low jitter clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML, LVPECL, LVDS, or LVCMOS signals for a variety of wireless infrastructure baseband, wireline data communication, computing, low power medical imaging and portable test and measurement applications. The CDCM6208V1F also features an innovative fractional divider architecture for four of its outputs that can generate any frequency with better than 1ppm frequency accuracy. The CDCM6208V1F can be easily configured through I2C or SPI programming interface and in the absence of serial interface, pin mode is also available that can set the device in 1 of 32 distinct pre-programmed configurations using control pins.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

CDCM6208V1F VQFN (48) 7.00 mm × 7.00 mm (1) For all available packages, see the orderable addendum at

the end of the datasheet.

CDCM6208V1F

SCAS943 –MAY 2015

(1)

4 Simplified Schematics

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

CDCM6208V1F

SCAS943 –MAY 2015

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5 Revision History

DATE REVISION NOTES

May 2015 * Initial release.

Product Folder Links: CDCM6208V1F

48

VDD_PLL1

47

RESETN/PWR

46

PDN

45

SYNCN

44

Y7_N

43

Y7_P

42

41

VDD_Y7

40

Y6_N

39

Y6_P

38

VDD_Y6

VDD_Y5

36

37

35

34

33

STATUS0

STATUS1/PIN0

ELF

17

18

19

20

21

22

23

24

28

27

26

29

25

30

31

32

Y0_P

Y1_N

Y1_P

VDD_Y0_Y1

VDD_Y2_Y3

Y2_P

Y2_N

VDD_Y0_Y1

SDI/SDA/PIN1

SDO/AD0/PIN2

SCS/AD1/PIN3

REF_SEL

SCL/PIN4

1

2

3

4

5

6

7

8

9

10

11

131214

15

16

Y5_P

PRI_REFN

Y0_N

PRI_REFP

SI_MODE0

Y4_N

Y3_N

REG_CAP

VDD_VCO

SEC_REFP

SEC_REFN

Y3_P

VDD_Y2_Y3

Y4_P

VDD_Y4

Y5_N

VDD_PLL2

SI_MODE1

DVDD

VDD VDD_Y 2_Y3

VDD_Y4

VDD_Y5

VDD_Y6

VDD_Y7

VDD_PRI_REF

VDD_SECI_REF

VDD_SEC_REF

_Y0_Y1

VDD_PRI_REF

CDCM6208V1F

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6 Description (continued)

In synthesizer mode, the overall output jitter performance is less than 0.5 ps-rms (10 k - 20 MHz) or 20 ps-pp (unbound) on output using integer dividers and is between 50 to 220 ps-pp (10 k - 40 MHz) on outputs using fractional dividers depending on the prescaler output frequency.

In jitter cleaner mode, the overall output jitter is less than 2.1 ps-rms (10 k - 20 MHz) or 40 ps-pp on output using integer dividers and is less than 70 ps to 240 ps-pp on outputs using fractional dividers. The CDCM6208V1F is packaged in a small 48-pin 7 mm x 7 mm QFN package.

7 Pin Configuration and Functions

RGZ Package

48 Pin VQFN

Top View

NAME NO.

PRI_REFP 8 Input Universal Primary Reference Input + PRI_REFN 9 Input Universal Primary Reference Input –

VDD_PRI_REF 7 PWR Analog

SEC_REFP 11 Input Universal Secondary Reference Input + SEC_REFN 12 Input Universal Secondary Reference Input –

VDD_SEC_REF 10 PWR Analog

(1) If Secondary input buffer is disabled (Register 4 Bit 5 = 0), it is possible to connect VDD_SEC_REF to GND.

I/O TYPE DESCRIPTION

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Pin Functions

Supply pin for reference inputs to set between 1.8 V, 2.5 V, or 3.3 V or connect to VDD_SEC_REF.

Supply pin for reference inputs to set between 1.8 V, 2.5 V, or 3.3 V or connect to VDD_PRI_REF

(1)

.

CDCM6208V1F

SCAS943 –MAY 2015

Pin Functions (continued)

NAME NO.

REF_SEL 6 Input

ELF 41 Output Analog External loop filter pin for PLL Y0_P 14 Output Universal Output 0 Positive Terminal Y0_N 15 Output Universal Output 0 Negative Terminal Y1_P 17 Output Universal Output 1 Positive Terminal Y1_N 16 Output Universal Output 1 Negative Terminal

VDD_Y0_Y1 (2 13,

pins) 18 Y2_P 20 Output Universal Output 2 Positive Terminal Y2_N 21 Output Universal Output 2 Negative Terminal Y3_P 23 Output Universal Output 3 Positive Terminal Y3_N 22 Output Universal Output 3 Negative Terminal

VDD_Y2_Y3 (2 19,

pins) 24 Y4_P 26 Output Universal Output 4 Positive Terminal Y4_N 25 Output Universal Output 4 Negative Terminal

VDD_Y4 27 PWR Analog Supply pin for output 4 to set between 1.8 V, 2.5 V or 3.3 V

Y5_P 29 Output Universal Output 5 Positive Terminal Y5_N 28 Output Universal Output 5 Negative Terminal

VDD_Y5 30 PWR Analog Supply pin for output 5 to set between 1.8 V, 2.5 V or 3.3 V

Y6_P 32 Output Universal Output 6 Positive Terminal Y6_N 33 Output Universal Output 6 Negative Terminal

VDD_Y6 31 PWR Analog Supply pin for output 6 to set between 1.8 V, 2.5 V or 3.3 V

Y7_P 35 Output Universal Output 7 Positive Terminal Y7_N 36 Output Universal Output 7 Negative Terminal

VDD_Y7 34 PWR Analog Supply pin for output 7 to set between 1.8 V, 2.5 V or 3.3 V

VDD_VCO 39 PWR Analog supply of this pin and the VDD_PLL2 supply pin can be combined as they are both

VDD_PLL1 37 PWR Analog Analog Power Supply Connections

VDD_PLL2 38 PWR Analog supply of VDD_PLL2 and VDD_VCO can be combined as these pins are both

DVDD 48 PWR Analog

GND PAD PWR Analog Power Supply Ground and Thermal Pad

STATUS0 46 Output LVCMOS Status pin 0 (see Table 7 for details)

STATUS1/PIN0 45 and

SI_MODE1 47 Input mode;SI_MODE[1:0]=01: I2C mode;SI_MODE[1:0]=10: Pin Mode (No serial

SI_MODE0 1

SDI/SDA/PIN1 2 I/O

I/O TYPE DESCRIPTION

LVCMOS selection is also controlled through Register 4 bit 12.REF_SEL = 0 (≤ VIL): selects

w/ 50kΩ pull-up PRI_REFREF_SEL = 1 (≥ VIH): selects SEC_REF (when Reg 4.12 = 1). See

PWR Analog Supply pin for outputs 0, 1 to set between 1.8 V, 2.5 V or 3.3 V

PWR Analog Supply pin for outputs 2, 3 to set between 1.8 V, 2.5 V or 3.3 V

Output

Input

LVCMOS STATUS1: Status pin in SPI/I2C modes. For details see Table 6 for pin modes and

no pull resistor Table 7 for status mode. PIN0: Control pin 0 in pin mode.

LVCMOSw

50kΩ pull-up

LVCMOSw

50kΩ pull-down

LVCMOS in

Open drain out SDI: SPI Serial Data Input SDA: I2C Serial Data (Read/Write bi-directional), open

LVCMOS in drain output; requires a pull-up resistor in I2C mode;PIN1: Control pin 1 in pin mode

no pull resistor

Manual Reference Selection MUX for PLL. In SPI or I2C mode the reference

Table 36 for detail.

Analog power supply for PLL/VCO; This pin is sensitive to power supply noise; The analog and sensitive supplies;

Analog Power Supply Connections; This pin is sensitive to power supply noise; The power-sensitive, analog supply pins

Digital Power Supply Connections; This is also the reference supply voltage for all control inputs and must match the expected input signal swing of control inputs.

Serial Interface Mode or Pin mode selection.SI_MODE[1:0]=00: SPI programming);SI_MODE[1:0]=11: RESERVED

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Pin Functions (continued)

NAME NO.

SDO/AD0/PIN2 3

SCS/AD1/PIN 3 4 Input

SCL/PIN4 5 Input SCL: SPI/I2C ClockPIN4: Control pin 4 in pin mode

RESETN/PWR 44 Input up).

REG_CAP 40 Output Analog

PDN 43 Input the entire device and defaults all registers. It is recommended to connect a capacitor

SYNCN 42 Input

(2) Note: the device cannot be programmed in I2C while RESETN is held low.

I/O TYPE DESCRIPTION

LVCMOS out

Output/I LVCMOS in SDO: SPI Serial Data AD0: I2C Address Offset Bit 0 inputPIN2: Control pin 2 in pin

nput LVCMOS in mode

no pull resistor

LVCMOS no pull SCS: SPI Latch EnableAD1: I2C Address Offset Bit 1 inputPIN3: Control pin 3 in pin

resistor mode

LVCMOS no pull

resistor

In SPI/I2C programming mode, external RESETN signal (active low). RESETN = VIL: device in reset (registers values are retained) RESETN = VIH: device active. The device can be programmed via SPI while

LVCMOS

w/ 50kΩ pull-up

RESETN is held low (this is useful to avoid any false output frequencies at power

(2)

In Pin mode this pin controls device core and I/O supply voltage setting. 0 = 1.8 V, 1 = 2.5/3.3 V for the device core and I/O power supply voltage. In pin mode, it is not possible to mix and match the supplies. All supplies should either be 1.8 V or 2.5/3.3 V.

Regulator Capacitor; connect a 10 µF cap with ESR below 1 Ω to GND at frequencies above 100 kHz

Power Down Active low. When PDN = VIHis normal operation. When PDN = VIL, the

LVCMOS

w/ 50kΩ pull-up

device is disabled and current consumption minimized. Exiting power down resets to GND to hold the device in power-down until the digital and PLL related power

supplies are stable. See section on power down in the application section.

LVCMOS Active low. Device outputs are synchronized on a low-to-high transition on the

w/ 50kΩ pull-up SYNCN pin. SYNCN held low disables all outputs.

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8 Specifications

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8.1 Absolute Maximum Ratings

(1)

over operating free-air temperature range (unless otherwise noted)

PARAMETER MIN MAX UNIT

Supply Voltage Range, VDD_PRI, VDD_SEC, VDD_Yx_Yy, VDD_PLL[2:1], DVDD -0.5 4.6 V

4.6

Input Voltage Range CMOS control inputs, V

IN

-0.5 and V V

+ 0.5

DVDD

4.6

Input Voltage Range PRI/SEC inputs and V

Output Voltage Range, V Input Current, I

IN

Output Current, I Junction Temperature, T

OUT

J

Storage temperature range, T

V

VDDPRI.SEC

-0.5 V

stg

-65 150 °C

+ 0.5

+ 0.5 V

YxYy

20 mA 50 mA

125 °C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute—maximum—rated conditions for extended periods may affect device reliability.

8.2 ESD Ratings

VALUE UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins

V

(ESD)

Electrostatic discharge V

Charged device model (CDM), per JEDEC specification JESD22-C101, all

(2)

pins

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(1)

±2000

±500

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8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

VDD_Yx_Yy Output Supply Voltage 1.71 1.8/2.5/3.3 3.465 V VDD_PLL1

VDD_PLL2 DVDD Core Digital Supply Voltage 1.71 1.8/2.5/3.3 3.465 V VDD_PRI,

VDD_SEC ΔVDD/Δt 50 < t T

A

SDA and SCL in I2C MODE (SI_MODE[1:0] = 01)

V

I

d

R

V

IH

V

IL

C

BUS_I2C

(1) For fast power up ramps under 50 ms and when all supply pins are driven from the same power supply source, PDN can be left floating.

For slower power up ramps or if supply pins are sequenced with uncertain time delays, PDN needs to be held low until DVDD, VDD_PLLx, and VDD_PRI/SEC reach at least 1.45V supply voltage. See application section on mixing power supplies and particularly

Figure 58 for details.

Core Analog Supply Voltage 1.71 1.8/2.5/3.3 3.465 V

Reference Input Supply Voltage 1.71 1.8/2.5/3.3 3.465 V VDD power-up ramp time (0 to 3.3 V) PDN left open, all VDD tight

together PDN low-high is delayed

(1)

PDN

ms

Ambient Temperature -40 85 °C

Input Voltage

Data Rate kbps

High-level input voltage V

DVDD = 1.8 V –0.5 2.45 V DVDD = 3.3 V –0.5 3.965 V

100 400

0.7 x

DVDD Low-level input voltage 0.3 x DVDD V Total capacitive load for each bus line 400 pF

8.4 Thermal Information, Airflow = 0 LFM

(1) (2) (3) (4)

CDCM6208

THERMAL METRIC

(1)

RGZ UNIT

48 PINS VQFN

R

θJA

R

θJC(top)

R

θJB

ψ

JT

ψ

JB

R

θJC(bot)

Junction-to-ambient thermal resistance 30.27 Junction-to-case (top) thermal resistance 16.58 Junction-to-board thermal resistance 6.83 Junction-to-top characterization parameter 0.23 Junction-to-board characterization parameter 6.8 Junction-to-case (bottom) thermal resistance 1.06

°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board). (3) Connected to GND with 36 thermal vias (0.3 mm diameter). (4) θJB(junction to board) is used for the QFN package, the main heat flow is from the junction to the GND pad of the QFN.

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8.5 Thermal Information, Airflow = 150 LFM

(1) (2) (3) (4)

CDCM6208

THERMAL METRIC

(1)

RGZ UNIT

48 PINS

R

θJA

R

θJC(top)

R

θJB

ψ

JT

ψ

JB

R

θJC(bot)

Junction-to-ambient thermal resistance 21.8 Junction-to-case (top) thermal resistance Junction-to-board thermal resistance 6.61 Junction-to-top characterization parameter 0.37 Junction-to-board characterization parameter Junction-to-case (bottom) thermal resistance 1.06

°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board). (3) Connected to GND with 36 thermal vias (0.3 mm diameter). (4) θJB(junction to board) is used for the QFN package, the main heat flow is from the junction to the GND pad of the QFN.

8.6 Thermal Information, Airflow = 250 LFM

(1) (2) (3) (4)

CDCM6208

THERMAL METRIC

(1)

RGZ UNIT

48 PINS

R

θJA

R

θJC(top)

R

θJB

ψ

JT

ψ

JB

R

θJC(bot)

Junction-to-ambient thermal resistance 19.5 Junction-to-case (top) thermal resistance Junction-to-board thermal resistance 6.6 Junction-to-top characterization parameter 0.45 Junction-to-board characterization parameter Junction-to-case (bottom) thermal resistance 1.06

°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board). (3) Connected to GND with 36 thermal vias (0.3 mm diameter). (4) θJB(junction to board) is used for the QFN package, the main heat flow is from the junction to the GND pad of the QFN.

8.7 Thermal Information, Airflow = 500 LFM

(1) (2) (3) (4)

CDCM6208

THERMAL METRIC

(1)

RGZ UNIT

48 PINS

R

θJA

R

θJC(top)

R

θJB

ψ

JT

ψ

JB

R

θJC(bot)

Junction-to-ambient thermal resistance 17.7 Junction-to-case (top) thermal resistance Junction-to-board thermal resistance 6.58 Junction-to-top characterization parameter 0.58 Junction-to-board characterization parameter Junction-to-case (bottom) thermal resistance 1.05

°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board). (3) Connected to GND with 36 thermal vias (0.3 mm diameter). (4) θJB(junction to board) is used for the QFN package, the main heat flow is from the junction to the GND pad of the QFN.

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8.8 Single Ended Input Characteristics

(SI_MODE[1:0], SDI/SDA/PIN1, SCL/PIN4, SDO/ADD0/PIN2, SCS/ADD1/PIN3, STATUS1/PIN0, RESETN/PWR, PDN, SYNCN, REF_SEL), DVDD = 1.71V to 1.89V, 2.375V to 2.625V, 3.135V to 3.465V, TA= –40°C to 85°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

IH

V

IL

I

IH

I

IL

ΔV/ΔT 20% - 80% 0.75 V/ns

minPulse 10 ns C

IN

RESETN, PWR, SYNCN, PDN, REF_SEL, SI_MODE[1:0]:

R Input Pullup and Pulldown Resistor 35 50 65 kΩ

SDA and SCL in I2C Mode (SI_MODE[1:0]=01)

V

HYS_I2C

I

H

V

OL

C

IN

Input High Voltage 0.8 x DVDD V Input Low Voltage 0.2 x DVDD V

Input High Current 30 µA

DVDD = 3.465V, VIH= 3.465 V (pull-up

resistor excluded) Input Low Current DVDD = 3.465V, VIL= 0 V -30 µA PDN, RESETN, SYNCN, REF_SEL Input

Edge Rate PDN, RESETN, SYNCN low pulse to

trigger proper device reset Input Capacitance 2.25 pF

Input hysteresis

DVDD = 1.8 V 0.1 V

DVDD = 2.5/3.3 V 0.05 V

DVDD DVDD

High-level input current VI= DVDD –5 5 µA Output Low Voltage IOL= 3mA 0.2 x DVDD V Input Capacitance terminal 5 pF

V V

8.9 Single Ended Input Characteristics (PRI_REF, SEC_REF)

VDD_PRI, VDD_SEC = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, TA= –40°C to 85°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

IN

V

V I

IH

I

IL

IH

IL

HYST

Reference and Bypass Input Frequency

Input High Voltage VDD_PRI/V V

Input Low Voltage VDD_PRI/V V

Input hysteresis 20 65 150 mV Input High Current VDD_PRI/VDD_SEC = 3.465 V, VIH= 3.465 V 30 µA Input Low Current VDD_PRI/VDD_SEC = 3.465 V, VIL= 0 V -30 µA

ΔV/ΔT Reference Input Edge Rate 20% - 80% 0.75 V/ns

IDC

C

SE

IN

Reference Input Duty Cycle

Input Capacitance 2.25 pF

VDD_PRI/SEC = 1.8 V 0.008 200 MHz VDD_PRI/SEC = 3.3 V 0.008 250 MHz

0.8 x

DD_SEC

0.2 x

DD_SEC

f

≤ 200MHz 40% 60%

PRI

200 ≤ f

≤ 250 MHz 43% 60%

PRI

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8.10 Differential Input Characteristics (PRI_REF, SEC_REF)

VDD_PRI, VDD_SEC = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, TA= –40°C TO 85°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

IN

V

I

V

ICM

V

ICM

V

HYST

I

IH

I

IL

ΔV/ΔT Reference Input Edge Rate 20% - 80% 0.75 V/ns IDC

DIFF

C

IN

Reference and Bypass Input Frequency 0.008 250 MHz Differential Input Voltage Swing, Peak-to-

Peak

Input Common Mode Voltage CML input signaling, R4[7:6] = 00 DD_SEC- DD_SEC- V

Input Common Mode Voltage 0.8 1.2 1.5 V

Input hysteresis

Input High Current VDD_PRI/SEC = 3.465 V, VIH= 3.465 V 30 µA Input Low Current VDD_PRI/SEC = 3.465V, VIL= 0 V -30 µA

Reference Input Duty Cycle 30% 70% Input Capacitance 2.7 pF

VDD_PRI/SEC = 2.5/3.3 V 0.2 1.6 V

VDD_PRI/SEC = 1.8 V 0.2 1 V

VDD_PRI/V VDD_PRI/V

0.4 0.1

LVDS, VDD_PRI/SEC

= 1.8/2.5/3.3 V,

R4[7:6] = 01, R4.1 = d.c.,

R4.0 = d.c.

LVDS (Q4[7:6,4:3] = 01) 15 65 mV

CML (Q4[7:6,4:3] = 00) 20 85 mV

8.11 Crystal Input Characteristics (SEC_REF)

VDD_SEC = 1.71 to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V,TA= –40°C to 85°C

PARAMETER MIN TYP MAX UNIT

MODE OF OSCILLATION FUNDAMENTAL

Frequency

See note

10 MHz 150

Equivalent Series Resistance (ESR) 25 MHz 70

50 MHz 30

1.8 V / 3.3 V SEC_REFP 3.5 4.5 5.5

On-chip load capacitance 1.8 V SEC_REFN 5.5 7.25 8.5 pF

3.3 V SEC_REFN 6.5 7.34 8.5

Drive Level See note

(1) Verified with crystals specified for a load capacitance of CL=8pF, the pcb related capacitive load was estimated to be 2.3pF, and

completed with a load capacitors of 4pF on each crystal terminal connected to GND. XTALs tested: NX3225GA 10MHz EXS00ACG02813 CRG, NX3225GA 19.44MHz EXS00A-CG02810 CRG, NX3225GA 25MHz EXS00A-CG02811 CRG, and NX3225GA

30.72MHz EXS00A-CG02812 CRG.

(2) For 30.73 MHz to 50 MHz, it is recommended to verify sufficient negative resistance and initial frequency accuracy with the crystal

vendor. The 50 MHz use case was verified with a NX3225GA 50MHz EXS00A-CG02814 CRG. To meet a minimum frequency error, the

best choice of the XTAL was one with CL= 7pF instead of CL= 8pF. (3) With NX3225GA_10M the measured remaining negative resistance on the EVM is 6430 Ω (43 x margin) (4) With NX3225GA_25M the measured remaining negative resistance on the EVM is 1740 Ω (25 x margin) (5) With NX3225GA_50M the measured remaining negative resistance on the EVM is 350 Ω (11 x margin) (6) Maximum drive level measured was 145 µW; XTAL should at least tolerate 200 µW

(1) (2)

(6)

10 30.72 MHz

30.73 50 MHz

(3) (4) (5)

200 µW

PP PP

pp pp

Ω

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8.12 Single Ended Output Characteristics (STATUS1, STATUS0, SDO, SDA)

VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71V to 1.89V, 2.375V to 2.625V, 3.135V to 3.465V; TA= –40°C to 85°C (Output load capacitance 10 pF unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Status 1, Status 0, and SDO only;

V

OH

V

OL

V

slew

I

OZH

I

OZL

t

LOS

t

LOCK

Output High Voltage V

Output Low Voltage IOL= 1 mA V Output slew rate 30% - 70% 0.5 V/ns

3-stat Output High Current DVDD = 3.465 V, VIH= 3.465 V 5 µA 3-stat Output Low Current DVDD = 3.465 V, VIL= 0 V -5 µA Status Loss of Signal Detection

Time

Status PLL Lock Detection Time 1/f

SDA is open drain and relies on 0.8 x external pullup for high output; IOH= DVDD 1 mA

0.2 x

DVDD

LOS_REFfvco 1 2 1/f Detect lock 2304

Detect unlock 512

PFD

8.13 PLL Characteristics

VDD_PLLx, VDD_VCO = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, TA= –40°C TO 85°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

VCO

K

VCO

f

PFD

I

CP-L

f

FOM

t

STARTUP

VCO Frequency Range 2.39 2.55 GHz

2.39 GHz 178

VCO Gain 2.50 GHz 204 MHz/V

2.55 GHz 213 PFD Input Frequency 0.008 100 MHz High Impedance Mode Charge

Pump Leakage Estimated PLL Figure of Merit

(FOM)

Measured in-band phase noise at the VCO output minus 20log(N- –224 dBc/Hz divider) at the flat region

±700 nA

Power supply ramp time of 1ms from 0 V to 1.7 V, final frequency

Startup time (see Figure 42 )

accuracy of 10 ppm, f C

PDN_to_GND

= 22nF

= 25 MHz,

PFD

w/ PRI input signal 12.8 ms w/ NDK 25 MHz crystal 12.85 ms

Product Folder Links: CDCM6208V1F

CDCM6208V1F

SCAS943 –MAY 2015

www.ti.com

8.14 LVCMOS Output Characteristics

VDD_Yx_Yy = 1.71 V to 1.89V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, TA= –40°C TO 85°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Fract Out divVDD_Yx_Yy = 2.5/3.3 V 0.78 250

f

OUT-F

f

ACC-F

V

OH

V

OL

V

OH

V

OL

I

OH

I

OL

t

SLEW-RATE-N

t

SLEW-RATE-S

PN-floor Phase Noise Floor f ODC Output Duty Cycle Not in bypass mode 45% 55%

R

OUT

(1) The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach

of a multiple 1 over 220, the actual output frequency error is 0. Note: In LVCMOS Mode, positive and negative outputs are in phase.

Output Frequency Integer out divVDD_Yx_Yy = 2.5/3.3 V 1.55 250 MHz

Int or frac out divVDD_Yx_Yy = 1.8 V 0.78/1.5 200

Output Frequency Error Output High Voltage (normal mode) VDD_Yx = min to max, IOH= -1 mA V

Output Low Voltage(normal mode) VDD_Yx = min to max, IOL= 100 µA V

Output High Voltage (slow mode) VDD_Yx = min to max, IOH= -100 µA V

Output Low Voltage(slow mode) VDD_Yx = min to max, IOL= 100 µA V

(1)

Fractional Output Divider –1 1 ppm

0.8 x

VDD_Yx_Yy

0.2 x

VDD_Yx_Yy

0.7 x

VDD_Yx_Yy

0.3 x

VDD_Yx_Yy

V

= VDD_Yx_Yy/2

OUT

Output High Current Normal mode –50 -8 mA

Slow mode –45 -5 mA

V

= VDD_Yx_Yy/2

OUT

Output Low Current Normal mode 10 55 mA

Slow mode 5 40 mA

Output Rise/Fall Slew Rate (normal mode)

Output Rise/Fall Slew Rate (slow mode)

Output Impedance

20% to 80%, VDD_Yx_Yy = 2.5/3.3 V, CL= 5 pF

20% to 80%, VDD_Yx_Yy = 1.8 V, CL= 5 pF

20% to 80%, VDD_Yx_Yy = 2.5/3.3 V, CL= 5 pF

20% to 80%, VDD_Yx_Yy = 1.8 V, CL= 5 pF

= 122.88 MHz –159.5 –154 dBc/Hz

OUT

V

= VDD_Yx/2

OUT

5.37 V/ns

2.62 V/ns

4.17 V/ns

1.46 V/ns

Normal mode 30 50 90

Slow mode 45 74 130

Ω

Product Folder Links: CDCM6208V1F

CDCM6208V1F

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SCAS943 –MAY 2015

8.15 LVPECL (High-Swing CML) Output Characteristics

VDD_Yx_Yy = 1.71 V to 3.465 V, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, TA= –40°C TO 85°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

OUT-I

V

CM-DC

|VOD| Differential output voltage

V

OUT

tR/t

t

slew

PN-floor Phase noise floor VDD_Yx_Yy = 3.3 V (See Figure 54) –161.4 –155.8 dBc/Hz ODC Output duty cycle Not in bypass mode 47.5% 52.5% R

OUT

Output frequency Integer Output Divider 1.55 800 MHz Output DC coupled common mode

voltage

DC coupled with 50 Ω external termination to VDD_Yx_Yy V

100 Ω diff load AC coupling (See Figure 12), f

≤ 250 MHz

OUT

VDD_Yx

_

Yy – 0.4

VDD_Yx_Yy ≤ 1.89 V 0.45 0.75 1.12 V VDD_Yx_Yy ≥ 2.375 V 0.6 0.8 1.12 V 100 Ω diff load AC coupling (See Figure 12), f

≥ 250 MHz

OUT

VDD_Yx_Yy ≤ 1.89 V 0.73 V VDD_Yx_Yy ≥ 2.375 V 0.55 0.75 1.12 V

Differential output peak-to-peak voltage

Output rise/fall time

F

±200 mV around crossing point 109 217 ps 20% to 80% V

OD

2 x |VOD| V

211 ps

Output rise/fall slew rate 3.7 5.1 7.3 V/ns

Output impedance measured from pin to VDD_Yx_Yy 50 Ω

8.16 CML Output Characteristics

VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71V to 1.89V, 2.375V to 2.625V, 3.135V to 3.465V, TA= –40°C to 85°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

OUT-I

V

CM-AC

V

CM-DC

|VOD| Differential output voltage 100 Ω diff load AC coupling, (See Figure 12) 0.3 0.45 0.58 V V

OUT

tR/t

F

PN-floor Phasenoise floor at > 5 Hz offset f

ODC Output duty cycle Not in bypass mode 47.5% 52.5% R

OUT

Output frequency Integer Output Divider 1.55 800 MHz Output AC coupled common

mode voltage Output DC coupled common

mode voltage

Differential output peak-to-peak voltage

Output rise/fall time 20% to 80%

AC coupled with 50 Ω receiver termination VDD_Yx_Yy – 0.46 V DC coupled with 50 Ω on-chip termination

to VDD_Yx_Yy

VDD_Yx_Yy – 0.2 V

2 x |VOD| V

VDDYx = 1.8 V 100 151 300 ps VDDYx = 2.5 V/3.3 V 100 143 200 ps

= 122.88 MHz

OUT

VDD_Yx_Yy = 1.8 V –161.2 –155.8 dBc/Hz VDD_Yx_Yy = 3.3 V –161.2 –153.8 dBc/Hz

Output impedance measured from pin to VDD_Yx_Yy 50 Ω

Product Folder Links: CDCM6208V1F

CDCM6208V1F

SCAS943 –MAY 2015

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8.17 LVDS (Low-Power CML) Output Characteristics

VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135V to

3.465V, TA= –40°C to 85°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

OUT-I

f

OUT-F

f

ACC-F

V

CM-AC

V

CM-DC

|VOD| Differential output voltage 100 Ω diff load AC coupling, (See Figure 12) 0.247 0.34 0.454 V V

OUT

tR/t

F

PN-floor Phase noise floor f

ODC Output duty cycle Not in bypass mode

R

OUT

Output frequency

Output frequency error Output AC coupled

common mode voltage Output DC coupled

common mode voltage

Differential output peak-topeak voltage

Output rise/fall time ±100mV around crossing point 300 ps

Output impedance Measured from pin to VDD_Yx_Yy 167 Ω

(1) The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach

of a multiple of 1 over 220, the actual output frequency error is 0.

Integer output divider 1.55 400 MHz Fractional output divider 0.78 400 MHz

(1)

Fractional output divider -1 1 ppm AC coupled with 50 Ω receiver termination VDD_Yx_Yy – 0.76 V

DC coupled with 50 Ω on-chip termination to VDD_Yx_Yy VDD_Yx_Yy – 0.13 V

2 x |VOD| V

= 122.88 MHz

OUT

VDD_Yx = 1.8 V –159.3 –154.5 dBc/Hz VDD_Yx = 2.5/3.3 V –159.1 –154.9 dBc/Hz Y[3:0] 47.5% 52.5% Y[7:4] 45% 55%

8.18 HCSL Output Characteristics

VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 to 1.89 V, 2.375 V to 2.625 V,3.135 V to 3.465 V, TA= –40°C to 85°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

OUT-I

f

OUT-F

f

ACC-F

V

CM

Output frequency

Output Frequency Error

(1)

Output Common Mode Voltage

|VOD| Differential Output Voltage

V

tR/t

OUT

F

Differential Output Peak-to-peak Voltage

Output Rise/Fall Time ps

PN-floor Phase Noise Floor f

ODC Output Duty Cycle Not in bypass mode 45% 55%

(1) The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach

of A 1/220multiple, the actual output frequency error is 0.

Integer Output Divider 1.55 400 MHz Fractional Output Divider 0.78 400 MHz Fractional Output Divider -1 1 ppm VDD_Yx_Yy = 2.5/3.3 V 0.2 0.34 0.55 V VDD_Yx_Yy = 1.8 V 0.2 0.33 0.55 V VDD_Yx_Yy = 2.5/3.3 V 0.4 0.67 1.0 V VDD_Yx_Yy = 1.8 V 0.4 0.65 1.0 V VDD_Yx_Yy = 2.5/3.3 V 1.0 2.1 V VDD_Yx_Yy = 1.8 V 2 x|VOD| V Measured from V

V

= +100mV, VDD_Yx_Yy = 2.5/3.3 V

DIFF

Measured from V V

= +100 mV, VDD_Yx_Yy = 1.8 V

DIFF

= 122.88 MHz

OUT

= –100 mV to

DIFF

= –100 mV to

DIFF

100 167 250

120 192 295

VDD_Yx_Yy = 1.8 V –158.8 –153 dBc/Hz VDD_Yx = 2.5/3.3 V –157.6 –153 dBc/Hz

Product Folder Links: CDCM6208V1F

CDCM6208V1F

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SCAS943 –MAY 2015

8.19 Output Skew and Sync to Output Propagation Delay Characteristics

VDD_Yx_Yy = 1.71 to 1.89 V, 2.375 V to 2.625 V, 3.135V to 3.465 V, TA= –40°C to 85°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

PD-PS

Propagation delay SYNCN↑ to output toggling high

f

= 2.5 GHz PS_A = 5 9 10.2 11 1/f

VCO

Part-to-Part Propagation delay

Δt

PD-PS

variation SYNCN↑ to output toggling Fixed supply voltage, temp, and device setting

(1)

high

OUTPUT SKEW – ALL OUTPUTS USE IDENTICAL OUTPUT SIGNALING, INTEGER DIVIDERS ONLY; PS_A = PS_B = 6, OutDiv = 4

t

SK,LVDS

t

SK,LVDS

t

SK,LVDS

t

SK,CML

t

SK,PECL

t

SK,HCSL

t

SK,SE

Skew between Y[7:4] LVDS Y[7:4] = LVDS 40 ps Skew between Y[3:0] LVDS Y[3:0] = LVDS 40 ps Skew between Y[7:0] LVDS Y[7:0] = LVDS 80 ps Skew between Y[3:0] CML Y[3:0] = CML 40 ps Skew between Y[3:0] PECL Y[3:0] = LVPECL 40 ps Skew between Y[7:4] HCSL Y[7:4] = HCSL 40 ps Skew between Y[7:4] CMOS Y[7:4] = CMOS 50 ps

OUTPUT SKEW - MIXED SIGNAL OUTPUT CONFIGURATION, INTEGER DIVIDERS ONLY; PS_A = PS_B = 6, OutDiv = 4

t

SK,CMOS-LVDS

t

SK,CMOS-PECL

t

SK,PECL-LVDS

t

SK,PECL-CML

t

SK,LVDS-PECL

t

SK,LVDS-HCSL

Skew between Y[7:4] LVDS and CMOS mixed

Skew between Y[7:0] CMOS and LVPECL mixed

Skew between Y[3:0] LVPECL and LVDS mixed

Skew between Y[3:0] LVPECL and CML mixed

Skew between Y[7:0] LVDS and LVPECL mixed

Skew between Y[7:4] LVDS and HCSL mixed

Y[4] = CMOS, Y[7:5] = LVDS 2.5 ns

Y[7:4] = CMOS, Y[3:0] = LVPECL 2.5 ns

Y[0] = LVPECL, Y[3:1] = LVDS 120 ps

Y[0] = LVPECL, Y[3:1] = CML 40 ps

Y[7:4] = LVDS, Y[3:0] = LVPECL 180 ps

Y[4] = LVDS, Y[7:5] = HCSL 250 ps

OUTPUT SKEW - USING FRACTIONAL OUTPUT DIVISION; PS_A = PS_B = 6, OutDiv = 3.125

Skew between Y[7:4] LVDS using all

t

SK,DIFF, frac

fractional divider with the same Y[7:4] = LVDS 200 ps divider setting

(1) SYNC is toggled 10,000 times for each device. Test is repeated over process voltage and temperature (PVT).

PS_A = 4 9 10.5 11 1/f

PS_A = 6 9 10.0 11 1/f

(1)

0 1 1/f

PS_A PS_A PS_A

PS_A

Product Folder Links: CDCM6208V1F

CDCM6208V1F

SCAS943 –MAY 2015

www.ti.com

8.20 Device Individual Block Current Consumption

VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.8 V, 2.5 V, or 3.3 V, TA= –40°C to 85°C, Output Types = LVPECL/CML/LVDS/LVCMOS/HCSL

BLOCK CONDITION TYPICAL CURRENT CONSUMPTION (mA)

Core CDCM6208V1F Core, active mode, PS_A = PS_B = 4 75

CML output, AC coupled w/ 100 Ω diff load 24.25 LVPECL, AC coupled w/ 100 Ω diff load 40

Output Buffer 1.8 + V x f

LVCMOS output, transient, 'CL' load, 'f' MHz output frequency, 'V' output swing

x (CL+ 12 x 10

OUT

LVDS output, AC coupled w/ 100 Ω diff load 19.7 HCSL output, 50 Ω load to GND on each output pin 31 Integer Divider Bypass (Divide = 1) 3

Output Divide Circuitry

Integer Divide Enabled, Divide > 1 8 Fractional Divider Enabled 12 additional current when PS_A differs from PS_B 15 Device Settings (V2)

1. PRI input enabled, set to LVDS mode

2. SEC input XTAL

3. Input bypass off, PRI only sent to PLL

4. Reference clock 30.72 MHz

5. PRI input divider set to 1 (excl. I

termination_resistors

(1.8 V: 251 mA

2.5 V: 254 mA

(incl. I

termination_resistors

(1.8 V: 310 mA

2.5 V: 313 mA

Total Device, CDCM6208V1F

6. Reference input divider set to 1

7. Charge Pump Current = 2.5 mA

8. VCO Frequency = 3.072 GHz 3.3 V: 257 mA)

9. PS_A = PS_B divider ration = 4

10. Feedback divider ratio = 25

11. Output divider ratio = 5 3.3 V: 316 mA)

12. Fractional divider pre-divider = 2

13. Fractional divider core input frequency = 384 MHz

14. Fractional divider value = 3.84, 5.76, 3.072, 7.68

15. CML outputs selected for CH0-3 (153.6 MHz)

LVDS outputs selected for CH4-7 (100 MHz, 66.66 MHz, 125 MHz, 50 MHz)

Total Device, CDCM6208V1F Power Down (PDN = '0') 0.35

-12

)

) x 10

3

Helpful Note: The CDCM6208V1F User GUI does an excellent job estimating the total device current consumption based on the actual device configuration. Therefore, it is recommended to use the GUI to estimate device power consumption.

The individual supply terminal current consumption for Pin mode P23 was measured to come out the following:

Table 1. Individual Supplies Measured

Y0-1 Y2-3 Y4 Y5 Y6 Y7 PRI PLL1 PLL2 VCO DVDD TOTAL

PWR PIN 39 = GND V

= 1.8 V 61 mA 40 mA 21 mA 29 mA 30 mA 31 mA 12 mA 70 mA 1.5 mA 295.5 mA

PRI

V

= 1.8 V

OUT

Customer EVM

Product Folder Links: CDCM6208V1F

SEC SEC

(V

= 1.8V) (V

SEC

= 2.5V)

CDCM6208V1F

www.ti.com

SCAS943 –MAY 2015

8.21 Worst Case Current Consumption

VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 3.45 V, TA= T-40°C to 85°C, Output Types = maximum swing, all blocks including duty cycle correction and fractional divider enabled and operating at maximum operation

BLOCK CONDITION CURRENT CONSUMPTION

TYP / MAX

All conditions over PVT, AC coupled outputs with all outputs terminated, device configuration: Device Settings (V2)

1. PRI input enabled, set to LVDS mode

2. SEC input XTAL

3. Input bypass off, PRI only sent to PLL

4. Reference clock 30.72 MHz

5. PRI input divider set to 1

6. Reference input divider set to 1

Total Device, CDCM6208V1F

7. Charge Pump Current = 2.5 mA

8. VCO Frequency = 3.072 GHz 3.3 V: 318 mA / +21% (excl term)

9. PS_A = PS_B divider ration = 4

10. Feedback divider ratio = 25

11. Output divider ratio = 5

12. Fractional divider pre-divider = 2

13. Fractional divider core input frequency = 384 MHz

14. Fractional divider value = 3.84, 5.76, 3.072, 7.68

15. CML outputs selected for CH0-3 (153.6 MHz)

LVDS outputs selected for CH4-7 (100MHz, 66.66 MHz, 125 MHz, 50 MHz)

1.8 V: 310 mA / +21% (excl term)

Product Folder Links: CDCM6208V1F

SCL

SCS

SDO

t

4

t

5

t

2

t

3

t

7

t

6

t

1

SDI

t

8

A31 D0D1

D15 D1 D0

A30

'21¶7&$5(

tri-state

CDCM6208V1F

SCAS943 –MAY 2015

www.ti.com

8.22 I2C TIMING

(1)

PARAMETER STANDARD MODE FAST MODE UNIT

MIN MAX MIN MAX

f

SCL

t

su(START)

t

h(START)

t

w(SCLL)

t

w(SCLH)

t

h(SDA)

t

su(SDA)

t

r-in

t

f-in

t

f-out

t

su(STOP)

t

BUS

t

glitch_filter

SCL Clock Frequency 0 100 0 400 kHz START Setup Time (SCL high before SDA low) 4.7 0.6 μs START Hold Time (SCL low after SDA low) 4.0 0.6 μs SCL Low-pulse duration 4.7 1.3 μs SCL High-pulse duration 4.0 0.6 μs SDA Hold Time (SDA valid after SCL low) 0

(2)

3.45 0 0.9 μs SDA Setup Time 250 100 ns SCL / SDA input rise time 1000 300 ns SCL / SDA input fall time 300 300 ns SDA Output fall time from VIHmin to VILmax with a bus 250 250 ns

capacitance from 10 pF to 400 pF STOP Setup Time 4.0 0.6 μs Bus free time between a STOP and START condition 4.7 1.3 μs Pulse width of spikes suppressed by the input glitch filter 75 300 75 300 ns

(1) For additional information, refer to the I2C-Bus specification, Version 2.1 (January 2000); the CDCM6208V1F meets the switching

characteristics for standard mode and fast mode transfer.

(2) The I2C master must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge

of SCL.

Figure 2. CDCM6208V1F SPI Port Timing

Product Folder Links: CDCM6208V1F

STOP

~

START

STOP

~

t

BUS

t

SU(START)

SDA

SCL

t

h(START)

t

r(SM)

t

SU(SDATA)

t

W(SCLL)tW(SCLH)

t

h(SDATA)

t

r(SM)

t

f(SM)

t

f(SM)

t

SU(STOP)

V

IH(SM)

V

IL(SM)

V

IH(SM)

V

IL(SM)

ACK

www.ti.com

8.23 SPI Timing Requirements

PARAMETER MIN NOM MAX UNIT

f

Clock Frequency for the SCL 20 MHz

Clock

t

SPI_LE to SCL setup time 10 ns

1

t

SDI to SCL setup time 10 ns

2

t

SDO to SCL hold time 10 ns

3

t

SCL high duration 25 ns

4

t

SCL low duration 25 ns

5

t

SCL to SCS Setup time 10 ns

6

t

SCS Pulse Width 20 ns

7

t

SDI to SCL Data Valid (First Valid Bit after SCS) 10 ns

8

CDCM6208V1F

SCAS943 –MAY 2015

Figure 3. I2C Timing Diagram

Product Folder Links: CDCM6208V1F

Frequency (Hz)

Jitter

2.9 ps

-50

10M10K100 1000 100k 1M

9.2 ps

0.92 ps

-60

0.29 ps

-70

-100

-80

-90

0.092 ps

-65

-55

-75

-85

-95

PSRR (dBc)

Frequency (MHz)

Jitter

0 ps-pp

60 ps-pp

100 ps-pp

120 ps-pp

140 ps-pp

180 ps-pp

200 ps-pp

400220 280 380

160 ps-pp

80 ps-pp

20 ps-pp

40 ps-pp

200 240 260 300 320 340 360

MSB-9, (1/1024) typ

all zero, (0) typ

MSB, (1/2) typ

MSB-1, (1/4) typ

MSB-2, (1/8) typ

MSB-3, (1/16) typ

MSB-4, (1/32) typ

MSB-5, (1/54) typ

MSB-6, (1/128) typ

MSB-7, (1/256) typ

MSB-13, (1/16384) typ

0x50A33D (÷x.315) typ

LSB, (1/1048576) typ

0x828F5 (÷x.51) typ

0xBAE14 (÷x.73) typ

Frequency (MHz)

Jitter

0

60

100

120

140

180

200

400

160

80

20

40

200 250 300 350

all zero, (0) max

MSB-9, (1/1024) typ

MSB-9, (1/1024) max

MSB-4, (1/32) max

MSB-13, (1/16384) max

MSB-13, (1/16384) typ

LSB, (1/1048576) max

LSB, (1/1048576) typ

MSB, (1/2) max

MSB, (1/2) typ

CDCM6208V1F

SCAS943 –MAY 2015

8.24 Typical Characteristics

www.ti.com

f

= 300 MHz

FRAC

Figure 4. Fractional Divider Bit Selection Impact on Jitter

Figure 6. Fractional Divider Bit Selection Impact on T

J

(Typical)

Using Divide by x.73 Example

Figure 5. Fractional Divider Input Frequency Impact on Jitter

Figure 7. Fractional Divider Bit Selection Impact on T

(Maximum Jitter Across Process, Voltage & Temperature)

J

f

= 122 MHz

OUT

Figure 8. PSRR (in dBc and DJ [ps]) Over Frequency [Hz] and Output Signal Format

Product Folder Links: CDCM6208V1F

(spur/20)

-12

p-p

CLK

2 x 10

x fp

CDCM6208V1F

www.ti.com

SCAS943 –MAY 2015

8.24.1 Fractional Output Divider Jitter Performance

The fractional output divider jitter performance is a function of the fraction output divider input frequency as well as actual fractional divide setting itself. To minimize the fractional output jitter, it is recommended to use the least number of fractional bits and the highest input frequency possible into the divider. As observable in Figure 4, the largest jitter contribution occurs when only one fractional divider bit is selected, and especially when the bits in the middle range of the fractional divider are selected. Tested using a LeCroy 40 Gbps RealTime scope over a time window of 200 ms. The RJimpact on TJis estimated for a BERT 10

(–12)

– 1. This measurement result is overly pessimistic, as it does not bandwidth limit the high-frequencies. In a real system, the SERDES TX will BW limit the jitter through its PLL roll-off above the TX PLL bandwidth of typically bit rate divided by 10.

8.24.2 Power Supply Ripple Rejection (PSRR) versus Ripple Frequency

See Figure 8 for reference. Many system designs become increasingly more sensitive to power supply noise rejection. In order to simplify

design and cost, the CDCM6208V1F has built in internal voltage regulation, improving the power supply noise rejection over designs with no regulators. As a result, the following output rejection is achieved:

The DJ due to PSRR can be estimated using Equation 1:

(1)

Example: Therefore, if 100 mV noise with a frequency of 10 kHz were observed at the output supply, the according output jitter for a 122.88 MHz output signal with LVDS signaling could be estimated with DJ = 0.7ps.

Product Folder Links: CDCM6208V1F

CDCM6208

LVCMOS

Phase Noise/

Spectrum

Analyzer

50 

CDCM6208

LVCMOS

Oscilloscope

High impedance probe

1mA

CDCM6208

LVCMOS

Oscilloscope

High impedance probe

1mA

VDD_Yx

CDCM6208

LVCMOS

5pF

Oscilloscope

High impedance probe

CDCM6208V1F

SCAS943 –MAY 2015

9 Parameter Measurement Information

9.1 Characterization Test Setup

This section describes the characterization test setup of each block in the CDCM6208V1F.

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Figure 9. LVCMOS Output AC Configuration During Device Test (VOH, VOL, t

Figure 10. LVCMOS Output DC Configuration During Device Test

SLEW

)

Figure 11. LVCMOS Output AC Configuration During Device Phase Noise Test

Product Folder Links: CDCM6208V1F

Signal

Generator

LVCMOS

CDCM6208

50 

Offset = VDD_PRI/SEC/2

CDCM6208

HCSL

50 50 

Balun

Phase Noise/

Spectrum

Analyzer

50 

CDCM6208

HCSL

50 

Oscilloscope

High impedance differential probe

Set to one of the following signaling

levels: LVPECL, CML, LVDS

CDCM6208

50 O

50



50



50 Balun

Phase Noise/

Spectrum

Analyzer

Y

N

Y

P

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Characterization Test Setup (continued)

Figure 12. LVDS, CML, and LVPECL Output AC Configuration During Device Test

CDCM6208V1F

SCAS943 –MAY 2015

Figure 13. HCSL Output DC Configuration During Device Test

Figure 14. HCSL Output AC Configuration During Device Test

Figure 15. LVCMOS Input DC Configuration During Device Test

Product Folder Links: CDCM6208V1F

Signal

Generator

CDCM6208

Differential

100 

VDD_PRI/SEC

100 

Signal

Generator

LVPECL

50  50 

CDCM6208

VDD_PRI/SEC - 2

Signal

Generator

LVDS

CDCM6208

LVDS

100 

Signal

Generator

CML

CDCM6208

50 

VDD_PRI/SEC

CML

CDCM6208V1F

SCAS943 –MAY 2015

Characterization Test Setup (continued)

Figure 16. CML Input DC Configuration During Device Test

Figure 17. LVDS Input DC Configuration During Device Test

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Figure 18. LVPECL Input DC Configuration During Device Test

Figure 19. Differential Input AC Configuration During Device Test

Product Folder Links: CDCM6208V1F

CDCM6208

Signal

Generator

Sine wave

Modulator

Reference

Input

Device Output

Power Supply

50 50 

Balun

Phase Noise/

Spectrum

Analyzer

50 

CDCM6208

Signal

Generator

Sine wave

Modulator

Reference

Input

Device Output

50 50 

Balun

Phase Noise/

Spectrum

Analyzer

50 

CDCM6208

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Characterization Test Setup (continued)

Figure 20. Crystal Reference Input Configuration During Device Test

CDCM6208V1F

SCAS943 –MAY 2015

Figure 21. Jitter transfer Test Setup

Figure 22. PSNR Test Setup

Product Folder Links: CDCM6208V1F

V

OUT,SE

t

20%

80%

V

OD

Yx_N

V

OUT,DIFF,PP

= 2 x V

OD

0 V

20%

80%

t

R

t

F

CDCM6208V1F

SCAS943 –MAY 2015

Characterization Test Setup (continued)

Figure 23. Differential Output Voltage and Rise and Fall Time

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Figure 24. Single Ended Output Voltage and Rise and Fall Time

Product Folder Links: CDCM6208V1F

VCXO_P

Yx_P

Yx_N

Yx_P

Yx_N

Yx_P

Yx_N

Yx_P/N

Differential

Differential, Integer Divide

Differential, Fractional Divide

Single Ended, Integer Divide

t

PD, SE

t

SK,SE,FRAC

t

PD,DIFF

t

SK,DIFF,INT

t

SK,DIFF,FRAC

Yx_P/N

t

SK,SE,INT

Single Ended, Fractional Divide

VCXO_P

Single Ended

t

SK,SE-DIFF,INT

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Characterization Test Setup (continued)

CDCM6208V1F

SCAS943 –MAY 2015

Figure 25. Differential and Single Ended Output Skew and Propagation Delay

Product Folder Links: CDCM6208V1F

Texas Instruments CDCM6208V1F Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Features 2 Applications

3 Description

4 Simplified Schematics

Table of Contents

5 Revision History

6 Description (continued)

7 Pin Configuration and Functions

8 Specifications

8.1 Absolute Maximum Ratings

8.2 ESD Ratings

8.3 Recommended Operating Conditions

8.4 Thermal Information, Airflow = 0 LFM

8.5 Thermal Information, Airflow = 150 LFM

8.6 Thermal Information, Airflow = 250 LFM

8.7 Thermal Information, Airflow = 500 LFM

8.8 Single Ended Input Characteristics

8.9 Single Ended Input Characteristics (PRI_REF, SEC_REF)

8.10 Differential Input Characteristics (PRI_REF, SEC_REF)

8.11 Crystal Input Characteristics (SEC_REF)

8.12 Single Ended Output Characteristics (STATUS1, STATUS0, SDO, SDA)

8.13 PLL Characteristics

8.14 LVCMOS Output Characteristics

8.15 LVPECL (High-Swing CML) Output Characteristics

8.16 CML Output Characteristics

8.17 LVDS (Low-Power CML) Output Characteristics

8.18 HCSL Output Characteristics

8.19 Output Skew and Sync to Output Propagation Delay Characteristics

8.20 Device Individual Block Current Consumption

8.21 Worst Case Current Consumption

8.22 I2C TIMING

8.23 SPI Timing Requirements

8.24 Typical Characteristics

8.24.1 Fractional Output Divider Jitter Performance

8.24.2 Power Supply Ripple Rejection (PSRR) versus Ripple Frequency

9 Parameter Measurement Information

9.1 Characterization Test Setup