TEXAS INSTRUMENTS CDCM1802 Technical data

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CDCM1802

CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,

LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

D Distributes One Differential Clock Input to

One LVPECL Differential Clock Output and

QFN PACKAGE

(TOP VIEW)

One LVCMOS Single-Ended Output

D Programmable Output Divider for Both

LVPECL and LVCMOS Outputs

D 1.6-ns Output Skew Between LVCMOS and

LVPECL Transitions Minimizing Noise

D 3.3-V Power Supply (2.5-V Functional)
D Signaling Rate Up to 800-MHz LVPECL and

EN

15

16

PECL

V

DD

IN

IN

1

2

3

14

S0

13

12

11

10

Vss

S1

200-MHz LVCMOS

D Differential Input Stage for Wide

Common-Mode Range Also Provides VBB

VBB

4

7

6

5

9

8

Bias Voltage Output for Single-Ended Input
Signals

D Receiver Input Threshold ±75 mV

Vss

Vss

Y1

Vdd1

D 16-Pin QFN Package (3 mm x 3 mm)

description

The CDCM1802 clock driver distributes one pair of differential clock input to one LVPECL differential clock
output pair Y0 and Y0
transmission lines. The LVCMOS output is delayed by 1.6 ns over the PECL output stage to minimize noise
impact during signal transitions.

and one single-ended LVCMOS output Y1. It is specifically designed for driving 50-Ω

V

DD

Y0

Y0

VDD0

0

The CDCM1802 has two control pins, S0 and S1, to select different output mode settings. The S[1:0] pins are
3-level inputs. Additionally, an enable pin EN is provided to disable or enable all outputs simultaneously. The
CDCM1802 is characterized for operation from −40°C to 85°C.

For single-ended driver applications, the CDCM1802 provides a VBB output pin that can be directly connected
to the unused input as a common-mode voltage reference.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2004, Texas Instruments Incorporated

1

CDCM1802
CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,
LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

functional block diagram

VBB

S1

IN

IN

Generator

VDD - 1.3 V

(i

max

Div 1
Div 2
Div 4
Div 8

Bias

< 1.5 mA)

Control

LVCMOS

LVPECL

Y1

Y0

Y0

ENS0

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CDCM1802

CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,

LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

Terminal Functions

TERMINAL

NAME NO.

EN 16 I

IN
IN

S0
S1

Y1 7 O LVCMOS clock output. This output provides a copy of IN or a divided down copy of clock

Y0
Y0

VBB 4 O Output bias voltage used to bias unused complementary input IN for single-ended input

V

SS

VDDPECL 1 Supply Supply voltage PECL input + internal logic

VDD0 9, 12 Supply PECL output supply voltage for output Y0;

VDD1 8 Supply Supply voltage CMOS output; The CMOS output can be disabled by pulling VDD1 to GND.

2
3

13
15

10
11

5, 6, 14 Supply Device ground

I/O DESCRIPTION

(with 60-kΩ pullup)

I

Differential input

I
I

(with 60-kΩ pullup)

O

LVPECL

ENABLE. Enables or disables all outputs simultaneously; The EN pin offers three
different configurations: tie to GND (logic 0), external 60-kΩ pulldown resistor (pull to

/2) or left floating (logic 1); EN = 1: outputs on according to S0 and S1 setting EN =

V

DD

V

/2: outputs on according to S0 and S1 setting EN = 0; outputs Y[1:0] off

DD

(high-impedance) see Table 1 for details.

Differential input clock. Input stage is sensitive and has a wide common mode range.
Therefore, almost any type of differential signal can drive this input (LVPECL, LVDS,
CML, HSTL). Since the input is high-impedance, it is recommended to terminate the PCB
transmission line before the input (e.g. with 100-Ω across input). The input can also be
driven by a single-ended signal, if the complementary input is tied to a dc reference
voltage (e.g. V
The inputs deploy an ESD structure protecting the inputs in case of an input voltage
exceeding the rails by more than ~0.7 V. Reverse biasing of the IC through this inputs is
possible and must be prevented by limiting the input voltage < VDD

Select mode of operation. Defines the output configuration of Y0 and Y1. Each pin offers
three different configurations: tied to GND (logic 0), external 60-kΩ pulldown resistor (pull
to VDD/2) or left floating (logic 1); see Table 1 for details

IN based on the selected mode of operation: S0, S1, and EN. Also, this output can be
disabled by tying VDD1 to GND.

LVPECL clock output. This output provides a copy of IN or a divided down copy of clock
IN based on the selected mode of operation: S1, S0, and EN. If Y0 output is unused, the
output can simply be left open to save power and minimize noise impact to Y1.

signals. The output voltage of VBB is V
drive is limited to about 1.5 mA.

Y0 can be disabled by pulling V
Caution: In this mode no voltage from outside may be forced because internal diodes
could be forced in a forward direction. Thus, it is recommended to leave the output
disconnect

Caution: In this mode no voltage from outside may be forced, because internal diodes
could be forced in forward direction. Thus, it is recommended to leave Y1 unconnected,
tied to GND or terminated into GND

CC

/2).

DD

−1.3 V. When driving a load, the output current

DD

0 to GND.

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3

CDCM1802
CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,
LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

control pin settings

The CDCM1802 has three control pins, S0, S1, and the enable pin (EN) to select different output mode settings.
All three inputs (S0, S1, EN) are 3-level inputs. In addition, the EN input allows disabling all outputs and place
them into a high-z (or tristate) output state when pulled to GND.

Setting for Mode 4:
EN = V
S1 = 0
S0 = 1

DD

/2

REN = 60 kΩ

RS1 = 0

RS0 = Open

CDCM1802

EN

S1

S0

Figure 1. Control Pin Setting for Example

Each control input incorporates a 60-kΩ pullup resistor. Thus, it is easy to choose the input setting by designing
a resistor pad between the control input and GND. To choose a logic zero, the resistor value must be zero.
Setting the input high requires leaving the resistor pad empty (no resistor installed). For setting the input to
V

/2, the installed resistor needs a value of 60 kΩ with a tolerance better or equal to 10%.

DD

Table 1. Selection Mode Table

LVPECL LVCMOS

MODE EN S1 S0 Y0 Y1

0 0 X X Off (high-z) Off (high-z)

1 VDD/2 0 VDD/2 ÷ 1 ÷ 1

2 VDD/2 VDD/2 1 ÷ 1 ÷ 2

3 1 0 0 ÷ 1 ÷ 4

4 VDD/2 0 1 ÷ 2 ÷ 2

5 1 0 1 ÷ 2 ÷ 4

6 VDD/2 0 0 ÷ 4 ÷ 4

7 VDD/2 1 0 ÷ 4 ÷ 8

8 VDD/2 VDD/2 VDD/2 ÷ 8 ÷ 1

9 1 1 0 ÷ 8 ÷ 4

10 1 1 1 Off (high-z) ÷ 4

NOTE: The LVPECL outputs are open emitter stages. Thus, if you leave the unused

LVPECL output Y0 unconnected, then the current consumption is minimized and
noise impact to remaining outputs is neglectable. Also, each output can be
individually disabled by connecting the corresponding V

input to GND.

DD

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CDCM1802

CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,

LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

V

DD

V

I

V

O

Yn, Yn, I

Supply voltage −0.3 V to 3.8 V

Input voltage −0.2 V to (VDD +0.2 V)

Output voltage −0.2 V to (VDD +0.2 V)

Differential short circuit current Continuous

OSD

†

ESD Electrostatic discharge (HBM 1.5 kΩ, 100 pF) >2000 V

Moisture level 16-pin QFN package (solder reflow temperature of 235°C) MSL 1

T

stg

T

J

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

Storage temperature −65°C to 150°C

Maximum junction temperature 125°C

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN TYP MAX UNIT

Supply voltage, V

DD

3 3.3 3.6 V

Supply voltage, VDD (only functionality) 2.375 3.6 V

Operating free-air temperature, T

A

−40 85 °C

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LVPECL INPUT IN, IN

f

clk

V

CM

V

IN

V

IN

I

IN

R

IN

C

I

LVPECL OUTPUT DRIVER Y0, Y0

f

clk

V

OH

V

OL

V

O

I

OZL

I

OZH

tr/t

t

Duty

t

sk(pp)

C

O

LOAD Expected output load 50 Ω

Input frequency 0 800 MHz

High-level input common mode 1 VDD−0.3 V

Input voltage swing between IN and IN,
See Note 1

Input voltage swing between IN and IN,
See Note 2

Input current V

= V

or 0 V ±10 µA

I

DD

500 1300 mV

150 1300 mV

Input impedance 300 kΩ

Input capacitance at IN, IN 1 pF

Output frequency, See Figure 4 0 800 MHz

High-level output voltage Termination with 50 Ω to VDD−2 V VDD−1.18 VDD–0.81 V

Low-level output voltage Termination with 50 Ω to VDD−2 V VDD−1.98 VDD–1.55 V

Output voltage swing between Y and Y,
See Figure 4

Output 3-state VDD = 3.6 V, V

Termination with 50 Ω to VDD−2 V 500 mV

= 0 V 5 µA

O

Output 3-state VDD = 3.6 V, VO = VDD – 0.8 V 10 µA

Rise and fall time 20% to 80% of V

f

see Figure 9 200 350 ps

OUTPP,

Output duty cycle distortion, See Note 3 Crossing point-to-crossing point distortion −50 50 ps

Part-to-part skew Any Y0, See Note A in Figure 8 50 ps

Output capacitance VO = VDD or GND 1 pF

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5

CDCM1802

VOHHigh level output voltage

V

VOLLow level output voltage

V

CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,
LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LVPECL INPUT-TO-LVPECL OUTPUT PARAMETER

t

pd(lh)

t

pd(hl)

t

sk(p)

NOTES: 1. Is required to maintain ac specifications

LVCMOS OUTPUT PARAMETER, Y1

f

clk

t

skLVCMOS(o)

t

sk(pp)

V

OH

V

OL

I

OH

I

OL

I

OZ

C

O

Load Expected output loading, see Figure 10 10 pF

t

Duty

t

pd(lh)

t

pd(hl)

t

r

t

f

NOTES: 4. Operating the CDCM1802 LVCMOS output above the maximum frequency will not cause a malfunction to the device, but the Y1

Propagation delay rising edge VOX to VOX 320 600 ps

Propagation delay falling edge VOX to VOX 320 600 ps

LVPECL pulse skew, See Note B in Figure 8 VOX to VOX 100 ps

2. Is required to maintain device functionality

3. For a 800-MHz signal, the 50-ps error would result into a duty cycle distortion of ±4% when driven by an ideal clock input signal.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output frequency, see Note 4 and
Figure 5

Output skew between the LVCMOS
output Y1 and LVPECL output Y0

VOX to VDD/2, See Figure 8 1.6 ns

0 200 MHz

Part-to-part skew Y1, See Note A in Figure 8 300 ps

High-level output voltage

V

= min to max, I

DD

V

= 3 V, I

DD

VDD = 3 V, I

= −100 µA VDD–0.1

OH

= −6 mA 2.4

OH

= −12 mA 2

OH

V

VDD = min to max, IOL=100 µA 0.1

V

Low-level output voltage

= 3 V, I

DD

VDD = 3 V, I

High-level output current VDD = 3.3 V, V

Low-level output current VDD = 3.3 V, V

= 6 mA 0.5

OL

= 12 mA 0.8

OL

= 1.65 V −29 mA

O

= 1.65 V 37 mA

O

V

High-impedance state output current VDD = 3.6 V, VO = VDD or 0 V ±5 µA

Output capacitance V

= 3.3 V 2 pF

DD

Output duty cycle distortion, see Note 5 Measured at VDD/2 −150 150 ps

Propagation delay rising edge from IN
to Y1

Propagation delay falling edge from IN
to Y1

VOX to VDD/2 load, see Figure 10 1.6 2.6 ns

VOX to VDD/2 load, see Figure 10 1.6 2.6 ns

Output rise slew rate 20% to 80% of swing, see Figure 10 1.4 2.3 V/ns

Output fall slew rate 80% to 20% of swing, see Figure 10 1.4 2.3 V/ns

output signal swing will not achieve enough signal swing to meet the output specification. Therefore, the CDCM1802 can be operated
at higher frequencies, while the LVCMOS output Y1 becomes unusable.

5. For a 200-MHz signal, the 150-ps error would result in a duty cycle distortion of ±3% when driven by an ideal clock input signal.

6

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jitter characteristics

/

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Additive phase jitter from input to

t

jitterLVPECL

t

jitterLVCMOS

LVPECL output Y0,
See Figure 2

Additive phase jitter from input to
LVCMOS output Y1,
See Figure 3

CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,

12 kHz to 20 MHz, f
divide by 1 mode

50 kHz to 40 MHz, f
divide by 1 mode

12 kHz to 20 MHz, f
divide by 1 mode

50 kHz to 40 MHz, f
divide by 1 mode

CDCM1802

LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

= 250 MHz to 800 MHz,

out

= 250 MHz to 800 MHz,

out

= 250 MHz,

out

= 250 MHz,

out

0.15

ps rms

0.25

0.25 ps rms

0.4 ps rms

ADDITIVE PHASE NOISE

vs

FREQUENCY OFFSET FROM CARRIER − LVPECL

−110

−115

−120

−125

−130

−135

−140

−145

−150

Additive Phase Noise − dBc/Hz

−155

−160

VDD = 3.3 V
T

= 25°C

A

f = 622 MHz
÷1 Mode

10 100 1k 100M10k 100k 10M1M

f − Frequency Offset From Carrier − Hz

Figure 2

ADDITIVE PHASE NOISE

vs

FREQUENCY OFFSET FROM CARRIER − LVCMOS

−100

−105

−110

Hz

−115

−120

−125

−130

−135

−140

−145

Additive Phase Noise − dBc

−150

−155

−160

10 100 1k 100M10k 100k 10M1M

f − Frequency Offset From Carrier − Hz

VDD = 3.3 V
T

= 25°C

A

f = 250 MHz
÷1 Mode

Figure 3

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7