TEXAS INSTRUMENTS CDCM1802 Technical data

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CDCM1802

CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,

LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

D Distributes One Differential Clock Input to

One LVPECL Differential Clock Output and

QFN PACKAGE

(TOP VIEW)

One LVCMOS Single-Ended Output

D Programmable Output Divider for Both

LVPECL and LVCMOS Outputs

D 1.6-ns Output Skew Between LVCMOS and

LVPECL Transitions Minimizing Noise

D 3.3-V Power Supply (2.5-V Functional) D Signaling Rate Up to 800-MHz LVPECL and

PECL

Vss

200-MHz LVCMOS

D Differential Input Stage for Wide

Common-Mode Range Also Provides VBB

VBB

Bias Voltage Output for Single-Ended Input Signals

D Receiver Input Threshold ±75 mV

Vss

Vdd1

D 16-Pin QFN Package (3 mm x 3 mm)

description

The CDCM1802 clock driver distributes one pair of differential clock input to one LVPECL differential clock output pair Y0 and Y0 transmission lines. The LVCMOS output is delayed by 1.6 ns over the PECL output stage to minimize noise impact during signal transitions.

and one single-ended LVCMOS output Y1. It is specifically designed for driving 50-Ω

VDD0

The CDCM1802 has two control pins, S0 and S1, to select different output mode settings. The S[1:0] pins are 3-level inputs. Additionally, an enable pin EN is provided to disable or enable all outputs simultaneously. The CDCM1802 is characterized for operation from −40°C to 85°C.

For single-ended driver applications, the CDCM1802 provides a VBB output pin that can be directly connected to the unused input as a common-mode voltage reference.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

functional block diagram

VBB

Generator

VDD - 1.3 V

max

Div 1 Div 2 Div 4 Div 8

Bias

< 1.5 mA)

Control

LVCMOS

LVPECL

ENS0

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CDCM1802

CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,

LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

Terminal Functions

TERMINAL

NAME NO.

EN 16 I

IN IN

S0 S1

Y1 7 O LVCMOS clock output. This output provides a copy of IN or a divided down copy of clock

Y0 Y0

VBB 4 O Output bias voltage used to bias unused complementary input IN for single-ended input

VDDPECL 1 Supply Supply voltage PECL input + internal logic

VDD0 9, 12 Supply PECL output supply voltage for output Y0;

VDD1 8 Supply Supply voltage CMOS output; The CMOS output can be disabled by pulling VDD1 to GND.

2 3

13 15

10 11

5, 6, 14 Supply Device ground

I/O DESCRIPTION

(with 60-kΩ pullup)

Differential input

I I

(with 60-kΩ pullup)

LVPECL

ENABLE. Enables or disables all outputs simultaneously; The EN pin offers three different configurations: tie to GND (logic 0), external 60-kΩ pulldown resistor (pull to

/2) or left floating (logic 1); EN = 1: outputs on according to S0 and S1 setting EN =

/2: outputs on according to S0 and S1 setting EN = 0; outputs Y[1:0] off

(high-impedance) see Table 1 for details.

Differential input clock. Input stage is sensitive and has a wide common mode range. Therefore, almost any type of differential signal can drive this input (LVPECL, LVDS, CML, HSTL). Since the input is high-impedance, it is recommended to terminate the PCB transmission line before the input (e.g. with 100-Ω across input). The input can also be driven by a single-ended signal, if the complementary input is tied to a dc reference voltage (e.g. V The inputs deploy an ESD structure protecting the inputs in case of an input voltage exceeding the rails by more than ~0.7 V. Reverse biasing of the IC through this inputs is possible and must be prevented by limiting the input voltage < VDD

Select mode of operation. Defines the output configuration of Y0 and Y1. Each pin offers three different configurations: tied to GND (logic 0), external 60-kΩ pulldown resistor (pull to VDD/2) or left floating (logic 1); see Table 1 for details

IN based on the selected mode of operation: S0, S1, and EN. Also, this output can be disabled by tying VDD1 to GND.

LVPECL clock output. This output provides a copy of IN or a divided down copy of clock IN based on the selected mode of operation: S1, S0, and EN. If Y0 output is unused, the output can simply be left open to save power and minimize noise impact to Y1.

signals. The output voltage of VBB is V drive is limited to about 1.5 mA.

Y0 can be disabled by pulling V Caution: In this mode no voltage from outside may be forced because internal diodes could be forced in a forward direction. Thus, it is recommended to leave the output disconnect

Caution: In this mode no voltage from outside may be forced, because internal diodes could be forced in forward direction. Thus, it is recommended to leave Y1 unconnected, tied to GND or terminated into GND

/2).

−1.3 V. When driving a load, the output current

0 to GND.

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CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

control pin settings

The CDCM1802 has three control pins, S0, S1, and the enable pin (EN) to select different output mode settings. All three inputs (S0, S1, EN) are 3-level inputs. In addition, the EN input allows disabling all outputs and place them into a high-z (or tristate) output state when pulled to GND.

Setting for Mode 4: EN = V S1 = 0 S0 = 1

REN = 60 kΩ

RS1 = 0

RS0 = Open

CDCM1802

Figure 1. Control Pin Setting for Example

Each control input incorporates a 60-kΩ pullup resistor. Thus, it is easy to choose the input setting by designing a resistor pad between the control input and GND. To choose a logic zero, the resistor value must be zero. Setting the input high requires leaving the resistor pad empty (no resistor installed). For setting the input to V

/2, the installed resistor needs a value of 60 kΩ with a tolerance better or equal to 10%.

Table 1. Selection Mode Table

LVPECL LVCMOS

MODE EN S1 S0 Y0 Y1

0 0 X X Off (high-z) Off (high-z)

1 VDD/2 0 VDD/2 ÷ 1 ÷ 1

2 VDD/2 VDD/2 1 ÷ 1 ÷ 2

3 1 0 0 ÷ 1 ÷ 4

4 VDD/2 0 1 ÷ 2 ÷ 2

5 1 0 1 ÷ 2 ÷ 4

6 VDD/2 0 0 ÷ 4 ÷ 4

7 VDD/2 1 0 ÷ 4 ÷ 8

8 VDD/2 VDD/2 VDD/2 ÷ 8 ÷ 1

9 1 1 0 ÷ 8 ÷ 4

10 1 1 1 Off (high-z) ÷ 4

NOTE: The LVPECL outputs are open emitter stages. Thus, if you leave the unused

LVPECL output Y0 unconnected, then the current consumption is minimized and noise impact to remaining outputs is neglectable. Also, each output can be individually disabled by connecting the corresponding V

input to GND.

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CDCM1802

CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,

LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Yn, Yn, I

Supply voltage −0.3 V to 3.8 V

Input voltage −0.2 V to (VDD +0.2 V)

Output voltage −0.2 V to (VDD +0.2 V)

Differential short circuit current Continuous

OSD

†

ESD Electrostatic discharge (HBM 1.5 kΩ, 100 pF) >2000 V

Moisture level 16-pin QFN package (solder reflow temperature of 235°C) MSL 1

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

Storage temperature −65°C to 150°C

Maximum junction temperature 125°C

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN TYP MAX UNIT

Supply voltage, V

3 3.3 3.6 V

Supply voltage, VDD (only functionality) 2.375 3.6 V

Operating free-air temperature, T

−40 85 °C

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LVPECL INPUT IN, IN

clk

LVPECL OUTPUT DRIVER Y0, Y0

clk

OZL

OZH

tr/t

Duty

sk(pp)

LOAD Expected output load 50 Ω

Input frequency 0 800 MHz

High-level input common mode 1 VDD−0.3 V

Input voltage swing between IN and IN, See Note 1

Input voltage swing between IN and IN, See Note 2

Input current V

= V

or 0 V ±10 µA

500 1300 mV

150 1300 mV

Input impedance 300 kΩ

Input capacitance at IN, IN 1 pF

Output frequency, See Figure 4 0 800 MHz

High-level output voltage Termination with 50 Ω to VDD−2 V VDD−1.18 VDD–0.81 V

Low-level output voltage Termination with 50 Ω to VDD−2 V VDD−1.98 VDD–1.55 V

Output voltage swing between Y and Y, See Figure 4

Output 3-state VDD = 3.6 V, V

Termination with 50 Ω to VDD−2 V 500 mV

= 0 V 5 µA

Output 3-state VDD = 3.6 V, VO = VDD – 0.8 V 10 µA

Rise and fall time 20% to 80% of V

see Figure 9 200 350 ps

OUTPP,

Output duty cycle distortion, See Note 3 Crossing point-to-crossing point distortion −50 50 ps

Part-to-part skew Any Y0, See Note A in Figure 8 50 ps

Output capacitance VO = VDD or GND 1 pF

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CDCM1802

VOHHigh level output voltage

VOLLow level output voltage

CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LVPECL INPUT-TO-LVPECL OUTPUT PARAMETER

pd(lh)

pd(hl)

sk(p)

NOTES: 1. Is required to maintain ac specifications

LVCMOS OUTPUT PARAMETER, Y1

clk

skLVCMOS(o)

sk(pp)

Load Expected output loading, see Figure 10 10 pF

Duty

pd(lh)

pd(hl)

NOTES: 4. Operating the CDCM1802 LVCMOS output above the maximum frequency will not cause a malfunction to the device, but the Y1

Propagation delay rising edge VOX to VOX 320 600 ps

Propagation delay falling edge VOX to VOX 320 600 ps

LVPECL pulse skew, See Note B in Figure 8 VOX to VOX 100 ps

2. Is required to maintain device functionality

3. For a 800-MHz signal, the 50-ps error would result into a duty cycle distortion of ±4% when driven by an ideal clock input signal.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output frequency, see Note 4 and Figure 5

Output skew between the LVCMOS output Y1 and LVPECL output Y0

VOX to VDD/2, See Figure 8 1.6 ns

0 200 MHz

Part-to-part skew Y1, See Note A in Figure 8 300 ps

High-level output voltage

= min to max, I

= 3 V, I

VDD = 3 V, I

= −100 µA VDD–0.1

= −6 mA 2.4

= −12 mA 2

VDD = min to max, IOL=100 µA 0.1

Low-level output voltage

= 3 V, I

VDD = 3 V, I

High-level output current VDD = 3.3 V, V

Low-level output current VDD = 3.3 V, V

= 6 mA 0.5

= 12 mA 0.8

= 1.65 V −29 mA

= 1.65 V 37 mA

High-impedance state output current VDD = 3.6 V, VO = VDD or 0 V ±5 µA

Output capacitance V

= 3.3 V 2 pF

Output duty cycle distortion, see Note 5 Measured at VDD/2 −150 150 ps

Propagation delay rising edge from IN to Y1

Propagation delay falling edge from IN to Y1

VOX to VDD/2 load, see Figure 10 1.6 2.6 ns

Output rise slew rate 20% to 80% of swing, see Figure 10 1.4 2.3 V/ns

Output fall slew rate 80% to 20% of swing, see Figure 10 1.4 2.3 V/ns

output signal swing will not achieve enough signal swing to meet the output specification. Therefore, the CDCM1802 can be operated at higher frequencies, while the LVCMOS output Y1 becomes unusable.

5. For a 200-MHz signal, the 150-ps error would result in a duty cycle distortion of ±3% when driven by an ideal clock input signal.

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jitter characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Additive phase jitter from input to

jitterLVPECL

jitterLVCMOS

LVPECL output Y0, See Figure 2

Additive phase jitter from input to LVCMOS output Y1, See Figure 3

CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,

12 kHz to 20 MHz, f divide by 1 mode

50 kHz to 40 MHz, f divide by 1 mode

12 kHz to 20 MHz, f divide by 1 mode

50 kHz to 40 MHz, f divide by 1 mode

CDCM1802

LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

= 250 MHz to 800 MHz,

out

= 250 MHz to 800 MHz,

out

= 250 MHz,

out

= 250 MHz,

out

0.15

ps rms

0.25

0.25 ps rms

0.4 ps rms

ADDITIVE PHASE NOISE

FREQUENCY OFFSET FROM CARRIER − LVPECL

−110

−115

−120

−125

−130

−135

−140

−145

−150

Additive Phase Noise − dBc/Hz

−155

−160

VDD = 3.3 V T

= 25°C

f = 622 MHz ÷1 Mode

10 100 1k 100M10k 100k 10M1M

f − Frequency Offset From Carrier − Hz

Figure 2

ADDITIVE PHASE NOISE

FREQUENCY OFFSET FROM CARRIER − LVCMOS

−100

−105

−110

−115

−120

−125

−130

−135

−140

−145

Additive Phase Noise − dBc

−150

−155

−160

10 100 1k 100M10k 100k 10M1M

f − Frequency Offset From Carrier − Hz

VDD = 3.3 V T

= 25°C

f = 250 MHz ÷1 Mode

Figure 3

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CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

jitter characteristics (continued)

AMPLITUDE PECL PEAK-TO-PEAK

FREQUENCY

0.90

0.85

0.80

0.75

0.70

0.65

0.60

0.55

0.50

Amplitude PECL Peak-to-Peak − V

0.45

0.40

0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5

2.375 V

Mode = 1 (Divider: Y0 = 1, Y1 = 1 ) Input Swing = 500 mV

Load = See Figure 11

f − Frequency − GHz

3 V

3.3 V

2.625 V

Figure 4

2.5 V

3.6 V

3.5

3.0

2.5

2.0

1.5

1.0

Amplitude CMOS Peak-to-Peak − V

0.5

0.0

AMPLITUDE CMOS PEAK-TO-PEAK

FREQUENCY

3.6 V

3.3 V

3 V

2.625 V

2.5 V

Mode = 1 ( divider: Y0 = 1, Y1 = 1 ) Input Swing = 500 mV Load = See Figure 10

50 100 150 200 250 300 350 400 450 500

f − Frequency − MHz

2.375 V

Figure 5

supply current electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

All outputs enabled and terminated with 50 Ω to V

− 2 V on LVPECL outputs and 10 pF on LVCMOS output,

Full load

Supply current

No load

Supply current, 3-state All outputs 3-state by control logic, f = 0 Hz, VDD = 3.6 V 0.5 mA

DDZ

f = 800 MHz for LVPECL outputs and 200 MHz for LVCMOS, VDD = 3.3 V

Outputs enabled, no output load, f = 800 MHz for LVPECL outputs and 200 MHz for LVCMOS, V

= 3.6 V

100

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CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,

LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SUPPLY CURRENT

FREQUENCY

110

CMOS and PECL Running (Mode 3)

100

− Supply Current − mA

NOTE: Input swing = 500 mV

CMOS Off, PECL Running

CMOS and PECL

0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5

Running, No Load

f − Frequency − GHz

CMOS Running,

PECL Off (Mode 10)

CDCM1802

SCAS759 − APRIL 2004

Figure 6

Package Thermal Resistance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

NOTE 1: It is recommended to provide four thermal vias to connect the thermal pad of the package effectively with the PCB and ensure a good

QFN−16 package thermal resistance with thermal vias in PCB, See Note 1

heat sink.

Example:

Calculation of the junction-lead temperature with a 4-layer JEDEC test board using four thermal vias:

∆T

= 85°C (temperature of the chassis)

Chassis

= I

effective

Junction

= θ

= ∆T

max

Junction

x V

x P

= 85 mA x 3.6 V = 306 mW (max power consumption inside the package)

max

= 40.8°C/W x 306 mW = 12.48°C

effective

+ T

Chassis

= 125°C is not violated)

4-layer JEDEC test board (JESD51−7) with four thermal vias of 22-mil diameter each, airflow = 0 ft/min

= 12.48°C + 85°C = 97.48°C (the maximum junction temperature of T

40.8 °C/W

die−max

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CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

control input characteristics over recommended operating free-air temperature range

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

(disable)

(enable)

Rpullup Internal pullup resistor on S0, S1, and EN input 42 60 78 kΩ

IH(H)

IM(M)

IL(L)

NOTES: 1. Leaving this pin floating automatically pulse the logic level high to VDD through an internal pullup resistor of 60 kΩ.

bias voltage VBB over recommended operating free-air temperature range

VBB Output reference voltage VDD = 3 V − 3.6 V, IBB = −0.2 mA VDD − 1.4 VDD − 1.2 V

Setup time, S0, S1, and EN pin before clock IN 25 ns

Hold time, S0, S1, and EN pin after clock IN 0 ns

Time between latching the EN low transition and when all outputs are disabled (how much time is required until the outputs turn off)

Time between latching the EN low-to-high transition and when outputs are enabled based on control settings (how much time passes before the outputs carry valid signals)

Three level input high, S0, S1, and EN pin, see Note 1 0.9xV

Three level input MID, S0, S1, and EN pin 0.3xV

Three level low, S0, S1, and EN pin 0.1xV

Input current, S0, S1, and EN pin VI = V

Input current, S0, S1, and EN pin VI = GND 38 85 µA

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

10 ns

1 µs

0.7xV

−5 µA

OUTPUT REFERENCE VOLTAGE (VBB)

4.0

3.5

3.0

2.5

2.0

1.5

1.0

− Output Reference Voltage − V

0.5

0.0

−5 0 5 101520253035

LOAD

VDD = 3.3 V

I − Load − mA

Figure 7

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CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,

LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

PARAMETER MEASUREMENT INFORMATION

PHLO

CDCM1802

SCAS759 − APRIL 2004

NOTES: A. Part-to-part skew, t

− The difference between the fastest and the slowest t

B. Pulse skew, t

pd(LH)

sk(p)

) propagation delays when a single switching input causes Y0 to switch, t

referred to as pulse width distortion or duty cycle skew.

|Yn*Yn|

skLVCMOS(o)

, is calculated as the greater of:

sk(pp)

0.5 X V

across multiple devices

pd(LH)n

across multiple devices

pd(HL)n

, is calculated as the magnitude of the absolute time difference between the high-to-low (t

Figure 8. Waveforms for Calculation of t

sk(o)

= | t

sk(p)

and t

pd(HL)

sk(pp)

− t

|. Pulse skew is sometimes

pd(LH)

80%

0 V

OUT(pp)

20%

) and the low-to-high

pd(HL

Figure 9. LVPECL Differential Output Voltage and Rise/Fall Time

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CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

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PARAMETER MEASUREMENT INFORMATION

CDCM1802

1 kΩ

LVCMOS

1 kΩ

10 pF

Figure 10. LVCMOS Output Loading During Device Test

CDCM1802

(VDD − 2 V)

50 Ω

LVPECL

Y0, Y0

Figure 11. LVPECL Output Loading During Device Test

PCB design for thermal functionality

It is recommended to take special care of the PCB design for good thermal flow from the QFN−16 pin package to the PCB. The current consumption of the CDCM1802 is fixed. JEDEC JESD51−7 specifies thermal conductivity for standard PCB boards.

Modeling the CDCM1802 with a 4−layer JEDEC board (including four thermal vias) results into 37.5_C max temperature with a θ

To ensure sufficient thermal flow, it is recommended to design with four thermal vias in applications.

of 40.84_C for 25_C ambient temperature.

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CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,

LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

PARAMETER MEASUREMENT INFORMATION

Package Thermal Pad

Thermal Via

Dia 0.020 In.

Top Side

Island

CDCM1802

SCAS759 − APRIL 2004

(Underside)

Heat

Dissipation

VSS Copper Plane

Figure 12. Recommended Thermal Via Placement

VSS Copper Plane

See the SCBA017 and the SLUA271 application notes for further package related information.

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CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

APPLICATION INFORMATION

LVPECL receiver input termination

The input of the CDCM1802 has high impedance and comes with a very large common mode voltage range. For optimized noise performance it is recommended to properly terminate the PCB trace (transmission line).

Additional termination techniques can be found in the following application notes: SCAA062 and SCAA059.

http://focus.ti.com/docs/apps/catalog/resources/appnoteabstract.jhtml?abstractName=scaa062

http://focus.ti.com/docs/apps/catalog/resources/appnoteabstract.jhtml?abstractName=scaa059

CDCM1802

LVPECL

150 Ω

50 Ω

LVPECL

50 Ω

VBB

150 Ω

50 Ω

Figure 13. Recommended AC-Coupling LVPECL Receiver Input Termination

CDCM1802

130 Ω

50 Ω

83 Ω

130 Ω

50 Ω

83 Ω

Figure 14. Recommended DC-Coupling LVPECL Receiver Input Termination

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CLK

NOTE: CAC − AC-coupling capacitor (e.g., 10 nF)

− Capacitor keeps voltage at IN constant (e.g., 10 nF)

− Load and correct duty cycle (e.g., 50 Ω)

− Bias voltage output

Figure 15. Typical Application Setting for Single-Ended Input Signals Driving the CDCM1802

CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,

LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

APPLICATION INFORMATION

CDCM1802

VBB

CDCM1802

SCAS759 − APRIL 2004

device behavior during RESET and control pin switching

output behavior when enabling the device (EN = 0 % 1)

In disable mode (EN = 0), all output drivers are switched in high-Z mode. The bandgap, current references, the amplifier, and the S0 and S1 control inputs are also switched off. In the same mode, all flip-flops will be reset. The typical current consumption is likely below 500 µA (to be measured).

When the device will be enabled again it takes maximal 1 µs for the settling of the reference voltage and currents. During this time the output Y0 and Y0 time, the outputs go into the low state. Due to the synchronization of each output driver signal with the input clock, the state of the waveforms after enabling the device look like those shown in Figure 16. The inverting input and output signal is not included. The Y:/1 waveform is the undivided output driver state.

drive a high signal. Y1 is unknown (could be high or low). After the settle

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APPLICATION INFORMATION

1 µs

Y:/1 Undefined

High-Z

High-ZY:/2 Undefined

High-ZY:/4 Undefined

Signal State After the Device is Enabled (IN = Low)

1 µs

High-Z

High-ZY:/2 Undefined

Low

Undivided State is Valid After the First

Positive Transition of the Input Clock

Low

High-ZY:/4 Undefined

Signal State After the Device is Enabled (IN = High)

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Low

Figure 16. Waveforms

CDCM1802

CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,

LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

APPLICATION INFORMATION

enabling a single output stage

If a single output stage becomes enabled:

1. Y0 will either be low or high (undefined).

will be the inverted signal of Y0.

2. Y0

With the first positive clock transition, the undivided output becomes the input clock state. If a divide mode is used, the divided output states are equal to the actual internal divider. The internal divider does not get a reset while enabling single output drivers.

ENABLE Yx:

Yx:/1

ENABLE Yx:

Yx:/1 Undefined

EnabledDisabled

High-Z

High-ZYx:/x Undefined

Undefined

Undivided State is Valid After the First

Positive Transition of the Input Clock

Divider State

Figure 17. Signal State After an Output Driver Becomes Enabled While IN = 0

EnabledDisabled

High-Z

High-ZYx:/x Undefined

Undivided State is Valid After the First

Positive Transition of the Input Clock

Divider State

Figure 18. Signal State After an Output Driver Becomes Enabled While IN = 1

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MECHANICAL DATA

Also see the following two application notes for further package related information.

http://focus.ti.com/lit/an/scba017c/scba017c.pdf http://focus.ti.com/lit/an/slua271/slua271.pdf

1.55

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1) All linear dimensions are in millimeters

2) The pin 1 indentification mark is electrically connected to the center thermal pad

4206349-3/B 11/04

PACKAGE OPTION ADDENDUM

www.ti.com

30-Mar-2005

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

CDCM1802RGTR ACTIVE QFN RGT 16 3000 TBD CU NIPDAU Level-1-235C-UNLIM

CDCM1802RGTT ACTIVE QFN RGT 16 250 TBD CU NIPDAU Level-1-235C-UNLIM

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

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TEXAS INSTRUMENTS CDCM1802 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual