TEXAS INSTRUMENTS CDCFR83 Technical data

查询CDCFR83供应商

D

533-MHz Differential Clock Source for
Direct Rambus
1066-MHz Data Transfer Rate

D

Synchronizes the Clock Domains of the
Rambus Channel With an External System
or Processor Clock

D

Three Power Operating Modes to Minimize
Power for Mobile and Other
Power-Sensitive Applications

D

Operates From a Single 3.3-V Supply and
120 mW at 300 MHz (Typ)

D

Packaged in a Shrink Small-Outline
Package (DBQ)

D

Supports Frequency Multipliers: 4, 6, 8,
16/3

D

No External Components Required for PLL

D

Supports Independent Channel Clocking

D

Spread Spectrum Clocking Tracking
Capability to Reduce EMI

D

Designed for Use With TI’s 133-MHz Clock
Synthesizers CDC924 and CDC921

description

The Direct Rambus clock generator (DRCG) provides the necessary clock signals to support a Direct Rambus
memory subsystem. It includes signals to synchronize the Direct Rambus channel clock to an external system
or processor clock. It is designed to support Direct Rambus memory on a desktop, workstation, server, and
mobile PC motherboards. DRCG also provides an off-the-shelf solution for a broad range of Direct Rambus
memory applications.

The DRCG provides clock multiplication and phase alignment for a Direct Rambus memory subsystem to
enable synchronous communication between the Rambus channel and ASIC clock domains. In a Direct
Rambus memory subsystem, a system clock source provides the REFCLK and PCLK clock references to the
DRCG and memory controller, respectively. The DRCG multiplies REFCLK and drives a high-speed BUSCLK
to RDRAMs and the memory controller. Gear ratio logic in the memory controller divides the PCLK and BUSCLK
frequencies by ratios M and N such that PCLKM = SYNCLKN, where SYNCLK = BUSCLK/4. The DRCG detects
the phase difference between PCLKM and SYNCLKN and adjusts the phase of BUSCLK such that the skew
between PCLKM and SYNCLKN is minimized. This allows data to be transferred across the SYNCLK/PCLK
boundary without incurring additional latency.

User control is provided by multiply and mode selection terminals. The multiply terminals provide selection of
one of four clock frequency multiply ratios, generating BUSCLK frequencies ranging from 267 MHz to 533 MHz
with clock references ranging from 33 MHz to 100 MHz. The mode select terminals can be used to select a
bypass mode where the frequency multiplied reference clock is directly output to the Rambus channel for
systems where synchronization between the Rambus clock and a system clock is not required. T est modes are
provided to bypass the PLL and output REFCLK on the Rambus channel and to place the outputs in a
high-impedance state for board testing.



Memory Systems for an

CDCFR83

DIRECT RAMBUS CLOCK GENERATOR

SCAS665A – APRIL 2001 REVISED MARCH 2002

D

Cycle-Cycle Jitter Is Less Than 40 ps at
533 MHz

D

Certified by Gigatest Labs to Exceed the
Rambus DRCG Validation Requirement

D

Supports Industrial Temperature Range of

°

–40

C to 85°C

DBQ PACKAGE

(TOP VIEW)

VDDIR

REFCLK

V

GNDP

GNDI

PCLKM

SYNCLKN

GNDC

V

V

DD

STOPB

PWRDNB

NC – No internal connection

DD

DD

IPD

1
2

P

3
4
5
6
7
8

C

9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

S0
S1
V

O

DD

GNDO
CLK
NC
CLKB
GNDO
V

O

DD

MULT0
MULT1
S2

The CDCFR83 is characterized for operation over free-air temperatures of –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Direct Rambus and Rambus are trademarks of Rambus Inc.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2002, Texas Instruments Incorporated

1

CDCFR83

DIRECT RAMBUS CLOCK GENERATOR

SCAS665A – APRIL 2001 REVISED MARCH 2002

functional block diagram

PWRDWNB S0 S1 S2 STOPB

Test MUX

PLLCLK

REFCLK

PLL

B

Phase

Aligner

Bypass MUX

ByPCLK

CLK
CLKB

A

φ

2

MULT0
MULT1

FUNCTION TABLE

MODE

Normal 0 0 0 Phase aligned clock Phase aligned clock B
Bypass 1 0 0 PLLCLK PLLCLKB
Test 1 1 0 REFCLK REFCLKB
Output test (OE) 0 1 X Hi-Z Hi-Z
Reserved 0 0 1 — —
Reserved 1 0 1 — —
Reserved 1 1 1 Hi-Z Hi-Z

†

X = don’t care, Hi-Z = high impedance

S0 S1 S2 CLK CLKB

PACLK

D

SYNCLKNPCLKM

†

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DIRECT RAMBUS CLOCK GENERATOR

I/O

DESCRIPTION

Terminal Functions

TERMINAL

NAME NO.

CLK 20 O Output clock
CLKB 18 O Output clock (complement)
GNDC 8 GND for phase aligner
GNDI 5 GND for control inputs
GNDO 17, 21 GND for clock outputs
GNDP 4 GND for PLL
MULT0 15 I PLL multiplier select
MULT1 14 I PLL multiplier select
NC 19 Not used
PCLKM 6 I Phase detector input
PWRDNB 12 I Active low power down
REFCLK 2 I Reference clock
S0 24 I Mode control
S1 23 I Mode control
S2 13 I Mode control
STOPB 11 I Active low output disable
SYNCLKN 7 I Phase detector input
VDDC 9 VDD for phase aligner
VDDIPD 10 Reference voltage for phase detector inputs and STOPB
VDDIR 1 Reference voltage for REFCLK
VDDO 16, 22 VDD for clock outputs
VDDP 3 VDD for PLL

CDCFR83

SCAS665A – APRIL 2001 REVISED MARCH 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

CDCFR83

DIRECT RAMBUS CLOCK GENERATOR

SCAS665A – APRIL 2001 REVISED MARCH 2002

PLL divider selection

Table 1 lists the supported REFCLK and BUSCLK frequencies. Other REFCLK frequencies are permitted,
provided that (267 MHz < BUSCLK < 533 MHz) and (33 MHz < REFCLK < 100 MHz).

Table 1. REFCLK and BUSCLK Frequencies

MULT0 MULT1

0 0 67 4 267
0 1 50 6 300
0 1 67 6 400
1 1 33 8 267
1 1 50 8 400
1 1 67 8 533
1 0 67 16/3 356

REFCLK

(MHz)

MULTIPLY

RATIO

BUSCLK

(MHz)

Table 2. Clock Output Driver States

STATE PWRDNB STOPB CLK CLKB

Powerdown 0 X GND GND

CLK stop 1 0 VX,

Normal 1 1

†

Depending on the state of S0, S1, and S2

STOP

PACLK/PLLCLK/

REFCLK

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range, V
Output voltage range, V
Input voltage range,V

(see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DD

, at any output terminal –0.5 V to V

O

, at any input terminal –0.5 V to VDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

VX,

STOP

PACLKB/PLLCLKB/

REFCLKB

DD

†

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation see Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T
Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

–40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to the GND terminals.

DISSIPATION RATING TABLE

PACKAGE

DBQ 1400 mW 11 mW/°C 905 mW 740 mW

‡

This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.

4

TA ≤ 25°C

POWER RATING

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DERATING FACTOR

ABOVE TA = 25°C

‡

POWER RATING

TA = 70°C

TA = 85°C

POWER RATING

CDCFR83

DIRECT RAMBUS CLOCK GENERATOR

SCAS665A – APRIL 2001 REVISED MARCH 2002

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V
High-level input voltage, VIH (CMOS) 0.7 ×V
Low-level input voltage, VIL (CMOS) 0.3 × V
Initial phase error at phase detector inputs (required range for phase aligner) –0.5 × t
REFCLK low-level input voltage, V
REFCLK high-level input voltage, V
Input signal low voltage, VIL (STOPB) 0.3 × VDDIPD V
Input signal high voltage, VIH (STOPB) 0.7 × VDDIPD V
Input reference voltage for (REFCLK) (VDDIR) 1.235 3.465 V
Input reference voltage for (PCLKM and SYSCLKN) (VDDIPD) 1.235 3.465 V
High-level output current, I
Low-level output current, I
Operating free-air temperature, T

DD

IL

IH

OH

OL

A

timing requirements

Input cycle time, t
Input cycle-to-cycle jitter 250 ps
Input duty cycle over 10,000 cycles 40% 60%
Input frequency modulation, f
Modulation index, nonlinear maximum 0.5% 0.6%
Phase detector input cycle time (PCLKM and SYNCLKN) 30 100 ns
Input slew rate, SR 1 4 V/ns
Input duty cycle (PCLKM and SYNCLKN) 25% 75%

c(in)

mod

3.135 3.3 3.465 V
DD

DD

c(PD)

0.7 × VDDIR V

–40 85 °C

0.5 × t

c(PD)

0.3 × VDDIR V

–16 mA

16 mA

MIN MAX UNIT

10 40 ns

30 33 kHz

V
V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

CDCFR83

I

g

A

I

A

Z

Ω

VDDIR, VDDIPD

V

3.465 V

DIRECT RAMBUS CLOCK GENERATOR

SCAS665A – APRIL 2001 REVISED MARCH 2002

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS

V

O(STOP)

V

O(X)

V

O

V

IK

V

OH

V

OL

I

OH

I

OL

I

OZ

I

OZ(STOP)

I

OZ(PD)

IH

IL

O

C

I

C

O

I

DD(PD)

I

DD(CLKSTOP)

I

DD(NORMAL)

†

VDD refers to any of the following; VDD, VDDIPD, VDDIR, VDDO, VDDC, and VDDP

‡

All typical values are at VDD = 3.3 V, TA = 25°C.

Output voltage during CLK Stop
(STOPB = 0)

Output crossing-point voltage See Figure 1 and Figure 6 1.3 1.8 V
Output voltage swing See Figure 1 0.4 0.6 V
Input clamp voltage VDD = 3.135 V, II = –18 mA –1.2 V

High-level output voltage

Low-level output voltage

High-level output current

Low-level output current

High-impedance-state output
current

High-impedance-state output
current during CLK stop

High-impedance-state output
current in power-down state

REFCLK, PCLKM,

High-level
input current

Low-level
input current

Output
impedance

Reference
current

Input capacitance VI = VDD or GND 2 pF
Output capacitance VO = VDD or GND 3 pF

Supply current in power-down state
Supply current in CLK stop state BUSCLK configured for 533 MHz 45 mA

Supply current in normal state BUSCLK = 533 MHz 100 mA

SYNCLKN, STOPB
PWRDNB, S0, S1,

S2, MULT0, MULT1
REFCLK, PCLKM,

SYNCLKN, STOPB
PWRDNB, S0, S1,

S2, MULT0, MULT1
High state RI at IO –14.5 mA to –16.5 mA 15 35 50
Low state

See Figure 1 1.1 2

See Figure 1 2
VDD = min to max,
VDD = 3.135 V, IOH = –16 mA 2.4
See Figure 1 1
VDD = min to max,
VDD = 3.135 V, IOL = 16 mA 0.5
VDD = 3.135 V, VO = 1 V –32 –52
VDD = 3.3 V,
VDD = 3.465 V, VO = 3.135 V –14.5 –21
VDD = 3.135 V, VO = 1.95 V 43 61.5
VDD = 3.3 V,
VDD = 3.465 V, VO = 0.4 V 25.5 36

S0 = 0, S1 = 1 ±10 µA

Stop = 0, VO = GND or V
PWRDNB = 0,

VO = GND or V
VDD = 3.465 V, VI = V

VDD = 3.465 V, VI = V

VDD = 3.465 V, VI = 0 –10

VDD = 3.465 V, VI = 0 –10

RI at IO 14.5 mA to 16.5 mA 11 17 35

=

DD

REFCLK = 0 MHz to 100 MHz,
PWDNB = 0, STOPB = 1

DD

†

IOH = –1 mA VDD – 0.1 V

IOL = 1 mA 0.1

VO = 1.65 V –51

VO = 1.65 V 65

DD

DD

DD

PWRDNB = 0 50 µA
PWRDNB = 1 0.5 mA

MIN TYP‡MAX UNIT

V

V

mA

mA

±100 µA

–10 100 µA

10

µ

10

µ

100 µA

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CDCFR83

(j

)

Infinite and

(j )

clock cycles

(

)

Infinite and

(,)

duty cycle error

t

Powerdown

Normal3ms

t

VDDNormal3ms

DIRECT RAMBUS CLOCK GENERATOR

SCAS665A – APRIL 2001 REVISED MARCH 2002

switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

t

c(out)

t

itter

t

(phase)

t

(phase, SSC)

t

(DC)

t

DC, err

tr, t

f

∆t

†

All typical values are at VDD = 3.3 V, TA = 25°C.

‡

Assured by design

§

Jitter measurement according to Rambus validation specification

Clock output cycle time

Total cycle jitter over 1, 2,
3, 4, 5, or 6

Phase detector phase error for distributed loop Static phase error
PLL output phase error when tracking SSC Dynamic phase error
Output duty cycle over 10,000 cycles See Figure 4 45% 55%

Output cycle-to-cycle

Output rise and fall times (measured at 20%–80% of
output voltage)

Difference between rise and fall times on a single device
(20%–80%) |tf – tr|

stopped phase
alignment

stopped phase
alignment

267 MHz 80
300 MHz 70
356 MHz
400 MHz 50
533 MHz

267 MHz 80
300 MHz 70
356 MHz
400 MHz 50
533 MHz 50

See Figure 3

§

}

}

See Figure 5

See Figure 7 160 400 ps

See Figure 7 100 ps

1.87 3.75 ns

ps

60

40

–100 100 ps
–100 100 ps

ps

60

state transition latency specifications

PARAMETER FROM TO

Delay time, PWRDNB↑ to CLK/CLKB output

(powerup)

(VDDpowerup)

t

(MULT)

t

(CLKON)

t

(CLKSETL)

t

(CLKOFF)

†

All typical values are at VDD = 3.3 V, TA = 25°C.

settled (excluding t
Delay time, PWRDNB↑ to internal PLL and

clock are on and settled
Delay time, power up to CLK/CLKB output

settled
Delay time, power up to internal PLL and

clock are on and settled
MULT0 and MULT1 change to CLK/CLKB

output resettled (excluding t
STOPB↑ to CLK/CLKB glitch-free clock

edges
STOPB↑ to CLK/CLKB output settled to

within 50 ps of the phase before STOPB was
disabled

STOPB↓ to CLK/CLKB output disabled Normal

(DISTLOCK)

)

(DISTLOCK)

TEST

CONDITIONS

See Figure 8 3

See Figure 8 3

)

Normal Normal See Figure 9 1 ms

CLK Stop Normal See Figure 10 10 ns

CLK Stop Normal See Figure 10 20 cycles

CLK
Stop

See Figure 10 5 ns

MIN TYP†MAX UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

CDCFR83

(1)

(2)

DIRECT RAMBUS CLOCK GENERATOR

SCAS665A – APRIL 2001 REVISED MARCH 2002

state transition latency specifications (continued)

PARAMETER FROM TO

t

(powerdown)

t

(STOP)

t

(ON)

t

(DISTLOCK)

†

All typical values are at VDD = 3.3 V, TA = 25°C.

Delay time, PWRDNB↓ to the device in the
power-down mode

Maximum time in CLKSTOP (STOPB = 0)
before reentering normal mode
(STOPB = 1)

Minimum time in normal mode (STOPB = 1)
before reentering CLKSTOP (STOPB = 0)

Time from when CLK/CLKB output is
settled to when the phase error between
SYNCLKN and PCLKM falls within t

PARAMETER MEASUREMENT INFORMATION

68 Ω, ±5%

68 Ω, ±5%

(phase)

10 pF

TEST

CONDITIONS

Normal Powerdown See Figure 8 1 ms

STOPB Normal See Figure 10 100 µs

Normal CLK stop See Figure 10 100 ms

Unlocked Locked 5 ms

39 Ω, ±5%

39 Ω, ±5%

100 pF

MIN TYP†MAX UNIT

RT = 28 Ω

RT = 28 Ω

10 pF

Figure 1. Test Load and Voltage Definitions (V

CLK

CLKB

t

c(1)

Cycle-to-cycle jitter = | t

– t

c

c

t

c(2)

| over 10000 consecutive cycles

Figure 2. Cycle-to-Cycle Jitter

O(STOP)

, V

, VO, VOH, VOL)

O(X)

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CLK

(3)

(4)

CLKB

DIRECT RAMBUS CLOCK GENERATOR

SCAS665A – APRIL 2001 REVISED MARCH 2002

PARAMETER MEASUREMENT INFORMATION

t

c(3)

t

c(4)

CDCFR83

Cycle-to-cycle jitter = | t

– t

c

| over 10000 consecutive cycles

c

Figure 3. Short Term Cycle-to-Cycle Jitter Over Four Cycles

CLK

CLKB

t

pd(1)

t

c(5)

Duty cycle = (t

pd(1)/tc(5)

)

Figure 4. Output Duty Cycle

CLK

CLKB

t

pd(2)

Duty cycle error = t

pd(2)

– t

pd(3)

t

c(6)

t

c(7)

Figure 5. Duty Cycle Error (Cycle-to-Cycle)

t

pd(3)

CLK

CLKB

Figure 6. Crossing-Point Voltage

80%

20%

t

r

t

Figure 7. Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

V

O(X)+

V

O(X), nom

V

O(X)–

V

OH

V

OL

f

9

CDCFR83

DIRECT RAMBUS CLOCK GENERATOR

SCAS665A – APRIL 2001 REVISED MARCH 2002

PARAMETER MEASUREMENT INFORMATION

PWRDNB

CLK/CLKB

MULT0 and/or

MULT1

CLK/CLKB

STOPB

CLK/CLKB

t

(CLKON)

(see Note A)

t

(power up)

Figure 8. PWRDNB Transition Timings

t

(MULT)

Figure 9. MULT Transition Timings

t

(ON)

t

(CLKSETL)

t

(STOP)

t

(CLKOFF)

(see Note A)

t

(power down)

NOTE A: V

10

= VO ±200 mV

ref

Output clock
not specified

glitches ok

Clock output settled

Clock enabled
and glitch free

within 50 ps of the
phase before disabled

Figure 10. STOPB Transition Timings

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CDCFR83

DIRECT RAMBUS CLOCK GENERATOR

SCAS665A – APRIL 2001 REVISED MARCH 2002

MECHANICAL DATA

DBQ (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

24-PIN SHOWN

0.025 (0,64)

24

1

0.069 (1,75) MAX

0.012 (0,30)

0.008 (0,20)

13

0.157 (3,99)

0.150 (3,81)

12

A

0.010 (0,25)

0.004 (0,10)

0.005 (0,13)

0.244 (6,20)

0.228 (5,80)

Seating Plane

0.004 (0,10)

M

0.008 (0,20) NOM

0°–8°

Gage Plane

0.010 (0,25)

0.035 (0,89)

0.016 (0,40)

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-137

16

0.197

(5,00)

0.188

(4,78)

2420

0.344 0.344

(8,74)

(8,56)

(8,74)

0.3370.337

(8,56)

4073301/C 02/97

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11

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Copyright  2002, Texas Instruments Incorporated