TEXAS INSTRUMENTS CDC2510 Technical data
CDC2510
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS597 – DECEMBER 1997
AGND
V
CC
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
V
CC
G
PW PACKAGE
(TOP VIEW)
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
CLK
AV
CC
V
CC
1Y9
1Y8
GND
GND
1Y7
1Y6
1Y5
V
CC
FBIN
D
Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
D
Distributes One Clock Input to One Bank of
Ten Outputs
D
Single Output Enable Terminal Controls All
Ten Outputs
D
External Feedback (FBIN) Pin Is Used to
Synchronize the Outputs to the Clock Input
D
On-Chip Series Damping Resistors
D
No External RC Network Required
D
Operates at 3.3-V V
D
Packaged in Plastic 24-Pin Thin Shrink
CC
Small-Outline Package
FBOUT
description
The CDC2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to
precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It
is specifically designed for use with synchronous DRAMs. The CDC2510 operates at 3.3-V V
integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of ten outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted
to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output
enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input
is low, the outputs are disabled to the logic-low state.
and provides
CC
Unlike many products containing PLLs, the CDC2510 does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2510 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or
feedback signals. The PLL can be bypassed for test purposes by strapping AV
to ground.
CC
The CDC2510 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
G CLK
X L L L
L HLH
H H H H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OUTPUTS
1Y
(0:9)
FBOUT
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
CDC2510
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS597 – DECEMBER 1997
functional block diagram
11
G
15
3
1Y0
4
1Y1
5
1Y2
8
1Y3
9
1Y4
1Y5
CLK
FBIN
AV
CC
24
13
23
PLL
AVAILABLE OPTIONS
PACKAGE
T
A
0°C to 70°C CDC2510PWR
SMALL OUTLINE
(PW)
16
17
20
21
12
1Y6
1Y7
1Y8
1Y9
FBOUT
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPE
DESCRIPTION
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
Terminal Functions
TERMINAL
NAME NO.
Clock input. CLK provides the clock signal to be distributed by the CDC2510 clock driver. CLK is used
to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must
CLK 24 I
FBIN 13 I
G 11 I
FBOUT 12 O
3, 4, 5, 8, 9
CC
15, 16, 17, 20,
21
23 Power
2, 10, 14, 22 Power Power supply
1Y (0:9)
AV
AGND 1 Ground Analog ground. AGND provides the ground reference for the analog circuitry.
V
CC
GND 6, 7, 18, 19 Ground Ground
have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered
up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the
feedback signal to its reference signal.
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
Output bank enable. G is the output enable for outputs 1Y(0:9). When G is low, outputs 1Y(0:9) are
disabled to a logic-low state. When G is high, all outputs 1Y(0:9) are enabled and switch at the same
frequency as CLK.
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has
and integrated 25-Ω series-damping resistor.
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:9) is enabled via
the G input. These outputs can be disabled to a logic-low state by deasserting the G control input.
O
Each output has an integrated 25-Ω series-damping resistor.
Analog power supply . A VCC provides the power reference for the analog circuitry. In addition, A V
can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed
and CLK is buffered directly to the device outputs.
CDC2510
SCAS597 – DECEMBER 1997
CC
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
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