CDC2510
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS597 – DECEMBER 1997
AGND
V
CC
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
V
CC
G
PW PACKAGE
(TOP VIEW)
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
CLK
AV
CC
V
CC
1Y9
1Y8
GND
GND
1Y7
1Y6
1Y5
V
CC
FBIN
D
Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
D
Distributes One Clock Input to One Bank of
Ten Outputs
D
Single Output Enable Terminal Controls All
Ten Outputs
D
External Feedback (FBIN) Pin Is Used to
Synchronize the Outputs to the Clock Input
D
On-Chip Series Damping Resistors
D
No External RC Network Required
D
Operates at 3.3-V V
D
Packaged in Plastic 24-Pin Thin Shrink
CC
Small-Outline Package
FBOUT
description
The CDC2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to
precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It
is specifically designed for use with synchronous DRAMs. The CDC2510 operates at 3.3-V V
integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of ten outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted
to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output
enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input
is low, the outputs are disabled to the logic-low state.
and provides
CC
Unlike many products containing PLLs, the CDC2510 does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2510 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or
feedback signals. The PLL can be bypassed for test purposes by strapping AV
to ground.
CC
The CDC2510 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
G CLK
X L L L
L HLH
H H H H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OUTPUTS
1Y
(0:9)
FBOUT
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
CDC2510
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS597 – DECEMBER 1997
functional block diagram
11
G
15
3
1Y0
4
1Y1
5
1Y2
8
1Y3
9
1Y4
1Y5
CLK
FBIN
AV
CC
24
13
23
PLL
AVAILABLE OPTIONS
PACKAGE
T
A
0°C to 70°C CDC2510PWR
SMALL OUTLINE
(PW)
16
17
20
21
12
1Y6
1Y7
1Y8
1Y9
FBOUT
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPE
DESCRIPTION
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
Terminal Functions
TERMINAL
NAME NO.
Clock input. CLK provides the clock signal to be distributed by the CDC2510 clock driver. CLK is used
to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must
CLK 24 I
FBIN 13 I
G 11 I
FBOUT 12 O
3, 4, 5, 8, 9
CC
15, 16, 17, 20,
21
23 Power
2, 10, 14, 22 Power Power supply
1Y (0:9)
AV
AGND 1 Ground Analog ground. AGND provides the ground reference for the analog circuitry.
V
CC
GND 6, 7, 18, 19 Ground Ground
have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered
up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the
feedback signal to its reference signal.
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
Output bank enable. G is the output enable for outputs 1Y(0:9). When G is low, outputs 1Y(0:9) are
disabled to a logic-low state. When G is high, all outputs 1Y(0:9) are enabled and switch at the same
frequency as CLK.
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has
and integrated 25-Ω series-damping resistor.
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:9) is enabled via
the G input. These outputs can be disabled to a logic-low state by deasserting the G control input.
O
Each output has an integrated 25-Ω series-damping resistor.
Analog power supply . A VCC provides the power reference for the analog circuitry. In addition, A V
can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed
and CLK is buffered directly to the device outputs.
CDC2510
SCAS597 – DECEMBER 1997
CC
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
CDC2510
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS597 – DECEMBER 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, VI (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high
or low state, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 3) 0.7 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the
Book
, literature number SCBD002.
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
OK
< 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(V
= 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
O
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
Package Thermal Considerations
application note in the
ABT Advanced BiCMOS T echnology Data
recommended operating conditions (see Note 4)
MIN MAX UNIT
V
V
V
V
I
OH
I
OL
T
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
Supply voltage 3 3.6 V
CC
High-level input voltage 2 V
IH
Low-level input voltage 0.8 V
IL
Input voltage 0 V
I
High-level output current –12 mA
Low-level output current 12 mA
Operating free-air temperature 0 70 °C
A
CC
V
†
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS V
V
IK
V
OH
V
OL
I
I
§
I
CC
∆I
CC
C
i
C
‡
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§
For ICC of AVCC, see Figure 5.
o
II = –18 mA 3 V –1.2 V
IOH = –100 µA MIN to MAX VCC–0.2
IOH = –12 mA 3 V 2.1
IOH = –6 mA 3 V 2.4
IOL = 100 µA MIN to MAX 0.2
IOL = 12 mA 3 V 0.8
IOL = 6 mA 3 V 0.55
VI = VCC or GND 3.6 V ±5 µA
VI = VCC or GND, IO = 0, Outputs: low or high 3.6 V 10 µA
One input at VCC – 0.6 V, Other inputs at VCC or GND 3.3 V to 3.6 V 500 µA
VI = VCC or GND 3.3 V 4 pF
VO = VCC or GND 3.3 V 6 pF
CC
MIN TYP‡MAX UNIT
V
V
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
(INPUT)
(OUTPUT)
CDC2510
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS597 – DECEMBER 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN MAX UNIT
f
clock
†
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency , fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew ,
and jitter parameters given in the switching characteristics table are not applicable.
Clock frequency 25 125 MHz
Input clock duty cycle 40% 60%
Stabilization time
†
1 ms
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
t
phase error
reference
(see Figure 3)
t
phase error
– jitter
(see Note 6)
t
sk(o)
Jitter
Duty cycle
reference
(see Figure 4)
t
r
t
f
‡
These parameters are not production tested.
§
The t
NOTES: 5. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
,
§
(pk-pk)
specification is only valid for equal loading of all outputs.
sk(o)
6. Phase error does not include jitter. The total phase error is –600 ps to 50 ps for the 5% VCC range.
= 30 pF (see Note 5 and Figures 1 and 2)
L
FROM
66 MHz < CLKIN↑ < 100 MHz FBIN↑ –0.7...0.1 ns
CLKIN↑ = 100 MHz FBIN↑ –500 –50 –310 ps
Any Y or FBOUT Any Y or FBOUT 200 ps
F(clkin > 66 MHz) Any Y or FBOUT –100 100 ps
TO
Any Y or FBOUT 43% 55%
Any Y or FBOUT 1.3 1.9 0.8 2.1 ns
Any Y or FBOUT 1.7 2.3 1.2 2.5 ns
‡
VCC = 3.3 V
± 0.165 V
MIN TYP MAX MIN TYP MAX
VCC = 3.3 V
± 0.3 V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
CDC2510
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS597 – DECEMBER 1997
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
500
30 pF
W
Input
Output
3 V
50% V
CC
t
pd
t
r
0.4 V
2 V
50% V
CC
2 V
t
f
0.4 V
0 V
V
V
OH
OL
LOAD CIRCUIT FOR OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, ZO = 50 Ω, tr ≤ 1.2 ns, tf≤ 1.2 ns.
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
CLKIN
FBIN
t
phase error
FBOUT
Any Y
t
sk(o)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Any Y
Any Y
t
sk(o)
Figure 2. Phase Error and Skew Calculations
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2510
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS597 – DECEMBER 1997
TYPICAL CHARACTERISTICS
0
–0.1
–0.2
–0.3
–0.4
–0.5
Phase Error – ns
–0.6
–0.7
–0.8
–0.9
VDD = 3.3 V
TA = 25°C
35
25
PHASE ERROR
vs
CLOCK FREQUENCY
45 55 65 95 105
f
– Clock Frequency – MHz
clk
75 115 125
85
Figure 3
9
VDD = 3.3 V
8
TA = 25°C
57%
VDD = 3.3 V
55%
53%
51%
49%
Output Duty Cycle
47%
45%
43%
CL = 30 pF
40 50 60 70 100 110
ANALOG SUPPLY CURRENT
vs
CLOCK FREQUENCY
OUTPUT DUTY CYCLE
vs
CLOCK FREQUENCY
9080 120 13030
f
– Clock Frequency – MHz
clk
Figure 4
7
6
5
4
3
2
Analog Supply Current – mA
1
0
35
25
45 55 65 95 105
f
– Clock Frequency – MHz
clk
Figure 5
85
75 115 125
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
CDC2510
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS597 – DECEMBER 1997
MECHANICAL INFORMATION
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,65
14
1
1,20 MAX
A
7
0,05 MIN
0,30
0,19
8
6,60
4,50
4,30
6,20
M
0,10
Seating Plane
0,10
0,15 NOM
Gage Plane
0,25
0°–8°
0,75
0,50
PINS **
DIM
A MAX
A MIN
NOTES: D. All linear dimensions are in millimeters.
E. This drawing is subject to change without notice.
F. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
G. Falls within JEDEC MO-153
8
3,10
2,90
14
5,10
4,90
16
5,10
20
6,60
6,404,90
24
7,90
7,70
28
9,80
9,60
4040064/E 08/96
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 1998, Texas Instruments Incorporated
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