Texas Instruments CD74HCT85M, CD74HCT85E, CD74HC85PWR, CD74HC85M96, CD74HC85M Datasheet

CD74HC85,

/
j

[ /Title
(CD74
HC85,
CD74
HCT85
)

Sub-

ect
(High
Speed
CMOS
Logic
4-Bit
Magni­tude
Com­para-

Data sheet acquired from Harris Semiconductor
SCHS136

August 1997

Features

• Buffered Inputs and Outputs

• Typical Propagation Delay: 13ns (Data to Output at
V

= 5V, CL = 15pF, TA = 25oC

CC

• Serial or Parallel Expansion Without External Gating

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High NoiseImmunity: N

V

= 5V

CC

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH= 30%of VCCat

IL

≤ 1µA at VOL, V

l

o

C to 125oC

OH

CD74HCT85

High Speed CMOS Logic

4-Bit Magnitude Comparator

Description

The CD74HC85 and CD74HCT85 are high speed
magnitude comparators that use silicon-gate CMOS
technology to achieve operating speeds similar to LSTTL
with the low power consumption of standard CMOS
integrated circuits.

These 4-bit devices compare two binary, BCD, or other
monotonic codes and present the three possible magnitude
results at the outputs (A > B, A < B, and A = B). The 4-bit
input words are weighted (A0 to A3 and B0 to B3), where A3
and B

are the most significant bits.

3

The devices are expandable without external gating, in both
serial and parallel fashion. The upper part of the truth table
indicates operation using a single device or devices in a
serially expanded application. The parallel expansion
scheme is described by the last three entries in the truth
table.

Ordering Information

PKG.

PART NUMBER TEMP. RANGE (oC) PACKAGE

CD74HC85E -55 to 125 16 Ld PDIP E16.3
CD74HCT85E -55 to 125 16 Ld PDIP E16.3
CD74HC85M -55 to 125 16 Ld SOIC M16.15

NO.

Pinout

CD74HC85, CD74HCT85

B3
(A < B) IN
(A = B) IN
(A > B) IN

(A > B) OUT
(A = B) OUT
(A < B) OUT

GND

(PDIP, SOIC)

TOP VIEW

1
2
3
4
5
6
7
8

CD74HCT85M -55 to 125 16 Ld SOIC M16.15

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Die for this part number is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.

16

V

CC

15

A3

14

B2

13

A2

12

A1
B1

11
10

A0

9

B0

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

1

File Number 1770.1

CD74HC85, CD74HCT85

Functional Diagram

15

A3

13

A2

12

A1

10

A0

7

(A < B) OUT

6

(A = B) OUT

5

(A > B) OUT

B3
B2
B1
B0

2
3
4

1
14
11

9

(A < B) IN
(A = B) IN
(A > B) IN

TRUTH TABLE

COMPARING INPUTS CASCADING INPUTS OUTPUTS

A3, B3 A2, B2 A1, B1 A0, B0 A > B A < B A = B A > B A < B A = B

SINGLE DEVICE OR SERIES CASCADING

A3 > B3 X X X X X X H L L
A3 < B3 X X X X X X L H L
A3 = B3 A2 >B2 X X X X X H L L
A3 = B3 A2 < B2 X X X X X L H L
A3 = B3 A2 = B2 A1 > B1 X X X X H L L
A3 = B3 A2 = B2 A1 < B1 X X X X L H L
A3 = B3 A2 = B2 A1 = B1 A0 > B0 X X X H L L
A3 = B3 A2 = B2 A1 = B1 A0 < B0 X X X L H L
A3 = B3 A2 = B2 A1 = B1 A0 = B0 H L L H L L
A3 = B3 A2 = B2 A1 = B1 A0 = B0 L H L L H L
A3 = B3 A2 = B2 A1 = B1 A0 = B0 L L H L L H

PARALLEL CASCADING

A3 = B3 A2 = B2 A1 = B1 A0 = B0 X X H L L H
A3 = B3A2 = B2A1 = B1A0 = B0HHLLLL
A3 = B3 A2 = B2S A1 = B1 A0 = B0 L L L H H L

NOTE: H = High Voltage Level, L = Low Voltage, Level, X = Don’t Care

2

CD74HC85, CD74HCT85

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

TEST

CONDITIONS

V

CC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

VCC or

0 6 - - 8 - 80 - 160 µA

GND

3

CD74HC85, CD74HCT85

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note)

NOTE: For dual-supply systems theorectical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

∆I

CC

- - 4.5 to

- - 4.5 to

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

4 4.5 - - 0.26 - 0.33 - 0.4 V

VCCand

GND

VCC or

GND

V

CC

-2.1

0 5.5 - ±0.1 - ±1-±1 µA

0 5.5 - - 8 - 80 - 160 µA

- 4.5 to

V

CC

(V)

5.5

5.5

5.5

25oC -40oC TO 85oC -55oC TO 125oC

2--2- 2 - V

- - 0.8 - 0.8 - 0.8 V

- 100 360 - 450 - 490 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

A0-A3, B0-B3 and (A = B) IN 1.5

(A > B) IN, (A < B) IN 1

NOTE: Unit Load is ∆I
360µA max at 25oC.

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay,
An, Bn to (A > B) OUT,
(A < B) OUT

An, Bn to (A = B) OUT t

limit specified in DC Electrical Table, e.g.

CC

, tf = 6ns

r

t

PLH,tPHLCL

PLH,tPHLCL

-40oC TO

TEST

CONDITIONS VCC(V)

= 50pF 2 - - 195 - 245 - 295 ns

4.5 - - 39 - 47 - 59 ns
CL= 15pF 5 - 16 - - - - - ns
CL= 50pF 6 - - 33 - 42 - 50 ns

= 50pF 2 - - 175 - 240 - 265 ns

4.5 - - 35 - 44 - 53 ns
CL= 15pF 5 - 14 - - - - - ns
CL= 50pF 6 - - 30 - 37 - 45 ns

25oC

85oC

-55oC TO
125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

4

CD74HC85, CD74HCT85

Switching Specifications Input t

, tf = 6ns (Continued)

r

TEST

PARAMETER SYMBOL

(A > B) IN, (A < B) IN, (A = B) IN
to (A > B) OUT, (A < B) OUT

t

PLH,tPHLCL

CONDITIONS VCC(V)

= 50pF 2 - - 140 - 175 - 210 ns

4.5 - - 28 - 35 - 42 ns
CL= 15pF 5 - 11 - - - - - ns
CL= 50pF 6 - - 24 - 30 - 36 ns

(A > B) IN to (A = B) OUT t

PLH,tPHLCL

= 50pF 2 - - 120 - 150 - 180 ns

4.5 - - 24 - 30 - 36 ns
CL= 15pF 5 - 9 - - - - - ns
CL= 50pF 6 - - 20 - 26 - 31 ns

Power Dissipation Capacitance

C

-5-24-----pF

PD

(Notes 2, 3)
Output Transition Times

(Figure 1)

t

TLH

, t

THLCL

= 50pF 2 - - 75 - 95 - 110 ns

4.5 - - 15 - 19 - 22 ns

6 - - 13 - 16 - 19 ns

Input Capacitance C

- - - - 10 - 10 - 10 pF

IN

HCT TYPES

Propagation Delay,
An, Bn to (A > B) OUT,
(A < B) OUT

An, Bn to (A = B) OUT t

t

PLH,tPHLCL

PLH,tPHLCL

= 50pF 4.5 - - 37 - 46 - 56 ns

CL= 15pF 5 - 15 - - - - - ns

= 50pF 4.5 - - 40 - 50 - 60 ns

CL= 15pF 5 - 17 - - - - - ns

(A > B) IN, (A < B) IN, (A = B) IN
to (A > B) OUT, (A < B) OUT

(A > B) IN to (A = B) OUT t

t

PLH,tPHLCL

PLH,tPHLCL

= 50pF 4.5 - - 30 - 38 - 45 ns

CL= 15pF 5 - 12 - - - - - ns

= 50pF 4.5 - - 31 - 39 - 47 ns

CL= 15pF 5 - 13 - - - - - ns

Output Transition Times

t

TLH

, t

THLCL

= 50pF 4.5 - - 15 - 19 - 22 ns

(Figure 1)
Power Dissipation Capacitance

C

-5-26-----pF

PD

(Notes 4, 5)
Input Capacitance C

IN

- - - - 10 - 10 - 10 pF

NOTES:

4. CPD is used to determine the dynamic power consumption, per gate/package.

5. PD = V

2

fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CC

25oC

-40oC TO
85oC

-55oC TO
125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Test Circuits and Waveforms

tr = 6ns tf = 6ns

V

t

CC

GND

TLH

t

PHL

90%
50%
10%

t

90%

50%

10%

PLH

INPUT

t

INVERTING

OUTPUT

THL

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

= 6ns

t

PLH

t

f

1.3V

10%

90%

t

TLH

tr = 6ns

INPUT

t

INVERTING

OUTPUT

THL

t

2.7V

1.3V

0.3V

PHL

FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

5

3V

GND

Test Circuits and Waveforms

CD74HC85, CD74HCT85

LEAST SIGNIFICANT

4-BITS OF EACH WORD

MOST SIGNIFICANT

4-BITS OF EACH WORD

FIGURE 3. SERIES CASCADING - COMPARING 12-BIT WORDS

GND

V

CC

GND

A0
A1
A2
A3
B0
B1
B2
B3

A4
A5
A6
A7
B4
B5
B6
B7

A0
A1
A2
A3
B0
B1
B2
B3

(A > B) IN
(A = B) IN
(A < B) IN

A0
A1

CD74HC85

A2

CD74HCT85

A3
B0
B1
B2
B3

(A > B) IN
(A = B) IN
(A < B) IN

A4
A5

CD74HC85

A6

CD74HCT85

A7
B4

(A > B) OUT

B5

(A = B) OUT

B6

(A < B) OUT

B7

(A > B) IN
(A = B) IN
(A < B) IN

A0
A1

CD74HC85

A2

CD74HCT85
A3
B0

(A > B) OUT

B1

(A = B) OUT

B2

(A < B) OUT

B3

OUTPUTS

6

Test Circuits and Waveforms

GND

B1
A1
B0
A0

VCC
GND

CD74HC85

B3

CD74HCT85

A3
B2
A2

(A < B) OUT

B1

(A = B) OUT

A1

(A > B) OUT

B0
A0
(A < B) IN
(A = B) IN
(A > B) IN

CD74HC85

B3

CD74HCT85

A3

B2
A2

(A < B) OUT

B1

(A = B) OUT

A1

(A > B) OUT

B0
A0
(A < B) IN
(A = B) IN
(A > B) IN

NC

OUTPUTS

B6
A6
B5
A5
B4
A4
B3
A3
B2

GND

A2

CD74HC85

B3

CD74HCT85

A3

B2

(A < B) OUT

A2

(A = B) OUT

B1
A1

(A > B) OUT
B0
A0

(A < B) IN
(A = B) IN
(A > B) IN

B11
A11
B10
A10

B9
A9
B8
A8
B7

GND

A7

NC

FIGURE 4. PARALLEL CASCADING - COMPARING 12-BIT WORDS

CD74HC85

B3

CD74HCT85

A3
B2
A2

(A > B) OUT

B1

(A = B) OUT

A1

(A < B) OUT

B0
A0
(A < B) IN
(A = B) IN
(A > B) IN

OUTPUTS

7

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