Texas Instruments CD74HCT75E, CD74HC75E, CD74HC75PWR, CD74HC75M96, CD74HC75M Datasheet

CD74HC75,

/
j

[ /Title
(CD74
HC75,
CD74
HCT75
)

Sub-

ect
(Dual
2-Bit
Bistabl
e

Data sheet acquired from Harris Semiconductor
SCHS135

March 1998

Features

• True and Complementary Outputs

• Buffered Inputs and Outputs

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, NIH = 30% of V

IL

o

Pinout

C to 125oC

CC

CD74HCT75

Dual 2-Bit Bistable

Transparent Latch

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,
V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

Description

The Harris CD74HC75 and CD74HCT75 are dual 2-bit
bistable transparent latches. Each one of the 2-bit latches is
controlled by separate Enable inputs (
active LOW. When the Enable input is HIGH data enters the
latch and appears at the Q output. When the Enable input
(

1E and 2E) is LOW the output is not affected.

Ordering Information

≤ 1µA at VOL, V

l

1E and 2E) which are

OH

CD74HC75, CD74HCT75

(PDIP, SOIC)

TOP VIEW

1

1Q0

2

1D0

3

1D1

4

2E

5

V

CC

6

2D0
2D1

7
8

2Q1

1Q0

16
15

1Q1

14

1Q1

13

1E

12

GND

11

2Q0

10

2Q0

9

2Q1

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

1

File Number 1666.1

CD74HC75, CD74HCT75

Functional Diagram

16 (10)

2 (6)

D0

3 (7)

D1

E

1 OF 2

LATCHES

13 (4)

TRUTH TABLE

INPUTS OUTPUTS

D EQQ

LHLH
HHHL
XLQ0Q0

NOTE:
H = High Level
L = Low Level
X = Don’t Care
Q0 = The level of Q before the transition of E.

1 (11)
14 (8)
15 (9)

Q0

Q0
Q1
Q1

D0

E

D1

2 (6)

13 (4)

3 (7)

5

12

V

CC

GND

LATCH 0

QD

LE LE

LE LE

QD

LATCH 1

16 (10)

1 (11)

14 (8)

15 (9)

Q0

Q0

Q1

Q1

LE

Q

P
N

LE Q

FIGURE 1. LOGIC DIAGRAM FIGURE 2. LATCH DETAIL

LE

P
N

LE

2

CD74HC75, CD74HCT75

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Maximum Junction Temperature (Hermetic P ac kage or Die) . . . 175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

VCC (V)

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

4.5 4.4 - - 4.4 - 4.4 - V
6 5.9 - - 5.9 - 5.9 - V

---------V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

4.5 - - 0.1 - 0.1 - 0.1 V
6 - - 0.1 - 0.1 - 0.1 V

---------V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

3

CD74HC75, CD74HCT75

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device
Current

I

CC

VCC or

GND

VCC (V)

0 6 - - 4 - 40 - 80 µA

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

- - 4.5 to

5.5

V

IL

- - 4.5 to

5.5

V

OH

VIH or

V

IL

- 4.5 4.4 - - 4.4 - 4.4 - V

CMOS Loads
High Level Output

-0.02 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads

Low Level Output
Voltage CMOS Loads

Low Level Output

V

OL

VIH or

V

IL

-4 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads

Input Leakage
Current

I

I

V

CC

4 5.5 - ±0.1 - ±1-±1 µA

and

GND

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

CC

∆I

CC

(Note 4)

VCC or

GND

V

CC

- 2.1

0 5.5 - - 4 - 40 - 80 µA

- 4.5 to

5.5

Input Pin: 1 Unit Load

NOTE:

4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

25oC -40oC TO 85oC -55oC TO 125oC

2-- 2 - 2 - V

- - 0.8 - 0.8 - 0.8 V

- 100 360 - 450 - 490 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

D0, D1 0.8
1E, 2E 1.2

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Specifica­tions table, e.g., 360µA max at 25oC.

Prerequisite For Switching Specifications

TEST

PARAMETER SYMBOL

HC TYPES

Pulse Width Enable Input t

Setup Time D to Enable t

SU

W

CONDITIONS

- 2 80 - - 100 - 120 - ns

- 2 60 - - 75 - 90 - ns

V

CC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns

4.5 12 - - 15 - 18 - ns
6 10 - - 13 - 15 - ns

4

CD74HC75, CD74HCT75

Prerequisite For Switching Specifications (Continued)

PARAMETER SYMBOL

Hold Time Enable to D t

HCT TYPES

Pulse Width Enable Input t
Setup Time D to Enable t
Hold Time Enable to D t

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay,
Data to Q

Propagation Delay,
Data to Q

Propagation Delay,
Enable to Q

Propagation Delay,
Enable to Q

Output Transition Time t

Input Capacitance C
Power Dissipation Capacitance

(Notes 5, 6)

HCT TYPES

Propagation Delay,
Data to Q

Propagation Delay,
Data to Q

Propagation Delay,
Enable to Q

t

PLH

t

PLH

t

PLH

t

PLH

TLH

t

PLH

t

PLH

t

PLH

H

W

SU

H

, tf = 6ns

r

, t

PHLCL

, t

PHLCL

, t

PHLCL

, t

PHLCL

, t

THLCL

I

C

PD

, t

PHLCL

, t

PHLCL

, t

PHLCL

TEST

CONDITIONS

V

CC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

-23--3-3-ns

4.5 3 - - 3 - 3 - ns
63--3-3-ns

- 4.5 16 - - 20 - 24 - ns

- 4.5 12 - - 15 - 18 - ns

- 4.5 3 - - 3 - 3 - ns

TEST

CONDITIONS

V

CC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

= 50pF 2 - - 110 - 140 - 165 ns
CL= 50pF 4.5 - - 22 - 28 - 33 ns
CL= 15pF 5 - 9 - ----ns
CL= 50pF 6 - - 19 - 24 - 28 ns

= 50pF 2 - - 130 - 165 - 195 ns
CL= 50pF 4.5 - - 26 - 33 - 39 ns
CL= 15pF 5 - 10 - ----ns
CL= 50pF 6 - - 22 - 28 - 33 ns

= 50pF 2 - - 130 - 165 - 195 ns
CL= 50pF 4.5 - - 26 - 33 - 39 ns
CL= 15pF 5 - 10 - ----ns
CL= 50pF 6 - - 22 - 28 - 33 ns

= 50pF 2 - - 130 - 165 - 195 ns
CL= 50pF 4.5 - - 26 - 33 - 39 ns
CL= 15pF 5 - 11 - ----ns
CL= 50pF 6 - - 22 - 28 - 33 ns

= 50pF 2 - - 75 - 95 - 110 ns
CL= 50pF 4.5 - - 15 - 19 - 22 ns
CL= 50pF 6 - - 13 - 16 - 19 ns

- - - - 10 - 10 - 10 pF

- 5-46-----pF

= 50pF 4.5 - - 28 - 35 - 42 ns
CL= 15pF 5 - 11 - ----ns

= 50pF 4.5 - - 28 - 35 - 42 ns
CL= 15pF 5 - 11 - ----ns

= 50pF 4.5 - - 28 - 35 - 42 ns
CL= 15pF 5 11 - ----ns

5

CD74HC75, CD74HCT75

Switching Specifications Input t

PARAMETER SYMBOL

Propagation Delay,
Enable to Q

Output Transition Time t
Input Capacitance C
Power Dissipation Capacitance

, tf = 6ns (Continued)

r

CONDITIONS

t

, t

PLH

PHLCL

CL= 15pF 5 - 12 - ----ns

, t

TLH

THLCL

I

C

PD

TEST

V

CC

(V)

= 50pF 4.5 - - 30 - 38 - 45 ns

= 50pF 4.5 - - 15 - 19 - 22 ns

- - - - 10 - 10 - 10 pF

- 5-46-----pF

(Notes 5, 6)

NOTES:

5. CPD is used to determine the dynamic power consumption, per latch.

6. PD = V

2

fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

CC

Test Circuits and Waveforms

trC

L

CLOCK

10%

90%

50%

10%

tfC

t

WL

L

tWL+ tWH=

50%

t

WH

f

CL

50%

I

V

CC

GND

25oC -40oC TO 85oC -55oC TO 125oC

trCL= 6ns

CLOCK

2.7V

0.3V

1.3V

0.3V

t

t

fCL

WL

= 6ns

1.3V

t

WH

t

WL

+ tWH=

1.3V

UNITSMIN TYP MAX MIN MAX MIN MAX

I

fC

L

3V

GND

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For f

, input duty cycle = 50%.

MAX

FIGURE 3. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

tr = 6ns tf = 6ns

V

t

CC

GND

TLH

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

90%
50%
10%

t

90%

50%

10%

PLH

FIGURE 5. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For f

, input duty cycle = 50%.

MAX

FIGURE 4. HCT CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

= 6ns

t

PLH

t

f

10%

90%

1.3V

t

3V

GND

TLH

tr = 6ns

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

2.7V

1.3V

0.3V

FIGURE 6. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

6

CD74HC75, CD74HCT75

Test Circuits and Waveforms

90%

t

PLH

IC

t

TLH

tfC

L

50%

C
50pF

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

OUTPUT

t

REM

V

CC

SET, RESET
OR PRESET

trC

L

90%

10%

t

H(H)

50%

(Continued)

t

H(L)

t

SU(L)

t

THL

90%

50%

10%
t

PHL

L

V

CC

GND

V

CC

50%
GND

GND

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

OUTPUT

t

REM

3V
SET, RESET
OR PRESET

trC

90%

t

PLH

IC

1.3V

t

TLH

tfC

L

1.3V

t

H(L)

1.3V

t

SU(L)

t

THL

90%

1.3V
10%

t

PHL

C

L

50pF

3V

GND

3V

GND

GND

L

2.7V

0.3V

t

H(H)

1.3V

1.3V

1.3V

FIGURE 7. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

FIGURE 8. HCT SETUP TIMES, HOLD TIMES, REMOVALTIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

7

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