Texas Instruments CD74HCT74M96, CD74HCT74M, CD74HCT74E, CD74HC74M96, CD74HC74M Datasheet

Data sheet acquired from Harris Semiconductor

/

SCHS124

January 1998

CD54HC74, CD74HC74,

CD74HCT74

Dual D Flip-Flop with Set and Reset

Positive-Edge Trigger

[ /Title
(CD54H
C74,
CD74H
C74,
CD74H
CT74)

Subject
(Dual D
Flip­Flop
with Set

Features

• Hysteresis on Clock Inputs for Improved Noise Immu­nity and Increased Input Rise and Fall Times

• Asynchronous Set and Reset

• Complementary Outputs

• Buffered Inputs

• Typical f
T

= 25oC

A

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 50MHz at VCC = 5V, CL = 15pF,

MAX

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

o

C to 125oC

OH

CC

Description

The Harris CD54HC74, CD74HC74 and CD74HCT74 utilize
silicon gate CMOS technology to achieve operating speeds
equivalent to LSTTL parts. They exhibit the low power
consumption of standard CMOS integrated circuits, together
with the ability to drive 10 LSTTL loads.

This flip-flop has independent DATA,
CLOCK inputs and Q and

Q outputs. The logic level present

SET, RESET and

at the data input is transferred to the output during the
positive-going transition of the clock pulse.

SET and RESET
are independent of the clock and are accomplished by a low
level at the appropriate input.

The 74HCT logic family is functionally as well as pin
compatible with the standard 74LS logic family.

Ordering Information

TEMP. RANGE

PART NUMBER

CD54HC74F -55 to 125 14 Ld CERDIP F14.3
CD74HC74E -55 to 125 14 Ld PDIP E14.3
CD74HCT74E -55 to 125 14 Ld PDIP E14.3
CD74HC74M -55 to 125 14 Ld SOIC M14.15
CD74HCT74M -55 to 125 14 Ld SOIC M14.15

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Die is available which meets all electrical specifications. Please
contact your local sales office or Harris customer service for
ordering information.

(oC) PACKAGE

PKG.

NO.

Pinout

CD54HC74, CD74HC74, CD74HCT74

(PDIP, SOIC, CERDIP)

TOP VIEW

1R

1
2

1D

1CP

3

1

S

4

1Q

5

1

Q

6
7

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

14

V

CC

2R

13

2D

12

2CP

11

2

S

10

9

2Q

Q

8

2

1

File Number 1476.1

CD54HC74, CD74HC74, CD74HCT74

Functional Diagram

RESET

CLOCK

RESET

CLOCK

INPUTS OUTPUTS

SET RESET CP D Q Q

LHXXHL

H

L
H
H

L
L
H
H

HHLXQ0Q0

NOTE:
H = High Level (Steady State)
L = Low Level (Steady State)
X = Don’t Care

↑ = Low-to-High Transition

Q0 = the level of Q before the indicated input conditions were established.

3. This configuration is nonstable, that is, it will not persist when set and reset inputs return to their inactive (high) level.

1

R

D

F/F 1

CP

S

R

D

F/F 2

CP

S

5

Q

6

Q

9

Q

8

Q

GND = PIN 7
V

= PIN 14

CC

DAT A

SET

DAT A

SET

2

3

4

13

12

11

10

TRUTH TABLE

XXLH
X X H (Note 3) H (Note 3)

↑ HHL
↑LLH

2

CD54HC74, CD74HC74, CD74HCT74

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

4. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 4) θJA (oC/W) θJC (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . 90 -

SOIC Package. . . . . . . . . . . . . . . . . . . 120 -

CERDIP Package . . . . . . . . . . . . . . . . 130 55

Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

VCC (V)

o

25

C -40oC TO 85oC -55oC TO 125oC

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

4.5 4.4 - - 4.4 - 4.4 - V
6 5.9 - - 5.9 - 5.9 - V

---------V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

4.5 - - 0.1 - 0.1 - 0.1 V
6 - - 0.1 - 0.1 - 0.1 V

---------V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1µA

GND

UNITSV

3

CD54HC74, CD74HC74, CD74HCT74

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device
Current

I

CC

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

VCC or

GND

HCT TYPES

High Level Input

V

IH

- - 4.5 to

Voltage
Low Level Input

V

IL

- - 4.5 to

Voltage
High Level Output

Voltage

V

OH

VIH or

V

IL

CMOS Loads
High Level Output

-0.02 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads

Low Level Output
Voltage CMOS Loads

V

OL

VIH or

V

IL

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

I

I

V

CC

and

GND

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

CC

∆I

CC

(Note 5)

VCC or

GND

V

CC

- 2.1

Input Pin: 1 Unit Load

NOTE:

5. For dual-supply systems theoretical worst case (V

o

25

C -40oC TO 85oC -55oC TO 125oC

V

CC

(V)

UNITSV

0 6 - - 4 - 40 - 80 µA

2-- 2 - 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

- 4.5 4.4 - - 4.4 - 4.4 - V

-4 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.26 - 0.33 - 0.4 V

4 5.5 - ±0.1 - ±1-±1µA

0 5.5 - - 4 - 40 - 80 µA

- 4.5 to

- 100 360 - 450 - 490 µA

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

HCT Input Loading Table

INPUT UNIT LOADS

D 0.5
R 0.5

CP 0.7

S 0.75

NOTE: Unit Load is ∆I

limit specified in DC Electrical Specifica-

CC

tions table, e.g., 360µA max at 25oC.

Prerequisite For Switching Specifications

TEST

PARAMETER SYMBOL

HC TYPES

Data to CP Setup Time
(Figure 5)

t

SU

CONDITIONS

o

25

V

CC

(V)

C -40oC TO 85oC -55oCTO125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

- 2 60 - - 75 - 90 - ns

4.5 12 - - 15 - 18 - ns
6 10 - - 13 - 15 - ns

4

CD54HC74, CD74HC74, CD74HCT74

Prerequisite For Switching Specifications (Continued)

PARAMETER SYMBOL

Hold Time (Figure 5) t

Removal Time

R, S, to CP

t

(Figure 5)

Pulse Width

R, S (Figure 1) t

Pulse Width CP (Figure 1) t

CP Frequency f

HCT TYPES

Data to CP Setup Time
(Figure 6)

Hold Time (Figure 6) t
Removal Time

R, S, to CP

t

(Figure 6)
Pulse Width

R, S (Figure 2) t
Pulse Width CP (Figure 2) t
CP Frequency f

H

REM

W

W

MAX

t

SU

H

REM

W
W

MAX

TEST

CONDITIONS

-23--3-3-ns

- 2 30 - - 40 - 45 - ns

- 2 80 - - 100 - 120 - ns

- 2 80 - - 100 - 120 - ns

- 2 6 - - 5 - 4 - MHz

- 4.5 12 - - 15 - 18 - ns

- 4.5 3 - - 3 - 3 - ns

- 4.5 6 - - 8 - 9 - ns

- 4.5 16 - - 20 - 24 - ns

- 4.5 18 - - 23 - 27 - ns

- 4.5 25 - - 20 - 16 - MHz

V

CC

(V)

4.5 3 - - 3 - 3 - ns
63--3-3-ns

4.5 6 - - 8 - 9 - ns
65--7-8-ns

4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns

4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns

4.5 30 - - 25 - 20 - MHz
6 35 - - 29 - 23 - MHz

o

25

C -40oC TO 85oC -55oCTO125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay,
CP to Q,

Q (Figure 3)

Propagation Delay,
R, S to Q, Q (Figure 3)

Transition Time (Figure 3) t

Input Capacitance C

t

PLH

t

PLH

TLH

, tf = 6ns

r

, t

PHLCL

, t

PHLCL

, t

THLCL

I

o

C -40oC TO 85oC -55oCTO125oC

TEST

CONDITIONS

V

CC

(V)

25

UNITSMIN TYP MAX MIN MAX MIN MAX

= 50pF 2 - - 175 - 220 - 265 ns
= 50pF 4.5 - - 35 - 44 - 53 ns

C

L

= 15pF 5 - 14 - ----ns

C

L

= 50pF 6 - - 30 - 37 - 45 ns

C

L

= 50pF 2 - - 200 - 250 - 300 ns
= 50pF 4.5 - - 40 - 50 - 60 ns

C

L

C

= 15pF 5 - 17 - ----ns

L

= 50pF 6 - - 34 - 43 - 51 ns

C

L

= 50pF 2 - - 75 - 95 - 110 ns
= 50pF 4.5 - - 15 - 19 - 22 ns

C

L

= 50pF 6 - - 13 - 16 - 19 ns

C

L

- - - - 10 - 10 - 10 pF

5

CD54HC74, CD74HC74, CD74HCT74

Switching Specifications Input t

, tf = 6ns (Continued)

r

PARAMETER SYMBOL

CP Frequency f
Power Dissipation Capacitance

MAX

C

PD

(Notes 6, 7)

HCT TYPES

t

Propagation Delay,
CP to Q,

Q (Figure 4)

Propagation Delay,

PLH

t

PHL

, t

PHLCL

, t

PLH

R, S to Q, Q (Figure 4)
Transition Time (Figure 4) t
Input Capacitance C
CP Frequency f
Power Dissipation Capacitance

TLH

, t

MAX

C

PD

I

THLCL

(Notes 6, 7)

NOTES:

6. C

is used to determine the dynamic power consumption, per flip-flop.

PD

7. PD=CPDV

2

fi+ Σ (CLV

CC

2

fo) where fi= input frequency, fo= output frequency, CL= output load capacitance, VCC= supply voltage.

CC

Test Circuits and Waveforms

trC

L

CLOCK

10%

90%

50%

10%

tfC

t

L

WL

tWL+ tWH=

50%

t

o

25

TEST

CONDITIONS

V

CC

(V)

C -40oC TO 85oC -55oCTO125oC

CL = 15pF 5 - 50 - ----MHz

- 5-25-----pF

= 50pF 4.5 - - 35 - 44 - 53 ns

CL = 50pF 4.5 - - 40 - 50 - 60 ns

= 50pF 4.5 - - 15 - 19 - 22 ns

- - - - 10 - 10 - 10 pF

CL = 15pF 5 - 50 - ----MHz

- 5-30-----pF

+ tWH=

t

WH

f

CL

50%

I

V

CC

GND

t

rCL

CLOCK

= 6ns

0.3V

2.7V

1.3V

0.3V

t

t

fCL

WL

= 6ns

1.3V

t

WL

1.3V

WH

UNITSMIN TYP MAX MIN MAX MIN MAX

I

fC

L

3V

GND

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table.For f

, input duty cycle = 50%.

MAX

FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

tr = 6ns tf = 6ns

V

t

CC

GND

TLH

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

90%
50%
10%

t

90%

50%

10%

PLH

FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table.For f

, input duty cycle = 50%.

MAX

FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

= 6ns

t

PLH

t

f

1.3V

10%

90%

t

TLH

3V

GND

tr = 6ns

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

2.7V

1.3V

0.3V

FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

6

CD54HC74, CD74HC74, CD74HCT74

Test Circuits and Waveforms

90%

t

PLH

IC

t

TLH

tfC

L

50%

C
50pF

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

OUTPUT

t

REM

V

CC

SET, RESET
OR PRESET

trC

L

90%

10%

t

H(H)

50%

(Continued)

t

H(L)

t

SU(L)

t

THL

90%

50%

10%
t

PHL

L

V

CC

GND

V

CC

50%
GND

GND

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

OUTPUT

t

REM

3V
SET, RESET
OR PRESET

trC

90%

t

PLH

IC

1.3V

t

TLH

tfC

L

1.3V

t

H(L)

1.3V

t

SU(L)

t

THL

90%

1.3V
10%

t

PHL

C

L

50pF

3V

GND

3V

GND

GND

L

2.7V

0.3V

t

H(H)

1.3V

1.3V

1.3V

FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVALTIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

7

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