Texas Instruments CD 74 HC 670 INSTALLATION INSTRUCTIONS

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Data sheet acquired from Harris Semiconductor

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SCHS195C

January 1998 - Revised October 2003

CD54HC670, CD74HC670,

CD74HCT670

High-Speed CMOS Logic

4x4 Register File

/Title
CD74H

670,
D74H

T670)
Subject
High-

peed

MOS

ogic

x4 Reg-

ster

Features

• Simultaneous and Independent Read and Write
Operations

• Expandable to 512 Words of n-Bits

• Three-State Outputs

• Organized as 4 Words x 4 Bits Wide

• Buffered Inputs

• Typical Read Time = 16ns for ’HC670 V
15pF, T

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

- CMOS Input Compatibility, I

= 25oC

A

at VCC = 5V

V

= 0.8V (Max), VIH = 2V (Min)

IL

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

= 5V, CL =

CC

o

C to 125oC

OH

Description

The ’HC670 and CD74HCT670 are 16-bit register files
organized as 4 words x 4 bits each. Read and write address
and enableinputs allow simultaneouswritinginto one location
while reading another. Four data inputs are provided to store
the 4-bit word. The write address inputs (WA0 and WA1)
determine the location of the stored word in the register.
When write enable (
address location and it remains transparent to the data. The
outputs will reflect the true form of the input data. When (
is high data and address inputs are inhibited. Data acquisition
from the four registers is made possible by the read address
inputs (RA1 and RA0). The addressed word appears at the
output when the read enable (
high impedance state when the (
tied together to increase the word capacity to 512 x 4 bits.

WE) is low the word is entered into the

RE) is low. The output is in the

RE) is high. Outputs can be

Ordering Information

TEMP. RANGE

PART NUMBER

CD54HC670F3A -55 to 125 16 Ld CERDIP
CD74HC670E -55 to 125 16 Ld PDIP
CD74HC670M -55 to 125 16 Ld SOIC

CC

CD74HC670MT -55 to 125 16 Ld SOIC
CD74HC670M96 -55 to 125 16 Ld SOIC
CD74HCT670E -55 to 125 16 Ld PDIP
CD74HCT670M -55 to 125 16 Ld SOIC
CD74HCT670MT -55 to 125 16 Ld SOIC
CD74HCT670M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of

250.

(oC) PACKAGE

WE)

Pinout

CD54HC670

(CERDIP)

CD74HC670, CD74HCT670

(PDIP, SOIC)

TOP VIEW

16

1

D1

2

D2

3

D3

4

RA1

5

RA0

6

Q3

7

Q2

8

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© 2003, Texas Instruments Incorporated

1

V

CC

15

D0

14

WA0

13

WA1

12

WE

11

RE

10

Q0

9

Q1

Functional Diagram

CD54HC670, CD74HC670, CD74HCT670CD54HC670, CD74HC670, CD74HCT670

15

D0

1

D1

2

D2

3

D3

12

WE

11

RE

RA1

RA0
WA0
WA1

4

WRITE MODE SELECT TABLE

INPUTS INTERNAL

OPERATING

MODE

N

LATCHES

(NOTE 1)WE D

Write Data L L L

LHH

Data Latched H X No Change

NOTE:

1. The Write Address (WA0 andWA1) to the “internal latches”must
be stable while WE is LOW for conventional operation.

10

Q0

9

Q1

7

Q2

6

Q3

514 13

READ MODE SELECT TABLE

INPUTS

INTERNAL

OPERATING

MODE

RE

LATCHES

(NOTE 2)

Read L L L

LHH

Disabled H X (Z)

NOTE:

2. The selection ofthe“internal latches” byReadAddress (RA0 and
RA1) are not constrained by WE or RE operation.
H = High Voltage Level
L = Low Voltage Level
X= Don’t Care
Z = High Impedance “Off” State

OUTPUT

Q

N

2

CD54HC670, CD74HC670, CD74HCT670CD54HC670, CD74HC670, CD74HCT670

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. The package thermal impedance is calculated in accordance with JESD 51-7.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

C -40oC TO 85oC -55oC TO 125oC

25

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-6 4.5 3.98 - - 3.84 - 3.7 - V

-7.8 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - - V

6 4.5 - - 0.26 - 0.33 - 0.4 V

7.8 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

3

CD54HC670, CD74HC670, CD74HCT670CD54HC670, CD74HC670, CD74HCT670

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device

I

CC

Current
Three-State Leakage

Current

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

V

IL

V

OH

CMOS Loads
High Level Output

Voltage
TTL Loads

Low Level Output

V

OL

Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

I

I

I

CC

Three-State Leakage
Current

Additional Quiescent
Device Current Per

∆I

CC

(Note 4)

Input Pin: 1 Unit Load

NOTE:

4. For dual-supply systems theoretical worst case (V

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

VCC or

GND

or VIHVO =

V

IL

VCC or

GND

- - 4.5 to

- - 4.5 to

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

VCCand

GND

VCC or

GND

or VIHVO =

V

IL

VCC or

GND

V

CC

-2.1

o

C -40oC TO 85oC -55oC TO 125oC

V

CC

(V)

25

UNITSV

0 6 - - 8 - 80 - 160 µA

6--±0.5 - ±5.0 - ±10 µA

2--2- 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

-6 4.5 3.98 - - 3.84 - 3.7 - V

6 4.5 - - 0.26 - 0.33 - 0.4 V

0 5.5 - ±0.1 - ±1-±1 µA

0 5.5 - - 8 - 80 - 160 µA

5.5 - - ±0.5 - ±5.0 - ±10 µA

- 4.5 to

- 100 360 - 450 - 490 µA

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

HCT Input Loading Table

INPUT UNIT LOADS

WE 0.3
WA0 0.2
WA1 0.4

RE 1.5

DATA 0.15

RA0 0.4
RA1 0.7

NOTE: UnitLoad is∆ICClimitspecific in DC Electrical Specifications
Table, e.g., 360µA max. at 25oC.

4

CD54HC670, CD74HC670, CD74HCT670CD54HC670, CD74HC670, CD74HCT670

Prerequisite for Switching Specifications

25oC -40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL VCC(V)

HC TYPES

Setup Time

tSU, t

h

Data to WE
Write to WE

Hold Time

tH, t

W

Data to WE
Write to WE

Pulse Width WE t

Latch Time WE to RA0,

W

t

LATCH

RA1

HCT TYPES

Setup Time

tSU, t

h

Data to WE

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

260- -75- -90--ns

4.5 12 - - 15 - - 18 - - ns
610- -13- -15--ns
25--5--5--ns

4.5 5 - - 5 - - 5 - - ns
65--5--5--ns
2 80 - - 100 - - 120 - - ns

4.5 16 - - 20 - - 24 - - ns
614- -17- -20--ns
2 100 - - 125 - - 150 - - ns

4.5 20 - - 25 - - 30 - - ns
617- -21- -26--ns

4.5 12 - - 15 - - 18 - - ns

Hold Time

tH, t

W

4.5 5 - - 5 - - 5 - - ns

Data to WE
Write to WE

Setup Time

t

SU

4.5 18 - - 23 - - 27 - - ns

Write to WE
Pulse Width WE t
Latch Time WE to RA0,

t

LATCH

W

4.5 20 - - 25 - - 30 - - ns

4.5 25 - - 31 - - 38 - - ns

RA1

Switching Specifications C

PARAMETER SYMBOL

= 50pF, Input tr, tf= 6ns

L

TEST

CONDITIONS VCC(V)

25oC

-40oC TO
85oC

-55oC TO
125oC

HC TYPES

Propagation Delay t

PLH

, t

PHLCL

= 50pF

Reading Any Word 2 - - 195 - 245 - 295 ns

4.5 - - 39 - 49 - 59 ns
CL = 15pF 5 - 16 - - - - - ns
CL = 50pF 6 - - 33 - 42 - 50 ns

Write Enable to Output t

PLH,tPHLCL

= 50pF 2 - - 250 - 315 - 375 ns

4.5 - - 50 - 63 - 75 ns
CL = 15pF 5 - 21 - - - - - ns
CL = 50pF 6 - - 43 - 54 - 64 ns

UNITSMIN TYP MAX MIN MAX MIN MAX

5