Texas Instruments CD 54 HCT 640, CD 74 HC 640, CD 74 HCT 640 INSTALLATION INSTRUCTIONS

www.DataSheet4U.com

Data sheet acquired from Harris Semiconductor

/
j

SCHS192B

January 1998 - Revised May 2003

CD54HC640, CD74HC640,

CD54HCT640, CD74HCT640

High-Speed CMOS Logic

Octal Three-State Bus Transceiver, Inverting

[ /Title
(CD74
HC640
,
CD74
HCT64

0)
Sub­ect

(High
Speed
CMOS

Features

• Buffered Inputs

• Three-State Outputs

• Applications in Multiple-Data-Bus Architecture

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, NIH = 30% of V

IL

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

≤ 1µA at VOL, V

l

o

C to 125oC

OH

Description

The ’HC640 and ’HCT640 silicon-gate CMOS three-state
bidirectional inverting and non-inverting buffers are intended
for two-way asynchronous communication between data
buses. They have high drive current outputs which enable
high-speed operation when driving large bus capacitances.
These circuits possess the low power dissipation of CMOS
circuits, and have speeds comparable to low power Schottky
TTL circuits. They can drive 15 LSTTL loads. The ’HC640
and ’HCT640 are inverting buffers.

The direction of data flow (A to B, B to A) is controlled by the
DIR input.

Outputs are enabled by a low on the Output Enable input
(

OE); a high OE puts these devices in the high impedance

mode.

Ordering Information

CC

TEMP. RANGE

PART NUMBER

CD54HC640F3A -55 to 125 20 Ld CERDIP
CD54HCT640F3A -55 to 125 20 Ld CERDIP
CD74HC640E -55 to 125 20 Ld PDIP

(oC) PACKAGE

Pinout

CD54HC640, CD54HCT640

(CERDIP)

CD74HC640, CD74HCT640

(PDIP, SOIC)

TOP VIEW

DIR

A0
A1
A2
A3
A4
A5
A6
A7

GND

1
2
3
4
5
6
7
8
9

10

20
19
18
17
16
15
14
13
12
11

V
OE
B0
B1
B2
B3
B4
B5
B6
B7

CD74HC640M -55 to 125 20 Ld SOIC
CD74HCT640E -55 to 125 20 Ld PDIP
CD74HCT640M -55 to 125 20 Ld SOIC

CC

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© 2003, Texas Instruments Incorporated

1

CD54HC640, CD74HC640, CD54HCT640, CD74HCT640CD54HC640, CD74HC640, CD54HCT640, CD74HCT640

Functional Diagram

A0

A1

THRU

A6

A7

OE

DIR

OUTPUT ENABLE AND

DIRECTION-SELECT LOGIC

TRUTH TABLE

CONTROL INPUTS DATA PORT STATUS
OE DIR A

n

B

n

LLOI
HHZZ
HLZZ

LHIO

B0

B1

THRU

B6

B7

VCC = 20

GND = 10

To prevent excess currents in the High-Z modes all I/O terminals
should be terminated with 1kΩ to 1MΩ resistors.
H = High Level
L = Low Level
I = Input
O = Output (Inversion of Input Level)
Z = High Impedance

2

CD54HC640, CD74HC640, CD54HCT640, CD74HCT640CD54HC640, CD74HC640, CD54HCT640, CD74HCT640

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

CC

Thermal Resistance (Typical, Note 1) θJA (oC/W)

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 69

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 58

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

C -40oC TO 85oC -55oC TO 125oC

25

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-6 4.5 3.98 - - 3.84 - 3.7 - V

-7.8 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - - V
6 4.5 - - 0.26 - 0.33 - 0.4 V

7.8 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

3

CD54HC640, CD74HC640, CD54HCT640, CD74HCT640CD54HC640, CD74HC640, CD54HCT640, CD74HCT640

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device

I

CC

Current
Three-State Leakage

I

OZ

Current

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

V

IL

V

OH

CMOS Loads
High Level Output

Voltage
TTL Loads

Low Level Output

V

OL

Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Three-State Leakage

I

I

I

CC

OZ

I

Current

Additional Quiescent
Device Current Per

∆I

CC

(Note 2)

Input Pin: 1 Unit Load

NOTE:

2. For dual-supply systems theoretical worst case (V

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

VCC or

GND

VILor VIHVO =

VCC or

GND

- - 4.5 to

- - 4.5 to

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

VCCand

GND

VCC or

GND

VILor VIHVO =

VCC or

GND

V

CC

-2.1

o

C -40oC TO 85oC -55oC TO 125oC

V

CC

(V)

25

UNITSV

0 6 - - 8 - 80 - 160 µA

6--±0.5 - ±5-±10 µA

2--2- 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

-6 4.5 3.98 - - 3.84 - 3.7 - V

6 4.5 - - 0.26 - 0.33 - 0.4 V

0 5.5 - - ±0.1 - ±1-±1 µA

0 5.5 - - 8 - 80 - 160 µA

5.5 - - ±0.5 - ±5-±10 µA

- 4.5 to

- 100 360 - 450 - 490 µA

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

HCT Input Loading Table

INPUT UNIT LOADS

DIR 0.9

OE, A 1.5

B 1.5

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Table,e.g.,
360µA max at 25oC.

4

CD54HC640, CD74HC640, CD54HCT640, CD74HCT640CD54HC640, CD74HC640, CD54HCT640, CD74HCT640

Switching Specifications C

PARAMETER SYMBOL

HC TYPES

Propagation Delay t

A to

B

B to A

Output High-Z
To High Level,
To Low Level

Output High Level
Output Low Level to High Z

Output Transition Time t

Input Capacitance C
Three-State Output

Capacitance
Power Dissipation Capacitance

(Notes 3, 4)

HCT TYPES

Propagation Delay

A to

B

B to A

Output High-Z
To High Level,
To Low Level

Output High Level
Output Low Level to High Z

Output Transition Time t
Input Capacitance C
Three-State Output

Capacitance
Power Dissipation Capacitance

(Notes 3, 4)

NOTES:

3. C

is used to determine the dynamic power consumption, per channel.

PD

4. PD = V

2

fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CC

PHL

t

PHL, tPLHCL

t

PHZ, tPLZ

THL

t

PHL, tPLHCL

t

PHL, tPLHCL

t

PHZ, tPLZ

THL

= 50pF, Input tr, tf= 6ns

L

TEST

CONDITIONS V

, t

PLHCL

= 50pF

CL = 15pF 5 - 7 - - - - - ns
C

= 50pF 6 - - 15 - 20 - 23 ns

L

= 50pF 2 - - 150 - 190 - 225 ns

C

= 15pF 5 - 12 - - - - - ns

L

= 50pF 6 - - 26 - 33 - 38 ns

C

L

CL = 50pF 2 - - 150 - 190 - 225 ns

CL = 15pF 5 - 12 - - - - - ns

= 50pF 6 - - 26 - 33 - 38 ns

C

L

, t

IN

C

O

C

PD

CL = 50pF 2 - - 60 - 75 - 90 ns

TLH

CL = 50pF - 10 - 10 - 10 - 10 pF

- - - - 20 - 20 - 20 pF

-5-38-----pF

= 50pF 4.5 - - 22 - 28 - 33 ns

C

= 15pF 5 - 9 - - - - - ns

L

= 50pF 4.5 - - 30 - 38 - 45 ns
= 15pF 5 - 12 - - - - - ns

C

L

CL = 50pF 4.5 - - 30 - 38 - 45 ns
C

= 15pF 5 - 12 - - - - - ns

L

, t

IN

C

O

C

PD

CL = 50pF 4.5 - - 12 - 15 - 18 ns

TLH

CL = 50pF - 10 - 10 - 10 - 10 pF

- - - - 20 - 20 - 20 pF

-5-41-----pF

CC

(V)

25

o

C

-40oC TO
85oC

-55oC TO
125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

2 - - 90 - 115 - 135 ns

4.5 - - 18 - 23 - 27 ns

4.5 - - 30 - 38 - 45 ns

4.5 - - 30 - 38 - 45 ns

4.5 - - 12 - 15 - 18 ns
6 - - 10 - 13 - 15 ns

5

CD54HC640, CD74HC640, CD54HCT640, CD74HCT640CD54HC640, CD74HC640, CD54HCT640, CD74HCT640

Test Circuits and Waveforms

tr = 6ns tf = 6ns

INPUT

90%
50%
10%

V

CC

GND

tr = 6ns

INPUT

2.7V

1.3V

0.3V

= 6ns

t

f

3V

GND

t

INVERTING

OUTPUT

THL

t

PHL

t

PLH

50%

10%

90%

t

TLH

FIGURE 7. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

6ns 6ns

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

50%

t

t

OUTPUTS
ENABLED

PLZ

PHZ

10%

90%

90%

10%

t

PZL

t

PZH

OUTPUTS

DISABLED

50%

50%

FIGURE 9. HCTHREE-STATE PROPAGATION DELAY

WAVEFORM

V

CC

GND

OUTPUTS
ENABLED

t

INVERTING

OUTPUT

THL

t

PHL

t

PLH

1.3V

10%

90%

t

TLH

FIGURE 8. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

0.3

t

t

PZH

6ns

PZL

1.3V

1.3V
OUTPUTS

ENABLED

t

r

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

t

t

OUTPUTS
ENABLED

6ns t

PLZ

PHZ

10%

90%

f

2.7

1.3

OUTPUTS

DISABLED

FIGURE 10. HCTTHREE-STATE PROPAGATION DELAY

WAVEFORM

3V

GND

NOTE: Open drain waveforms t
VCC, CL = 50pF.

FIGURE 11. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

TIED HIGH

and t

PLZ

OTHER

INPUTS

OR LOW

OUTPUT

DISABLE

PZL

IC WITH

THREE-

STATE

OUTPUT

OUTPUT
R

= 1kΩ

L

C

L

50pF

VCC FOR t
GND FOR t

PLZ

PHZ

AND t

AND t

PZL

PZH

are the same as those for three-state shown on the left. The test circuit is Output RL=1kΩ to

6

PACKAGE OPTION ADDENDUM

www.ti.com

30-Mar-2005

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

5962-8974001RA ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC

CD54HC640F3A ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC

CD54HCT640F3A ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC

CD74HC640E ACTIVE PDIP N 20 20 Pb-Free

CD74HC640M ACTIVE SOIC DW 20 25 Pb-Free

CD74HCT640E ACTIVE PDIP N 20 20 Pb-Free

CD74HCT640M ACTIVE SOIC DW 20 25 Pb-Free

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-NC-NC-NC

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

CU NIPDAU Level-NC-NC-NC

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

(3)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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Addendum-Page 1

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