Texas Instruments CD74HCT597M96, CD74HCT597M, CD74HCT597E, CD74HC597M96, CD74HC597M Datasheet

CD74HC597,

/
j

[ /Title
(CD74
HC597
,
CD74
HCT59

7)
Sub­ect

(High
Speed
CMOS

Data sheet acquired from Harris Semiconductor
SCHS191

January 1998

Features

• Buffered Inputs

• Asynchronous Parallel Load

• Typical f

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 60MHz at VCC=5V,CL= 15pF, TA=25oC

MAX

o

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

C to 125oC

CC

OH

CD74HCT597

High Speed CMOS Logic

8-Bit Shift Register with Input Storage

Description

The Harris CD74HC597 and CD74HCT597 are high-speed
silicon gate CMOS devices that are pin-compatible with the
LSTTL 597 devices. Each device consists of an 8-flip-flop
input register and an 8-bit parallel-in/serial-in, serial-out shift
register.Each register is controlled by its own clock. A “low”on
the parallel load input (
chronously into the shift register. A “low” master input (
clears the shift register. Serial input data can also be synchro­nously shifted through the shift register when

Ordering Information

PART NUMBER TEMP. RANGE (oC) PACKAGE

CD74HC597E -55 to 125 16 Ld PDIP E16.3
CD74HCT597E -55 to 125 16 Ld PDIP E16.3
CD74HC597M -55 to 125 16 Ld SOIC M16.15
CD74HCT597M -55 to 125 16 Ld SOIC M16.15

NOTES:

1. When ordering, use the entire part number.Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer and die is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.

PL) shifts parallel stored data asyn-

MR)

PL is high.

PKG.

NO.

Pinout

CD74HC597, CD74HCT597

(PDIP, SOIC)

TOP VIEW

V

1

D1
D2

2

D3

3

D4

4
5

D5
D6

6
7

D7

GND

8

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

1

16

CC

15

D0

14

D

S

13

PL

12

ST

CP

11

SH

CP

10

MR

9

Q7

File Number 1915.1

Functional Diagram

CD74HC597, CD74HCT597

PARALLEL

DAT A

INPUTS

ST

SH

DS

D0
D1

D2
D3
D4
D5
D6
D7

CP

CP

PL

MR

15

1
2
3
4

STORAGE

5
6

7
12
11

13
10

8 F/F
REG.

8-BIT

SHIFT

REG.

14

9

Q7

FUNCTION TABLE

ST

CP

SH

CP

PL MR FUNCTION

↑ X X X Data Loaded to Input Flip-Flops
↑ X L H Data Loaded from Inputs to Shift Register

No Clock Edge X L H Data Transferred from Input Flip-Flops to Shift Register

X X L L InvalidLogic, State of Shift Register Indeterminate when

Signals Removed
X X H L Shift Register Cleared
X ↑ H H Shift Register Clocked Qn = Qn-1, Q0 = D

S

NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,↑ = Transition from Low to High CP Level

2

CD74HC597, CD74HCT597

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

V

CC

(V)

25oC -40oC TO 85oC -55oCTO125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - -V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - -V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1µA

GND

3

CD74HC597, CD74HCT597

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device
Current

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load

I

CC

V

IH

V

IL

V

OH

V

OL

I

I

CC

∆I

CC

VCC or

GND

- - 4.5 to

- - 4.5 to

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

VCCand

I

GND

VCC or

GND

V

CC

-2.1

V

CC

(V)

0 6 - - 8 - 80 - 160 µA

5.5

5.5

-4 4.5 3.98 - - 3.84 - 3.7 - V

4 4.5 - - 0.26 - 0.33 - 0.4 V

0 5.5 - ±0.1 - ±1-±1µA

0 5.5 - - 8 - 80 - 160 µA

- 4.5 to

5.5

25oC -40oC TO 85oC -55oCTO125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

2--2 - 2 - V

- - 0.8 - 0.8 - 0.8 V

- 100 360 - 450 - 490 µA

HCT Input Loading Table

INPUT UNIT LOADS

D

S

D

n

PL, MR 1.5

STCP, SH

NOTE: Unitload is ∆ICClimit specified in DC Electrical Specifications
Table, e.g., 360µA max. at 25oC.

CP

0.2

0.3

1.5

Prerequisite for Switching Specifications

25oC -40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL VCC(V)

HC TYPES

SHCP Frequency f

MAX

2 6 - - 5 - - 4 - - MHz

4.5 30 - - 25 - - 20 - - MHz
6 35 - - 29 - - 23 - - MHz

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

4

CD74HC597, CD74HCT597

Prerequisite for Switching Specifications (Continued)

25oC -40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL V

SHCP Pulse Width t

STCP Pulse Width t

MR Pulse Width t

PL Pulse Width t

STCP to SHCP Setup
Time

D

to SHCP Setup Time

S

Dn to STCP Setup Time

(V)

CC

W

2 80 - - 100 - - 120 - - ns

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

4.5 16 - - 20 - - 24 - - ns
614--17- -20--ns

W

260--75- -90--ns

4.5 12 - - 15 - - 18 - - ns
610--13- -15--ns

W

2 80 - - 100 - - 120 - - ns

4.5 16 - - 20 - - 24 - - ns
614--17- -20--ns

W

2 70 - - 90 - - 105 - - ns

4.5 14 - - 18 - - 21 - - ns
612--15- -18--ns

t

SU

2 100 - - 125 - - 150 - - ns

4.5 20 - - 25 - - 30 - - ns
617--21- -26--ns

t

SU

250--65- -75--ns

4.5 10 - - 13 - - 15 - - ns

STCP to SHCP Setup
Time

D

to SHCP Hold Time

S

Dn to STCP Hold Time

MR to SHCP Removal
Time

HCT TYPES

SHCP Frequency f
SHCP Pulse Width t
STCP Pulse Width t
MR Pulse Width t
PL Pulse Width t
STCP to SHCP Setup

Time

t

REM

MAX

t

t

H

t

H

W

W

W

W

SU

6 9 - - 11 - - 13 - - ns
20--0--0--ns

4.5 0 - - 0 - - 0 - - ns
60--0--0--ns
23--3--3--ns

4.5 3 - - 3 - - 3 - - ns
63--3--3--ns
23--3--3--ns

4.5 3 - - 3 - - 3 - - ns
63--3--3--ns

4.5 25 - - 20 - - 16 - - MHz

4.5 20 - - 25 - - 30 - - ns

4.5 13 - - 16 - - 20 - - ns

4.5 18 - - 23 - - 27 - - ns

4.5 16 - - 20 - - 24 - - ns

4.5 24 - - 30 - - 36 - - ns

5

CD74HC597, CD74HCT597

Prerequisite for Switching Specifications (Continued)

25oC -40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL V

DS to SHCP Setup Time

t

H

(V)

CC

4.5 10 - - 13 - - 15 - - ns

Dn to STCP Setup Time
STCPto SHCPHold Time t
DS to SHCP Hold Time

H

t

H

4.5 0 - - 0 - - 0 - - ns

4.5 3 - - 3 - - 3 - - ns

Dn to STCP Hold Time
MR to SHCP Removal

t

REM

4.5 10 - - 13 - - 15 - - ns

Time

Switching Specifications Input t

PARAMETER SYMBOL

, tf = 6ns

r

CONDITIONS V

TEST

CC

25oC -40oCto85oC -55oC to 125oC

(V)

HC TYPES

Propagation Delay t

PLH,tPHL

CL= 50pF 2 - - 175 - 220 - 265 ns

SHCP to Q7 4.5 - - 35 - 44 - 53 ns

CL=15pF 5 - 14 - - - - - ns

CL= 50pF 6 - - 30 - 37 - 45 ns

PL to Q7 t

PLH,tPHL

CL= 50pF 2 - - 200 - 250 - 300 ns

4.5 - - 40 - 50 - 60 ns

CL=15pF 5 - 17 - - - - - ns

CL= 50pF 6 - - 34 - 43 - 51 ns

STCP to Q7 t

PLH,tPHL

CL= 50pF 2 - - 240 - 300 - 360 ns

4.5 - - 48 - 60 - 72 ns

CL=15pF 5 - 20 - - - - - ns

CL= 50pF 6 - - 41 - 51 - 61 ns

MR to Q7 t

PLH,tPHL

CL= 50pF 2 - - 175 - 220 - 265 ns

4.5 - - 35 - 44 - 53 ns

CL=15pF 5 - 14 - - - - - ns

CL= 50pF 6 - - 30 - 37 - 45 ns

Output Transition Time t

TLH

, t

CL= 50pF 2 - - 75 - 95 - 110 ns

THL

4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns

Input Capacitance C
Power Dissipation

C

I

PD

CL= 50pF - - - 10 - 10 - 10 pF

- 5 - 13.5 - - - - - pF

Capacitance, (Notes 4, 5)

HCT

Propagation Delay t

PLH,tPHL

SHCP to Q7 CL= 50pF 4.5 - - 38 - 48 - 57 ns

CL= 15pF 5 - 16 - - - - - ns

PL to Q7 t

PLH,tPHL

CL= 50pF 4.5 - - 48 60 72 ns
CL= 15pF 5 - 20 - - - - - ns

STCP to Q7 t

PLH,tPHL

CL= 50pF 4.5 - - 56 70 84 ns
CL= 15pF 5 - 23 - - - - - ns

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

UNITSMIN TYP MAX MIN MAX MIN MAX

6

CD74HC597, CD74HCT597

Switching Specifications Input t

, tf = 6ns (Continued)

r

TEST

PARAMETER SYMBOL

MR to Q7 t

PLH,tPHL

CONDITIONS V

CC

(V)

CL= 50pF 4.5 - - 44 - 55 - 66 ns

CL= 15pF 5 - 18 - - - - - ns
Output Transition Time t
Input Capacitance C
Power Dissipation

TLH

, t

I

C

PD

CL= 50pF 4.5 - - 15 - 19 - 22 ns

THL

CL= 50pF - - - 10 - 10 - 10 pF

- 5 - 18.5 - - - - - pF

Capacitance, (Notes 4, 5)

NOTES:

4. CPD is used to determine the dynamic power consumption, per package.

5. PD=CPDV

CC

2

fi+ Σ (CLV

2

fo) where: fi= Input Frequency, fo= Output Frequency, CL= Output Load Capacitance, VCC= Supply

CC

Voltage.

Test Circuits and Waveforms

trC

L

CLOCK

10%

90%

50%

10%

tfC

t

WL

L

tWL+ tWH=

50%

t

WH

fC

50%

I

L

V

CC

GND

25oC -40oCto85oC -55oC to 125oC

= 6ns

t

rCL

CLOCK

2.7V

0.3V

1.3V

0.3V

t

t

fCL

WL

= 6ns

1.3V

t

WH

t

WL

+ tWH=

1.3V

UNITSMIN TYP MAX MIN MAX MIN MAX

I

fC

L

3V

GND

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. Forf

, input duty cycle = 50%.

MAX

FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

tr = 6ns tf = 6ns

V

t

CC

GND

TLH

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

90%
50%
10%

t

90%

50%

10%

PLH

FIGURE 3. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. Forf

, input duty cycle = 50%.

MAX

FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

= 6ns

t

PLH

t

f

1.3V

10%

90%

t

3V

GND

TLH

tr = 6ns

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

2.7V

1.3V

0.3V

FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

7

CD74HC597, CD74HCT597

Test Circuits and Waveforms

90%

t

PLH

IC

t

TLH

tfC

L

50%

C
50pF

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

OUTPUT

t

REM

V

CC

SET, RESET
OR PRESET

trC

L

90%

10%

t

H(H)

50%

(Continued)

t

H(L)

t

SU(L)

t

THL

90%

50%

10%
t

PHL

L

V

CC

GND

V

CC

50%
GND

GND

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

OUTPUT

t

REM

3V
SET, RESET
OR PRESET

trC

90%

t

PLH

IC

1.3V

t

TLH

tfC

L

1.3V

t

H(L)

1.3V

t

SU(L)

t

THL

90%

1.3V
10%

t

PHL

C

L

50pF

3V

GND

3V

GND

GND

L

2.7V

0.3V

t

H(H)

1.3V

1.3V

1.3V

FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVALTIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

8

Timing Diagram

SHIFT CLOCK

SH

CP

CD74HC597, CD74HCT597

SERIAL DATE

MASTER RESET

PARALLEL LOAD

STORAGE CLOCK

PARALLEL

DAT A

INPUTS

ST

D

MR

PL

CP

S

D0

D1

D2

D3

D4

D5

D6

H

L

H

L

H

H

L

L

L

L

L

L

L

L

L

L

L

L

H

H

L

D7

Q7

RESET

SHIFT

REGISTER

FLIP-FLOPS

H

LL L L L L LLL L

SERIAL

SHIFT

LOAD

HHHH H H H HH

SERIAL

SHIFT

PARALLEL LOAD
SHIFT REGISTER

H

LOAD

FLIP-FLOPS

SERIAL

SHIFT

PARALLEL LOAD
SHIFT REGISTER

H

PARALLEL LOAD FLIP-FLOPS
AND SHIFT REGISTER

SERIAL

SHIFT

9

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