Texas Instruments CD74HCT4075E, CD74HC4075PWR, CD74HC4075M96, CD74HC4075M, CD74HC4075E Datasheet

CD74HC4075,

/

[ /Title
(CD74H
C4075,
CD74H
CT4075)

Subject
(High
Speed
CMOS
Logic
Triple 3­Input

Data sheet acquired from Harris Semiconductor
SCHS210

August 1997

Features

• Buffered Inputs

• Typical Propagation Delay: 8ns at V
C

= 15pF, TA = 25oC

L

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

CC

= 5V,

o

C to 125oC

CC

OH

CD74HCT4075

High Speed CMOS Logic

Triple 3-Input OR Gate

Description

The Harris CD74HC4075, CD74HCT4075 logic gates utilize
silicon-gate CMOS technology to achieve operating speeds
similar to LSTTL gates with the low power consumption of
standard CMOS integrated circuits. All devices have the
ability to drive 10 LSTTL loads. The 74HCT logic family is
functionally pin compatible with the standard 74LS logic
family.

Ordering Information

PKG.

PART NUMBER TEMP. RANGE (oC) PACKAGE

CD74HC4075E -55 to 125 14 Ld PDIP E14.3
CD74HC4075E -55 to 125 14 Ld PDIP E14.3
CD74HC4075M -55 to 125 14 Ld SOIC M14.15
CD74HC4075M -55 to 125 14 Ld SOIC M14.15
CD54HC4075H -55 to 125 Die
CD54HCT4075H -55 to 125 Die
CD54HC4075W -55 to 125 Wafer
CD54HCT4075W -55 to 125 Wafer

NO.

Pinout

NOTE: When ordering, usethe entire partnumber.Add the suffix 96
to obtain the variant in the tape and reel.

CD74HC4075, CD74HCT4075

(PDIP, SOIC)

TOP VIEW

2A
2B
1A
1B
1C
1C

GND

1
2
3
4
5
6
7

V

14

CC

3C

13

3B

12

3A

11

3Y

10

2Y

9

2C

8

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

1

File Number 1778.1

Functional Diagram

CD74HC4075, CD74HCT4075

3

1A

4

1B

5

1C

1

2A

2

2B

8

2C

11

3A

12

3B

13

3C

TRUTH TABLE

INPUTS OUTPUT

nA nB nC nY

6

1Y

9

2Y

10

3Y

GND = 7
V

= 14

CC

Logic Diagram

LLLL
HXXH
XHXH
XXHH

NOTE: H = High Voltage Level, L = Low Voltage Level, X = Irrelevant

nA

nB

nC

nY

2

CD74HC4075, CD74HCT4075

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . 100 N/A

SOIC Package. . . . . . . . . . . . . . . . . . . 180 N/A

Maximum Junction Temperature (Hermetic Pac kage or Die) . . .175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

C -40oC TO 85oC -55oCTO125oC

25

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1µA

GND

VCC or

0 6 - - 2 - 20 - 40 µA

GND

3

CD74HC4075, CD74HCT4075

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

V

IL

V

OH

CMOS Loads
High Level Output

Voltage
TTL Loads

Low Level Output
Voltage

V

OL

CMOS Loads
Low Level Output

Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

I

I

CC

∆I

CC

Input Pin: 1 Unit Load
(Note)

NOTE: For dual-supply systems theoretical worst case (V

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

- - 4.5 to

- - 4.5 to

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

4 4.5 - - 0.26 - 0.33 - 0.4 V

VCCand

0 5.5 - ±0.1 - ±1-±1µA

GND

VCC or

0 5.5 - - 2 - 20 - 40 µA

GND

V

CC

- 4.5 to

-2.1

o

C -40oC TO 85oC -55oCTO125oC

V

CC

25

(V)

2--2- 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

- 100 360 - 450 - 490 µA

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

UNITSV

HCT Input Loading Table

INPUT UNIT LOADS

All 1.6

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Table, e.g.
360µA max at 25oC.

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay,
Input to Output (Figure 1)

Transition Times (Figure 1) t

Input Capacitance C

r

t

PLH,tPHL

, t

TLH

THL

IN

, tf = 6ns

TEST

CONDITIONS VCC(V)

CL= 50pF 2 - - 100 - 125 - 150 ns

C

= 15pF 5 - 8 - - - - - ns

L

CL= 50pF 2 - - 75 - 95 - 110 ns

- - - - 10 - 10 - 10 pF

-40oC TO
85oC -55oC TO 125oC

25

o

C

UNITSMIN TYP MAX MIN MAX MIN MAX

4.5 - - 20 - 25 - 30 ns
6 - - 17 - 21 - 26 ns

4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns

4

CD74HC4075, CD74HCT4075

Switching Specifications Input t

, tf = 6ns (Continued)

r

PARAMETER SYMBOL

Power Dissipation Capacitance

C

PD

(Notes 2, 3)

HCT TYPES

Propagation Delay, Input to

t

PLH

, t

PHL

Output (Figure 2)

Transition Times (Figure 2) t
Input Capacitance C
Power Dissipation Capacitance

(Notes 2, 3)

TLH

, t

THL

IN

C

PD

NOTES:

2. C

is used to determine the dynamic power consumption, per gate.

PD

3. PD = V

2

fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CC

Test Circuits and Waveforms

tr = 6ns tf = 6ns

t

PHL

90%
50%
10%

t

PLH

INPUT

t

INVERTING

OUTPUT

THL

-40oC TO
85oC -55oC TO 125oC

TEST

25

o

C

CONDITIONS VCC(V)

-5-26-----pF

CL= 50pF 4.5 - - 24 - 30 - 36 ns
C

= 15pF 5 - 9 - - - - - ns

L

CL= 50pF 4.5 - - 15 - 19 - 22 ns

- - - - 10 - 10 - 10 pF

-5-28-----pF

= 6ns

t

PLH

t

f

1.3V

10%

90%

t

3V

GND

TLH

90%

50%

10%

t

TLH

V

CC

GND

tr = 6ns

INPUT

t

INVERTING

OUTPUT

THL

t

2.7V

1.3V

0.3V

PHL

UNITSMIN TYP MAX MIN MAX MIN MAX

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

FIGURE 2. HCTTRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

5

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