Texas Instruments CD 74 HCT 4046 A, CD 74 HC 4046 A, CD 54 HC 4046 A INSTALLATION INSTRUCTIONS
www.DataSheet4U.com
Data sheet acquired from Harris Semiconductor
SCHS204J
February 1998 - Revised December 2003
CD54HC4046A, CD74HC4046A,
CD54HCT4046A, CD74HCT4046A
High-Speed CMOS Logic
Phase-Locked Loop with VCO
[ /Title
(CD74
HC404
6A,
CD74
HCT40
46A)
/Subject
(HighSpeed
CMOS
Features
• Operating Frequency Range
- Up to 18MHz (Typ) at V
- Minimum Center Frequency of 12MHz at V
• Choice of Three Phase Comparators
- EXCLUSIVE-OR
- Edge-Triggered JK Flip-Flop
- Edge-Triggered RS Flip-Flop
• Excellent VCO Frequency Linearity
• VCO-Inhibit Control for ON/OFF Keying and for Low
Standby Power Consumption
• Minimal Frequency Drift
• Operating Power Supply Voltage Range
- VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V
- Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
= 5V
CC
o
= 30%, NIH = 30% of V
IL
≤ 1µA at VOL, VOH
l
= 4.5V
CC
C to 125oC
Applications
Description
The ’HC4046A and ’HCT4046A are high-speed silicon-gate
CMOS devices that are pin compatible with the CD4046B of
the “4000B” series. They are specified in compliance with
JEDEC standard number 7.
The ’HC4046A and ’HCT4046A are phase-locked-loop
circuits that contain a linear voltage-controlled oscillator
(VCO) and three different phase comparators (PC1, PC2 and
PC3). A signal input and a comparator input are common to
each comparator.
The signal input can be directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to small
voltage signals. A self-bias input circuit keeps small voltage
signals within the linear region of the input amplifiers. With a
passive low-pass filter, the 4046A forms a second-order loop
PLL. The excellent VCO linearity is achiev ed by the use of
linear op-amp techniques.
Ordering Information
TEMP. RANGE
PART NUMBER
CD54HC4046AF3A -55 to 125 16 Ld CERDIP
CD54HCT4046AF3A -55 to 125 16 Ld CERDIP
CD74HC4046AE -55 to 125 16 Ld PDIP
CD74HC4046AM -55 to 125 16 Ld SOIC
CD74HC4046AMT -55 to 125 16 Ld SOIC
CD74HC4046AM96 -55 to 125 16 Ld SOIC
CD74HC4046ANSR -55 to 125 16 Ld SOP
CC
CD74HC4046APWR -55 to 125 16 Ld TSSOP
CD74HC4046APWT -55 to 125 16 Ld TSSOP
CD74HCT4046AE -55 to 125 16 Ld PDIP
CD74HCT4046AM -55 to 125 16 Ld SOIC
CD74HCT4046AMT -55 to 125 16 Ld SOIC
CD74HCT4046AM96 -55 to 125 16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
(oC) PACKAGE
• FM Modulation and Demodulation
• Frequency Synthesis and Multiplication
• Frequency Discrimination
• Tone Decoding
• Data Synchronization and Conditioning
• Voltage-to-Frequency Conversion
• Motor-Speed Control
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
1
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046ACD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
Pinout
Functional Diagram
CD54HC4046A, CD54HCT4046A (CERDIP)
CD74HC4046A (PDIP, SOIC, SOP, TSSOP)
CD74HCT4046A (PDIP, SOIC)
TOP VIEW
16
PCP
PC1
COMP
VCO
COMP
SIG
GND
IN
IN
OUT
OUT
OUT
INH
C1
C1
1
2
3
IN
4
5
6
A
7
B
8
3
14
φ
V
CC
15
PC3
OUT
14
SIG
IN
13
PC2
OUT
12
R
2
11
R
1
10
DEM
OUT
9
VCO
IN
2
PC1
PC3
PC2
PCP
OUT
OUT
OUT
OUT
15
13
1
6
C1
A
C1
VCO
R
R
INH
7
B
11
1
12
2
IN
VCO
9
5
4
VCO
OUT
10
DEM
OUT
Pin Descriptions
PIN NUMBER SYMBOL NAME AND FUNCTION
1 PCP
2 PC1
3 COMP
4 VCO
OUT
OUT
IN
OUT
5 INH Inhibit Input
6C1
7C1
A
B
8 GND Ground (0V)
9 VCO
10 DEM
11 R
12 R
13 PC2
14 SIG
15 PC3
16 V
IN
OUT
1
2
OUT
IN
OUT
CC
Phase Comparator Pulse Output
Phase Comparator 1 Output
Comparator Input
VCO Output
Capacitor C1 Connection A
Capacitor C1 Connection B
VCO Input
Demodulator Output
Resistor R1 Connection
Resistor R2 Connection
Phase Comparator 2 Output
Signal Input
Phase Comparator 3 Output
Positive Supply Voltage
2
R2
C1
R1
R5
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046ACD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
674314
C1
C1
V
REF
R2
12
+
-
R1
11
10
DEM
OUT
-
+
B
A
VCO
-
+
INH
59
VCO
COMP
OUT
VCO
IN
SIG
IN
IN
PC1
OUT
2
PC2
PC3
OUT
PCP
OUT
V
CC
GND
p
n
OUT
15
13
1
R3
C2
S
D
Q
Q
R
D
CC
V
V
CC
D
CP
D
CP
UP
Q
Q
R
D
Q
DOWN
Q
R
D
FIGURE 1. LOGIC DIAGRAM
General Description
VCO
The VCO requires one external capacitor C1 (between C1
and C1B) and one external resistor R1 (between R1and
GND) or two external resistors R1 and R2 (between R
GND, and R
determine the frequency range of the VCO. Resistor R2
enables the VCO to have a frequency offset if required. See
logic diagram, Figure 1.
The high input impedance of the VCO simplifies the design
of low-pass filters by giving the designer a wide choice of
resistor/capacitor ranges. In order not to load the low-pass
filter, a demodulator output of the VCO input voltage is
provided at pin 10 (DEM
techniques where the DEM
voltage lower than the VCO input voltage, here the DEM
voltage equals that of the VCO input. If DEM
load resistor (R
GND; if unused, DEM
output (VCO
comparator input (COMP
divider. The VCO output signal has a specified duty factor of
50%. A LOW level at the inhibit input (INH) enables the VCO
and demodulator, while a HIGH level turns both off to
minimize standby power consumption.
and GND). Resistor R1 and capacitor C1
2
). In contrast to conventional
OUT
) should be connected from DEM
S
OUT
) can be connected directly to the
OUT
IN
voltage is one threshold
OUT
is used, a
OUT
OUT
should be left open. The VCO
), or connected via a frequency-
1
and
OUT
Phase Comparators
The signal input (SIG
A
biasing amplifier at pin 14, provided that the signal swing is
) can be directly coupled to the self-
IN
between the standard HC family input logic levels.
Capacitive coupling is required for signals with smaller
swings.
Phase Comparator 1 (PC1)
This is an Exclusive-OR network. The signal and comparator
input frequencies (f
) must have a 50% duty factor to obtain
i
the maximum locking range. The transfer characteristic of
PC1, assuming ripple (f
V
DEMOUT
=(VCC/π)(φSIGIN- φCOMPIN) where V
is the demodulator output at pin 10; V
= 2fi) is suppressed, is:
r
DEMOUT=VPC1OUT
(via low-pass filter).
The average output voltage from PC1, fed to the VCO input
via the low-pass filter and seen at the demodulator output at
to
pin 10 (V
DEMOUT
of signals (SIG
shown in Figure 2. The average of V
V
when there is no signal or noise at SIGIN, and with this
CC
), is the resultant of the phase differences
) and the comparator input (COMPIN)as
IN
is equal to 1/2
DEM
input the VCO oscillates at the center frequency (f
Typical waveforms for the PC1 loop locked at f
o
in Figure 3.
DEMOUT
o
are shown
).
3
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046ACD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
The frequency capture range (2f
) is defined as the
C
frequency range of input signals on which the PLL will lock if
it was initially out-of-lock. The frequency lock range (2f
L
)is
defined as the frequency range of input signals on which the
loop will stay locked if it was initially in lock. The capture
range is smaller or equal to the lock range.
With PC1, the capture range depends on the low-pass filter
characteristics and can be made as large as the lock range.
This configuration retains lock behavior even with very noisy
input signals. Typical of this type of phase comparator is that
it can lock to input frequencies close to the harmonics of the
VCO center frequency.
V
CC
V
DEMOUT (AV)
1/2 V
CC
0
o
0
o
φ
90
DEMOUT
180
o
FIGURE 2. PHASE COMPARATOR1: AVERAGE OUTPUT
VOLTAGE vs INPUT PHASE DIFFERENCE:
SIG
COMP
VCO
PC1
VCO
IN
IN
OUT
OUT
IN
V
DEMOUT
φCOMPIN); φ
= V
DEMOUT
= (VCC/π) (φSIGIN -
PC1OUT
=(φSIGIN - φCOMPIN)
V
CC
GND
FIGURE 3. TYPICAL WAVEFORMSFOR PLL USING PHASE
COMPARATOR 1, LOOP LOCKED AT f
o
Phase Comparator 2 (PC2)
This is a positive edge-triggered phase and frequency
detector. When the PLL is using this comparator, the loop
is controlled by positive signal transitions and the duty
factors of SIG
and COMPINare not important. PC2
IN
comprises two D-type flip-flops, control-gating and a threestate output stage. The circuit functions as an up-down
counter (Figure 1) where SIG
COMP
assuming ripple (f
a down-count. The transfer function of PC2,
IN
= fi) is suppressed, is:
r
causes an up-count and
IN
V
DEMOUT
V
DEMOUT
V
DEMOUT
=(VCC/4π)(φSIGIN- φCOMPIN) where
is the demodulator output at pin 10;
=V
PC2OUT
(via low-pass filter).
The average output voltage from PC2, fed to the VCO via the
low-pass filter and seen at the demodulator output at pin 10
(V
DEMOUT
SIG
for the PC2 loop locked at f
V
DEMOUT (AV)
FIGURE 4. PHASE COMPARATOR 2: AVERAGE OUTPUT
FIGURE 5. TYPICAL WAVEFORMS FOR PLL USING PHASE
When the frequencies of SIG
the phase of SIG
driver at PC2
the phase difference (φ
), is the resultant of the phase differences of
and COMPINas shown in Figure 4. Typical waveforms
IN
COMP
VCO
PC2
PCP
V
CC
1/2 V
CC
0
o
-360
VOLTAGE vs INPUT PHASE DIFFERENCE:
V
DEMOUT
= (VCC/4π) (φSIGIN - φCOMPIN);
φ
DEMOUT
SIG
IN
IN
OUT
OUT
HIGH IMPEDANCE OFF - STATE
VCO
IN
OUT
COMPARATOR 2, LOOP LOCKED AT f
leads that of COMPIN, the p-type output
IN
is held “ON” for a time corresponding to
OUT
are shown in Figure 5.
o
o
0
= V
PC2OUT
=(φSIGIN - φCOMPIN)
and COMPINare equal but
IN
DEMOUT
). When the phase of SIG
φ
DEMOUT
V
CC
GND
o
360
o
IN
lags that of COMPIN, the n-type driver is held “ON”.
When the frequency of SIGINis higher than that of
COMP
, the p-type output driver is held “ON” for most of
IN
the input signal cycle time, and for the remainder of the
cycle both n- and p-type drivers are “OFF” (three-state). If
the SIG
frequency is lower than the COMPINfrequency,
IN
then it is the n-type driver that is held “ON” for most of the
cycle. Subsequently, the voltage at the capacitor (C2) of
the low-pass filter connected to PC2
varies until the
OUT
signal and comparator inputs are equal in both phase and
4
COMPARATOR 3, LOOP LOCKED AT f
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
frequency. At this stable point the voltage on C2 remains
constant as the PC2 output is in three-state and the VCO
input at pin 9 is a high impedance. Also in this condition,
the signal at the phase comparator pulse output (PCP
is a HIGH level and so can be used for indicating a locked
condition.
OUT
)
V
DEMOUT (AV)
V
CC
Thus, for PC2, no phase difference exists between SIG
IN
and COMPINover the full frequency range of the VCO.
Moreover, the power dissipation due to the low-pass filter is
reduced because both p- and n-type drivers are “OFF” for
most of the signal input cycle. It should be noted that the
PLL lock range for this type of phase comparator is equal to
the capture range and is independent of the low-pass filter.
With no signal present at SIG
, the VCO adjusts, via PC2,
IN
to its lowest frequency.
Phase Comparator 3 (PC3)
This is a positive edge-triggered sequential phase
detector using an RS-type flip-flop. When the PLL is using
this comparator, the loop is controlled by positive signal
transitions and the duty factors of SIG
and COMPINare
IN
not important. The transfer character istic of PC3,
assuming ripple (f
V
DEMOUT
V
DEMOUT
= V
PC3OUT
is the demodulator output at pin 10; V
= fi) is suppressed, is:
r
=(VCC/2p) (fSIGIN- fCOMPIN) where
(via low-pass filter).
DEMOUT
The average output from PC3, fed to the VCO via the lowpass filter and seen at the demodulator at pin 10
(V
DEMOUT
SIG
waveforms for the PC3 loop locked at f
), is the resultant of the phase differences of
and COMPINas shown in Figure 6. Typical
IN
are shown in
o
Figure 7.
The phase-to-output response characteristic of PC3
(Figure 6) differs from that of PC2 in that the phase angle
between SIG
and COMPINvaries between 0oand 360
IN
and is 180oat the center frequency. Also PC3 gives a
greater voltage swing than PC2 for input phase differences
but as aconsequence the ripple content of the VCO input
signal is higher. With no signal present at SIG
, the VCO
IN
adjusts, via PC3, to its highest frequency.
1/2 V
CC
0
o
0
FIGURE 6. PHASE COMPARATOR3: AVERAGE OUTPUT
VOLTAGE vs INPUT PHASE DIFFERENCE:
V
DEMOUT
= (VCC/2π) (φSIGIN - φCOMPIN);
φ
DEMOUT
SIG
IN
COMP
IN
VCO
OUT
PC3
OUT
VCO
IN
FIGURE 7. TYPICAL WAVEFORMSFOR PLL USING PHASE
o
= V
PC3OUT
= (φSIGIN - φCOMPIN)
180
o
φ
DEMOUT
360
V
CC
GND
o
The only difference between the HC and HCT versions is the
input level specification of the INH input. This input disables
the VCO section. The comparator’s sections are identical, so
that there is no difference in the SIG
(pin 14) or COMP
IN
(pin 3) inputs between the HC and the HCT versions.
IN
5
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046ACD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, I
O
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Source or Sink Current per Output Pin, I
O
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, V
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
CC
Package Thermal Impedance, θJA(see Note 1):
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W
PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CC
DC Electrical Specifications
PARAMETER SYMBOL
HC TYPES
VCO SECTION
INH High Level Input
Voltage
INH Low Level Input
Voltage
VCO
High Level
OUT
Output Voltage
CMOS Loads
VCO
High Level
OUT
Output Voltage
TTL Loads
VCO
OUT
Low Level
Output Voltage
CMOS Loads
VCO
OUT
Low Level
Output Voltage
TTL Loads
C1A, C1B Low Level
Output Voltage
(Test Purposes Only)
V
IH
V
IL
V
OH
V
OL
V
OL
TEST
CONDITIONS
V
CC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
- - 3 2.1 - - 2.1 - 2.1 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
- - 3 - - 0.9 - 0.9 - 0.9 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
VIHor VIL-0.02 3 2.9 - - 2.9 - 2.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
- - ---- - - - V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
- - ---- - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
VILor V
4 4.5 - - 0.40 - 0.47 - 0.54 V
IH
5.2 6 - - 0.40 - 0.47 - 0.54 V
6
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
DC Electrical Specifications (Continued)
TEST
PARAMETER SYMBOL
INH VCOIN Input
Leakage Current
CONDITIONS
I
VCC or
I
-6--±0.1 - ±1-±1 µA
GND
V
CC
(V)
R1 Range (Note 2) - - - 4.5 3 - 300 - - - - kΩ
R2 Range (Note 2) - - - 4.5 3 - 300 - - - - kΩ
C1 Capacitance
Range
---3--No
4.5 - - - - - - pF
6-- ----pF
VCOIN Operating
Voltage Range
- Over the range
specified for R1 for
LinearitySeeFigure
10, and 34 - 37
3 1.1 - 1.9 - - - - V
4.5 1.1 - 3.2 - - - - V
6 1.1 - 4.6 - - - - V
(Note 3)
PHASE COMPARATOR SECTION
SIGIN, COMP
IN
DC Coupled
High-Level Input
Voltage
SIGIN, COMP
IN
DC Coupled
Low-Level Input
Voltage
PCP
, PCn OUT
OUT
High-Level Output
Voltage
CMOS Loads
PCP
, PCn OUT
OUT
High-Level Output
Voltage
V
IH
- - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
V
IL
- - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
V
VILor VIH-0.02 2 1.9 - - 1.9 - 1.9 - V
OH
4.5 4.4 - - 4.4 - 4.4 - V
6 5.9 - - 5.9 - 5.9 - V
V
OH
VILor V
-4 4.5 3.98 - - 3.84 - 3.7 - V
IH
-5.2 6 5.48 - - 5.34 - 5.2 - V
TTL Loads
PCP
Low-Level Output
Voltage
CMOS Loads
PCP
Low-Level Output
Voltage
, PCn OUT
OUT
, PCn OUT
OUT
V
OL
VILor V
0.02 2 - - 0.1 - 0.1 - 0.1 V
IH
4.5 - - 0.1 - 0.1 - 0.1 V
6 - - 0.1 - 0.1 - 0.1 V
V
OL
VILor V
4 4.5 - - 0.26 - 0.33 - 0.4 V
IH
5.2 6 - - 0.26 - 0.33 - 0.4 V
TTL Loads
SIGIN, COMPINInput
Leakage Current
I
VCC or
I
GND
-2--±3-±4-±5 µA
3--±7- ±9-±11 µA
4.5 - - ±18 - ±23 - ±29 µA
6--±30 - ±38 - ±45 µA
PC2
Three-State
OUT
I
OZ
VILor V
-6--±0.5 - ±5-±10 µA
IH
Off-State Current
SIGIN, COMPINInput
Resistance
R
I
VI at Self-Bias
Operation Point:
∆VI = 0.5V,
See Figure 10
3 - 800 - - - - - kΩ
4.5 - 250 - - - - - kΩ
6 - 150 - - - - - kΩ
DEMODULATOR SECTION
Resistor Range R
S
at RS > 300kΩ
Leakage Current
Can Influence
V
DEMOUT
3 50 - 300 - - - - kΩ
4.5 50 - 300 - - - - kΩ
6 50 - 300 - - - - kΩ
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
----pF
Limit
7
V
C
2
V
C
2
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
DC Electrical Specifications (Continued)
TEST
PARAMETER SYMBOL
OffsetVoltage VCO
to V
DEM
IN
V
OFF
CONDITIONS
VI = V
VCO IN
C
Values Taken Over
V
CC
(V)
=
3-±30 - - - - - mV
4.5 - ±20 - - - - - mV
6-±10 - - - - - mV
RS Range
See Figure 23
Dynamic Output
Resistance at
DEM
OUT
Quiescent Device
Current
R
D
V
C
DEMOUT
=3-25-----Ω
4.5 - 25 - - - - - Ω
6 - 25 - - - - - Ω
I
CC
Pins 3, 5 and 14
6 - - 8 - 80 - 160 µA
at VCC Pin 9 at
GND, I1 at Pins 3
and 14 to be
excluded
HCT TYPES
VCO SECTION
INH High Level Input
Voltage
INH Low Level Input
Voltage
VCO
High Level
OUT
V
IH
- - 4.5 to
5.5
V
IL
- - 4.5 to
5.5
V
VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V
OH
Output Voltage
CMOS Loads
VCO
High Level
OUT
-4 4.5 3.98 - - 3.84 - 3.7 - V
Output Voltage
TTL Loads
VCO
OUT
Low Level
V
VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V
OL
Output Voltage
CMOS Loads
VCO
OUT
Low Level
4 4.5 - - 0.26 - 0.33 - 0.4 V
Output Voltage
TTL Loads
C1A, C1B Low Level
V
OL
VIHor V
4 4.5 - - 0.40 - 0.47 - 0.54 V
IL
Output Voltage
(Test Purposes Only)
INH VCOIN Input
Leakage Current
I
I
Any Voltage
Between VCC and
5.5 - ±0.1 - ±1-±1 µA
GND
R1 Range (Note 2) - - - 4.5 3 - 300 - - - - kΩ
R2 Range (Note 2) - - - 4.5 3 - 300 - - - - kΩ
C1 Capacitance
- - - 4.5 0 - No
Range
VCOIN Operating
Voltage Range
- Over the range
specified for R1 for
4.5 1.1 - 3.2 - - - - V
LinearitySeeFigure
10, and 34 - 37
(Note 3)
PHASE COMPARATOR SECTION
SIGIN, COMP
DC Coupled
IN
V
IH
- - 4.5 to
5.5
High-Level Input
Voltage
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
2--2- 2 - V
- - 0.8 - 0.8 - 0.8 V
----pF
Limit
2--2- 2 - V
8
V
C
2
V
C
2
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
DC Electrical Specifications (Continued)
TEST
CONDITIONS
PARAMETER SYMBOL
SIGIN, COMP
IN
DC Coupled
Low-Level Input
Voltage
PCP
, PCn OUT
OUT
High-Level Output
Voltage
CMOS Loads
PCP
, PCn OUT
OUT
High-Level Output
Voltage
TTL Loads
PCP
, PCn OUT
OUT
Low-Level Output
Voltage
CMOS Loads
PCP
, PCn OUT
OUT
Low-Level Output
Voltage
TTL Loads
SIGIN, COMPINInput
Leakage Current
PC2
Three-State
OUT
Off-State Current
SIGIN, COMPINInput
Resistance
DEMODULATOR SECTION
Resistor Range R
OffsetVoltage VCO
to V
DEM
V
IL
V
OH
V
OH
V
OL
V
OL
I
I
- - 4.5 to
VILor V
IH
VILor V
IH
VILor V
IH
VILor V
IH
Any
Voltage
Between
VCCand
GND
I
VILor V
OZ
R
I
IH
VI at Self-Bias
Operation Point:
∆VI = 0.5V,
See Figure 10
S
at RS > 300kΩ
Leakage Current
Can Influence
V
DEM OUT
V
IN
OFF
VI = V
C
VCO IN
V
CC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
- - 0.8 - 0.8 - 0.8 V
5.5
- 4.5 4.4 - - 4.4 - 4.4 - V
- 4.5 3.98 - - 3.84 - 3.7 - V
- 4.5 - - 0.1 - 0.1 - 0.1 V
- 4.5 - - 0.26 - 0.33 - 0.4 V
- 5.5 - - ±30 ±38 ±45 µA
- 5.5 - - ±0.5 ±5- -±10 µA
4.5 - 250 - - - - - kΩ
4.5 5 - 300 - - - - kΩ
=
4.5 - ±20 - - - - - mV
Values tak en over
RS Range
See Figure 23
Dynamic Output
Resistance at
DEM
OUT
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
R
D
I
CC
∆I
CC
(Note 4)
V
DEM OUT
C
VCC or
GND
V
CC
-2.1
Excluding
= 4.5 - 25 - - - - - Ω
- 5.5 - - 8 - 80 - 160 µA
- 4.5 to
- 100 360 - 450 - 490 µA
5.5
Pin 5
NOTES:
2. The value for R1 and R2 in parallel should exceed 2.7kΩ.
3. The maximum operating voltage can be as high as VCC -0.9V, however, this may result in an increased offset voltage.
4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
9
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
HCT Input Loading Table
INPUT UNIT LOADS
INH 1
NOTE: Unitload is ∆ICClimit specific in DC Electrical Specifications
Table, e.g., 360µA max. at 25oC.
Switching Specifications C
PARAMETER SYMBOL
HC TYPES
PHASE COMPARATOR SECTION
Propagation Delay t
SIGIN, COMPIN to PCI
SIGIN, COMPIN to PCP
SIGIN, COMPIN to PC3
Output Transition Time t
Output Enable Time, SIGIN,
COMPIN to PC2
OUT
Output Disable Time, SIGIN,
COMPIN to PC2
OUT
AC Coupled Input Sensitivity
(
) at SIGIN or COMP
P-P
VCO SECTION
Frequency Stability with
Temperature Change
Maximum Frequency f
OUT
OUT
OUT
IN
= 50pF, Input tr, tf= 6ns
L
TEST
CONDITIONS VCC(V)
, t
PLH
PHL
, t
THL
TLH
t
, t
PZH
PZL
t
, t
PHZ
PLZ
V
I(P-P)
∆f
∆T
MAX
R1 = 100kΩ,
R
= ∞
2
C1 = 50pF
R1 = 3.5kΩ
R
= ∞
2
C1 = 0pF
R1 = 9.1kΩ
R
= ∞
2
25oC
-40oC TO
85oC
-55oC TO
125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
2 - - 200 - 250 - 300 ns
4.5 - - 40 - 50 - 60 ns
6 - - 34 - 43 - 51 ns
2 - - 300 - 375 - 450 ns
4.5 - - 60 - 75 - 90 ns
6 - - 51 - 64 - 77 ns
2 - - 245 - 305 - 307 ns
4.5 - - 49 - 61 - 74 ns
6 - - 42 - 52 - 63 ns
2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
2 - - 265 - 330 - 400 ns
4.5 - - 53 - 66 - 80 ns
6 - - 45 - 56 - 68 ns
2 - - 315 - 395 - 475 ns
4.5 - - 63 - 79 - 95 ns
6 - - 54 - 67 - 81 ns
3 - 11 - - - - - mV
4.5 - 15 - - - - - mV
6 - 33 - - - - - mV
3 - 0.11 - - - - - %/oC
4.5 - 0.11 - - - - - %/oC
6 - 0.11 - - - - - %/oC
3 - 24 - - - - - MHz
4.5 - 24 - - - - - MHz
6 - 24 - - - - - MHz
3 - 38 - - - - - MHz
4.5 - 38 - - - - - MHz
6 - 38 - - - - - MHz
10
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