Texas Instruments CD74HCT4040M96, CD74HCT4040M, CD74HCT4040E, CD74HC4040M96, CD74HC4040M Datasheet
...
CD74HC4040,
/
[ /Title
(CD74H
C4040,
CD74HC
T4040)
Subject
(High
Speed
CMOS
Logic
12-Stage
Binary
Data sheet acquired from Harris Semiconductor
SCHS203
February 1998
Features
• Fully Static Operation
• Buffered Inputs
• Common Reset
• Negative Edge Pulsing
• Typical f
T
= 25oC
A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
= 60 MHz at VCC = 5V, CL = 15pF,
MAX
= 30%, NIH = 30% of V
IL
o
C to 125oC
CC
CD74HCT4040
High Speed CMOS Logic
12-Stage Binary Counter
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
Description
The Harris CD74HC4040 and CD74HCT4040 are 14-stage
ripple-carry binary counters. All counter stages are masterslave flip-flops. The state of the stage advances one count
on the negative clock transition of each input pulse; a high
voltage level on the MR line resets all counters to their zero
state. All inputs and outputs are buffered.
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE
CD74HC4040E -55 to 125 16 Ld PDIP E16.3
CD74HCT4040E -55 to 125 16 Ld PDIP E16.3
≤ 1µA at VOL, V
l
OH
PKG.
NO.
Pinout
CD74HC4040, CD74HCT4040
(PDIP, SOIC)
TOP VIEW
16
Q
Q
Q
Q7
Q
Q
Q
GND
1
12
2
6
3
5
4
5
4
6
3
7
2
8
V
Q
15
14
Q
13
Q
12
Q
11
MR
10
CP
Q
9
CC
11
10
8
9
‘
1
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1998
1
File Number 1483.2
Functional Diagram
CD74HC4040, CD74HCT4040
V
CC
16
10
INPUT
PULSES
12-STAGE
RIPPLE
COUNTER
11
MASTER
RESET
GND
TRUTH TABLE
9
Q1’
7
Q
2
6
Q
3
5
Q
4
3
Q
5
2
Q
6
Q
Q
Q
Q
Q
Q
7
8
9
10
11
12
BUFFERED
OUTPUTS
4
13
12
14
15
1
8
CP COUNT MR OUTPUT STATE
↑ L No Change
↓ L Advance to Next State
X H All Outputs Are Low
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,
↑ = Transition from Low to High Level, ↓ = Transition from High to Low.
2
Logic Diagram
CD74HC4040, CD74HCT4040
1
Q
R
12
CP Q
CP
Q
R
11
CP Q
CP
Q
R
10
CP Q
CP
Q
9
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
R
CP
Q
8
R
CP
Q
7
R
CP
Q
6
R
CP
Q
5
R
CP
Q
4
R
CP
Q
3
R
CP
Q
2
R
CP
Q
Q’
I
R
CP
15
14
12
13
4
2
3
5
6
7
9
12
Q
11
Q
10
Q
9
Q
8
Q
7
Q
6
Q
5
Q
4
Q
3
Q
2
Q
’
1
Q
10
CP
11
MR
3
CD74HC4040, CD74HCT4040
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I
O
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, V
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
CC
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CC
DC Electrical Specifications
PARAMETER SYMBOL
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
V
IH
V
IL
V
V
I
VIH or VIL-0.02 2 1.9 - - 1.9 - 1.9 - V
OH
VIH or VIL0.02 2 - - 0.1 - 0.1 - 0.1 V
OL
I
I
CC
TEST
CONDITIONS
(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
I
VCC (V)
o
C -40oC TO 85oC -55oCTO125oC
25
- - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
- - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
- - ----- - -V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
- - ----- - -V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
VCC or
-6--±0.1 - ±1-±1µA
GND
VCC or
0 6 - - 8 - 80 - 160 µA
GND
UNITSV
4
CD74HC4040, CD74HCT4040
DC Electrical Specifications (Continued)
TEST
CONDITIONS
PARAMETER SYMBOL
HCT TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
V
IH
V
IL
V
OH
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
V
OL
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent Device Current
I
I
I
CC
∆I
CC
Per Input Pin: 1 Unit
Load
NOTE: For dual-supply systems theoretical worst case (V
(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
I
- - 4.5 to 5.5 2 - - 2 - 2 - V
- - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V
VIH or VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-4 4.5 3.98 - - 3.84 - 3.7 - V
VIH or VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V
4 4.5 - - 0.26 - 0.33 - 0.4 V
VCC and
0 5.5 - - ±0.1 - ±1-±1µA
GND
VCC or
0 5.5 - - 8 - 80 - 160 µA
GND
V
CC
- 4.5 to 5.5 - 100 360 - 450 - 490 µA
-2.1
o
C -40oC TO 85oC -55oCTO125oC
25
V
(V)
CC
= 2.4V, VCC = 5.5V) specification is 1.8mA.
I
UNITSV
HCT Input Loading Table
INPUT UNIT LOADS
MR 0.65
CP 0.5
NOTE: Unit Load is ∆ICClimit specified in DC Electrical Table, e.g.,
360µA max at 25oC.
Prerequisite for Switching Specifications
PARAMETER SYMBOL VCC (V)
HC TYPES
Maximum Input Pulse
Frequency
Input Pulse Width t
f
MAX
W
26-5-4-MHz
4.5 30 - 25 - 20 - MHz
635-29-24-MHz
2 80 - 100 - 120 - ns
4.516-20-24-ns
614-17-20-ns
o
25
C -40oC TO 85oC -55oC TO 125oC
UNITSMIN MAX MIN MAX MIN MAX
5
CD74HC4040, CD74HCT4040
Prerequisite for Switching Specifications (Continued)
25
PARAMETER SYMBOL V
Reset Removal Time t
Reset Pulse Width t
HCT TYPES
Maximum Input Pulse
Frequency
Input Pulse Width t
Reset Recovery Time t
Reset Pulse Width t
REM
f
MAX
REM
W
W
W
(V)
CC
250-65-75-ns
4.510-13-15-ns
6 9 -11-13-ns
2 80 - 100 - 120 - ns
4.516-20-24-ns
614-17-20-ns
4.5 25 - 20 - 16 - MHz
4.520-25-30-ns
4.510-13-15-ns
4.520-25-30-ns
o
C -40oC TO 85oC -55oC TO 125oC
UNITSMIN MAX MIN MAX MIN MAX
Switching Specifications Input t
PARAMETER SYMBOL
, tf = 6ns
r
TEST
CONDITIONS V
CC
(V)
25oC
-40oC TO
85oC
-55oC TO
125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Propagation Delay
t
PLH,tPHLCL
= 50pF 2 - - 140 - 175 - 210 ns
(Figure 1)
CP to Q1’ Output 4.5 - - 28 - 35 - 42 ns
CL=15pF 5 - 11 -----ns
C
= 50pF 6 - - 24 - 30 - 36 ns
L
Qnto Qn+ 1 t
PLH,tPHLCL
= 50pF 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
CL=15pF 5 - 4 -----ns
C
= 50pF 6 - - 13 - 16 - 19 ns
L
MR to Q
n
t
PLH,tPHLCL
= 50pF 2 - - 170 - 215 - 255 ns
4.5 - - 34 - 43 - 51 ns
5 -14-----ns
6 - -29-37-43ns
Output Transition Time
(Figure 1)
t
TLH,tTHLCL
= 50pF 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
6 - -13-16-19ns
Input Capacitance C
Power Dissipation
C
CL= 50pF - - - 10 - 10 - 10 pF
IN
CL=15pF 5 - 40 -----pF
PD
Capacitance (Notes 3, 4)
HCT TYPES
Propagation Delay
t
PLH,tPHLCL
= 50pF 4.5 - - 40 - 50 - 60 ns
(Figure 1)
CP to Q1’ Output CL=15pF 5 - 17 -----ns
6
CD74HC4040, CD74HCT4040
Switching Specifications Input t
, tf = 6ns (Continued)
r
TEST
PARAMETER SYMBOL
Qnto Qn+ 1 t
PLH,tPHLCL
CONDITIONS V
CC
(V)
= 50pF 4.5 - - 15 - 19 - 22 ns
CL=15pF 5 - 4 -----ns
MR to Q
n
t
PLH,tPHLCL
= 50pF 4.5 - - 40 - 50 - 60 ns
CL=15pF 5 - 17 -----ns
Output Transition t
TLH,tTHLCL
Input Capacitance C
Power Dissipation
IN
C
PD
= 50pF 4.5 - - 15 - 19 - 22 ns
CL=15pF - - - 10 - 10 - 10 pF
CL=15pF 5 - 45 -----pF
Capacitance (Notes 4, 5)
NOTES:
4. CPD is used to determine the dynamic power consumption, per package.
5. PD=V
CC
2
fi+ ∑ (CLV
2
fi/M) where:M=21,22,23, ...212,fi= Input Frequency, CL= Output Load Capacitance,VCC= Supply Voltage.
CC
Test Circuits and Waveforms
trC
L
CLOCK
10%
90%
50%
10%
tfC
t
WL
L
tWL+ tWH=
50%
t
WH
fC
50%
I
L
V
CC
GND
t
rCL
CLOCK
= 6ns
25oC
0.3V
2.7V
-40oC TO
85oC
= 6ns
t
fCL
1.3V
0.3V
t
WL
-55oC TO
125oC
1.3V
t
WH
t
WL
+ tWH=
1.3V
UNITSMIN TYP MAX MIN MAX MIN MAX
I
fC
L
3V
GND
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table.For f
, input duty cycle = 50%.
MAX
FIGURE 5. HC CLOCK PULSE RISE AND FALLTIMES AND
PULSE WIDTH
tr = 6ns tf = 6ns
V
t
TLH
CC
GND
INPUT
t
INVERTING
OUTPUT
THL
t
PHL
90%
50%
10%
t
PLH
90%
50%
10%
FIGURE 7. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table.For f
, input duty cycle = 50%.
MAX
FIGURE 6. HCT CLOCK PULSE RISE AND FALLTIMES AND
PULSE WIDTH
= 6ns
t
PLH
t
f
1.3V
10%
90%
t
TLH
3V
GND
tr = 6ns
INPUT
t
INVERTING
OUTPUT
THL
t
2.7V
1.3V
0.3V
PHL
FIGURE 8. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
7
CD74HC4040, CD74HCT4040
Test Circuits and Waveforms
90%
t
PLH
IC
t
TLH
tfC
L
50%
C
50pF
CLOCK
INPUT
DAT A
INPUT
t
SU(H)
OUTPUT
t
REM
V
CC
SET, RESET
OR PRESET
trC
L
90%
10%
t
H(H)
50%
(Continued)
t
H(L)
t
SU(L)
t
THL
90%
50%
10%
t
PHL
L
V
CC
GND
V
CC
50%
GND
GND
CLOCK
INPUT
DAT A
INPUT
t
SU(H)
OUTPUT
t
REM
3V
SET, RESET
OR PRESET
trC
90%
t
PLH
IC
1.3V
t
TLH
tfC
L
1.3V
t
H(L)
1.3V
t
SU(L)
t
THL
90%
1.3V
10%
t
PHL
C
L
50pF
3V
GND
3V
GND
GND
L
2.7V
0.3V
t
H(H)
1.3V
1.3V
1.3V
FIGURE 9. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 10. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
8
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