Texas Instruments CD74HC4017E, CD74HC4017PWR, CD74HC4017M96, CD74HC4017M Datasheet

Data sheet acquired from Harris Semiconductor

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SCHS200

November 1997

CD74HC4017

High Speed CMOS Logic

Decade Counter/Divider with 10 Decoded Outputs

[ /Title
(CD74
HC401

7)
Sub­ect

(High
Speed
CMOS
Logic
Decade
Counte

Features

• Fully Static Operation

• Buffered Inputs

• Common Reset

• Positive Edge Clocking

• Typical f

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

= 50MHz at VCC=5V,CL= 15pF, TA=25oC

MAX

o

= 30%, NIH = 30% of V

IL

C to 125oC

Description

The Harris CD74HC4017 is a high speed silicon gate CMOS
5-stage Johnson counter with 10 decoded outputs. Each of
the decoded outputs is normally low and sequentially goes
high on the low to high transition clock period of the 10 clock
period cycle. The CARRY (TC) output transitions low to high
after OUTPUT 10 goes low, and can be used in conjunction
with the CLOCK ENABLE (
The CLOCK ENABLE input disables counting when in the
high state. A RESET (MR) input is also provided which when
taken high sets all the decoded outputs, except “0”, low.

The device can drive up to 10 low power Schottky equivalent
loads.

CE) to cascade several stages.

Ordering Information

PART NUMBER TEMP. RANGE (oC) PACKAGE

CD74HC4017E -55 to 125 16 Ld PDIP E16.3

NOTES:

CC

1. When ordering,use the entire part number.Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer ordie forthis part numberis availablewhich meets all elec­trical specifications. Please contact your local sales office or
Harris customer service for ordering information.

PKG.

NO.

Pinout

CD74HC4017

(PDIP)

TOP VIEW

16

1

5

2

1

3

0

4

2

5

6

6

7

7

3

8

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

1

V

CC

MR

15
14

CP

13

CE

12

TC
9

11
10

4

9

8

File Number 1639.1

Functional Diagram

NOTE:
H = High Level
L = Low Level

↑ = High to Low Transition
↓ = Low to High Transition

X = Don’t Care.
† If n < 5 TC = H, Otherwise = L

CD74HC4017

3

0

CLOCK
CLOCK

ENABLE

MASTER

14

13

15

RESET

TRUTH TABLE

CP CE MR OUTPUT STATE †

L X L No Change
X H L No Change
X X H “0” = H, “1”-”9” = L

↑ L L Increments Counter
↓ X L No Change

X ↑ L No Change

H ↓ L Increments Counter

2
4
7
10
1
5
6
9
11
12

1
2
3
4
5
6
7

DECODED DECIMAL OUT

8
9

TERMINAL
COUNT

2

CD74HC4017

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

TEST

CONDITIONS

PARAMETER SYMBOL

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

V

IL

V

OH

CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage

V

OL

CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

I

I

I

CC

NOTE: For dual-supply systems theoretical worst case (V

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

- - 2 1.5 - - 1.5 - 1.5 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - - V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

VCC or

0 6 - - 8 - 80 - 160 µA

GND

o

C -40oC TO 85oC -55oC TO 125oC

V

CC

25

(V)

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

UNITSV

3

Prerequisite for Switching Specifications

TEST

PARAMETER SYMBOL

Maximum Clock
Frequency

CP Pulse Width t

MR Pulse Width t

Set-up Time,
CE to CP

Hold Time,
CE to CP

MR Removal Time t

f

MAX

t

SU

t

REM

W

W

H

CONDITIONS

- 26--5-4-MHz

- 2 80 - - 100 - 120 - ns

- 2 80 - - 100 - 120 - ns

- 2 75 - - 95 - 110 - ns

- 20--0-0-ns

- 25--5-5-ns

CD74HC4017

o

25

V

CC

(V)

4.5 30 - - 35 - 20 - MHz
6 35 - - 49 - 23 - MHz

4.5 16 - - 20 - 24 - ns
614- -17-20-ns

4.5 16 - - 20 - 24 - ns
614- -17-20-ns

4.5 15 - - 19 - 22 - ns
613- -16-19-ns

4.50--0-0-ns
60--0-0-ns

4.55--5-5-ns
65--5-5-ns

C -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Switching Specifications Input t

, tf = 6ns

r

-40oC TO

TEST

PARAMETER SYMBOL

Propagation Delay t

CP to any Dec. Out CL = 50pF 4.5 - - 46 - 58 - 69 ns

PLH,

t

PHL

CONDITIONS

CL = 50pF 2 - - 230 - 290 - 345 ns

V

CC

(V)

25oC

85oC -55oC TO 125oC

CL = 15pF 5 - 19 - - - - - ns
CL = 50pF 6 - - 39 - 49 - 59 ns

CP to TC t

PLH,

t

PHL

CL = 50pF 2 - - 230 - 290 - 345 ns
CL = 50pF 4.5 - - 46 - 58 - 69 ns
CL = 15pF 5 - 19 - - - - - ns
CL = 50pF 6 - - 39 - 49 - 59 ns

CE to any Dec. Out t

PLH,

t

PHL

CL = 50pF

- - 250 - 315 - 375 ns

2
CL = 50pF 4.5 - - 50 - 63 - 75 ns
CL = 15pF 5 - 21 - - - - - ns
CL = 50pF 6 - - 43 - 54 - 64 ns

CE to TC t

PLH,

t

PHL

CL = 50pF 2 - - 250 - 315 - 375 ns
CL = 50pF 4.5 - - 50 - 63 - 75 ns
CL = 15pF 5 - 21 - - - - - ns
CL = 50pF 6 - - 43 - 54 - 64 ns

UNITSMIN TYP MAX MIN MAX MIN MAX

4

CD74HC4017

Switching Specifications Input t

PARAMETER SYMBOL

MR to any Dec. Out t

, tf = 6ns (Continued)

r

TEST

CONDITIONS

PLH,

t

PHL

CL = 50pF 2 - - 230 - 290 - 345 ns
CL = 50pF 4.5 - - 46 - 58 - 69 ns

V

CC

(V)

CL = 15pF 5 - 19 - - - - - ns
CL = 50pF 6 - - 39 - 49 - 59 ns

MR to TC t

PLH,

t

PHL

CL = 50pF 2 - - 230 - 290 - 345 ns
CL = 50pF 4.5 - - 46 - 58 - 69 ns
CL = 15pF 5 - 19 - - - - - ns
CL = 50pF 6 - - 39 - 49 - 59 ns

Transition Time TC, Dec. Out t

TLH,tTHLCL

= 50pF 2 - - 75 - 95 - 110 ns
CL = 50pF 4.5 - - 15 - 19 - 22 ns
CL = 50pF 6 - - 13 - 16 - 19 ns

Input Capacitance C
Maximum CP Frequency f
Power Dissipation Capacitance

MAX

C

IN

PD

CL = 50pF - - - 10 - 10 - 10 pF
CL = 15pF 5 - 60 - - - - - MHz
CL = 15pF 5 - 39 - - - - - pF

(Notes 4, 5)

NOTES:

4. CPD is used to determine the dynamic power consumption, per package.

5. PD = V

CC

2

fiΣ CL V

2

fo where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage.

CC

25oC

-40oC TO
85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Test Circuits and Waveforms

fC

50%

I

L

V

CC

GND

+ tWH=

t

50%

WL

t

WH

trC

L

CLOCK

10%

90%

50%

10%

tfC

t

L

WL

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. Forf

, input duty cycle = 50%.

MAX

FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

tr = 6ns tf = 6ns

V

t

CC

GND

TLH

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

90%
50%
10%

t

90%

50%

10%

PLH

FIGURE 2. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

5

CD74HC4017

Test Circuits and Waveforms

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

OUTPUT

t

REM

V

CC

SET, RESET
OR PRESET

(Continued)

trC

L

10%

50%

90%

t

H(H)

90%

t

PLH

IC

t

TLH

tfC

L

50%

t

H(L)

t

SU(L)

t

THL

90%

50%

10%
t

PHL

C

L

50pF

V

CC

GND

V

CC

50%
GND

GND

FIGURE 3. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAYTIMES FOR EDGE TRIGGERED

SEQUENTIAL LOGIC CIRCUITS

Timing Diagrams

CLOCK

MASTER

RESET

CLOCK

C

L

D

C

C

C

L

R

P
N

L

C

PN

L

FF DETAIL

C

L

P
N

C

L

C

L

C

L

P
N

C

L

FIGURE 4. FIGURE 5.

ENABLE

“0”

0

“1”

Q

Q

“2”
“3”
“4”
“5”
“6”
“7”
“8”
“9”

TERMINAL

COUNT

1

2

3

4

5

6

7

0

8

9

1

2

6

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