Texas Instruments CD74HC4002PWR, CD74HC4002M96, CD74HC4002M, CD74HC4002E, CD54HC4002F3A Datasheet

Data sheet acquired from Harris Semiconductor

/

SCHS197

August 1997

CD74HC4002

High Speed CMOS Logic

Dual 4-Input NOR Gate

[ /Title
(CD74H
C4002)

Subject
(High
Speed
CMOS
Logic
Dual 4­Input
NOR
Gate)

Features

• Typical Propagation Delay = 8ns at VCC = 5V,
C

= 15pF, TA = 25oC

L

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

o

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High NoiseImmunity: N

V

= 5V

CC

= 30%, NIH= 30%of VCCat

IL

C to 125oC

Pinout

Description

The CD74HC4002 logic gate utilizes silicon gate CMOS
technology to achieve operating speeds similar to LSTTL
gates with the low power consumption of standard CMOS
integrated circuits. All devices have the ability to drive 10
LSTTL loads. The CD74HC4002 logic family is functional as
well as pin compatible with the standard 74LS logic family.

Ordering Information

PART NUMBER TEMP. RANGE (oC) PACKAGE

CD74HC4002E -55 to 125 14 Ld PDIP E14.3
CD74HC4002M -55 to 125 14 Ld SOIC M14.15

NOTES:

1. When ordering, use the entire part number.Add the suffix 96 to

2. Die for this part number is available which meets all electrical

CD74HC4002

(PDIP, SOIC)

TOP VIEW

PKG.

NO.

obtain the variant in the tape and reel.

specifications. Please contact your local sales office or Harris
customer service for ordering information.

1Y

1
2

1A

3

1B

4

1C

5

1D

6

NC

7

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

14

V

CC

2Y

13
12

2D

11

2C

10

2B

9

2A

8

NC

1

File Number 1776.1

Functional Diagram

CD74HC4002

2

1A

3

1B

4

1C

5

1D

9

2A

10

2B

11

2C

12

2D

TRUTH TABLE

INPUTS OUTPUT

nA nB nC nD nY

LLLLH

1

1Y

13

2Y

GND = 7

= 14

V

CC

NC = 6, 8

Logic Symbol

HXXXL
XHXXL
XXHXL
XXXHL

NOTE: H= High VoltageLevel,L = LowVoltageLevel,X = Irrelevant

nA
nB

nY

nC
nD

2

CD74HC4002

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

TEST

CONDITIONS

PARAMETER SYMBOL

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

V

IL

V

OH

CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage

V

OL

CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device

I

I

I

CC

Current (Note)

NOTE: For dual-supply systems theorectical worst case (V

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

- - 2 1.5 - - 1.5 - 1.5 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

VCC or

0 6 - - 2 - 20 - 40 µA

GND

o

25

V

CC

C -40oC TO 85oC -55oC TO 125oC

(V)

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

UNITSV

3

CD74HC4002

Switching Specifications Input t

, tf = 6ns

r

TEST

PARAMETER SYMBOL

CONDITIONS VCC (V)

HC TYPES

Propagation Delay,

t

PLH,tPHLCL

= 50pF 2 - 100 125 150 ns

nA, nB, nC, nD to nY

4.5 - 20 25 30 ns
6 - 17 21 26 ns

CL= 15pF 5 8 - - - ns

Output Transition Times

t

TLH

, t

THLCL

= 50pF 2 - 75 95 110 ns

(Figure 1)

4.5 - 15 19 22 ns
6 - 13 16 19 ns

Input Capacitance C
Power Dissipation

IN

C

PD

---1010 10pF

CL= 15pF 5 22 - - - pF

Capacitance

NOTES:

4. CPD is used to determine the dynamic power consumption, per gate.

5. PD = V

2

fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CC

25oC -40oC TO 85oC -55oC TO 125oC

UNITSTYP MAX MAX MAX

Test Circuit and Waveform

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC

tr = 6ns tf = 6ns

t

PHL

90%
50%
10%

t

90%

50%

10%

PLH

INPUT

t

INVERTING

OUTPUT

THL

t

TLH

V

CC

GND

4

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