Texas Instruments CD74HCT393M96, CD74HCT393M, CD74HCT393E, CD74HC393M96, CD74HC393M Datasheet

CD74HC393,

CD74

C393

D74
CT39

)
Sub­ect
High

peed

MOS

Data sheet acquired from Harris Semiconductor
SCHS186

September 1997

Features

• Fully Static Operation

• Buffered Inputs

• Common Reset

• Negative-Edge Clocking

• Typical f
T

= 25oC

A

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High NoiseImmunity: N

= 60 MHz at VCC = 5V, CL = 15pF,

MAX

= 30%, NIH= 30%of VCCat

IL

o

C to 125oC

CD74HCT393

High Speed CMOS Logic

Dual 4 -Stage Binary Counter

V

= 5V

CC

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,
V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

Description

The Harris CD74HC393 and CD74HCT393 are 4-stage
ripple-carry binary counters. Al counter stages are master­slave flip-flops. The state of the stage advances one count
on the negative transition of each clock pulse; a high voltage
level on the MR line resets all counters to their zero state. All
inputs and outputs are buffered.

Ordering Information

PART NUMBER TEMP. RANGE (oC) PACKAGE

CD74HC393E -55 to 125 14 Ld PDIP E14.3
CD74HCT393E -55 to 125 14 Ld PDIP E14.3

≤ 1µA at VOL, V

l

OH

PKG.

NO.

Pinout

CD74HC393, CD74HCT393

(PDIP, SOIC)

TOP VIEW

1CP

1MR

1Q0
1Q1
1Q2
1Q3

GND

1
2
3
4
5
6
7

14
13
12
11
10

9
8

V

CC

2CP
2MR
2Q0
2Q1
2Q2
2Q3

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

1

File Number 1653.1

Functional Diagram

CD74HC393, CD74HCT393

3

1Q

1

CP

1

1MR

CP

2

2MR

2

13

12

BINARY

COUNTER

BINARY

COUNTER

TRUTH TABLE

OUTPUTS

CP COUNT

Q

0

Q

1

0LLLL
1HLLL
2LHLL
3HHLL
4LLHL
5HLHL
6LHHL
7HHHL
8LLLH

9HLLH
10LHLH
11 H H L H
12 L L H H
13 H L H H
14LHHH
15HHHH

4

1Q

5

1Q

6

1Q

11

2Q

10

2Q

9

2Q

8

2Q

GND = 7
V

CC

= 14

Q

2

0

1

2

3

0

1

2

3

Q

3

CP COUNT MR OUTPUT

↑ L No Change
↓ L Count

X H L L L L

NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,
↑ = Transition from Low to High Level, ↓ = Transition from High to Low.

2

Logic Diagram

CD74HC393, CD74HCT393

CP

MR

1(13)

2(12)

Q

Φ

Q

Φ

R

3(11) 4(10) 5(9) 6(8)

Q

0

Q

ΦΦΦ

Q

ΦΦΦ

R R R

Q

1

Q

Q

Q

2

Q

Q

Q

3

3

CD74HC393, CD74HCT393

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

C -40oC TO 85oC -55oCTO125oC

25

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - - V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1µA

GND

VCC or

0 6 - - 8 - 80 - 160 µA

GND

4

CD74HC393, CD74HCT393

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

V

IL

V

OH

CMOS Loads
High Level Output

Voltage
TTL Loads

Low Level Output
Voltage

V

OL

CMOS Loads
Low Level Output

Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

I

I

CC

∆I

CC

Input Pin: 1 Unit Load

NOTE: For dual-supply systems theorectical worst case (V

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

- - 4.5 to

- - 4.5 to

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

4 4.5 - - 0.26 - 0.33 - 0.4 V

VCCand

0 5.5 - - ±0.1 - ±1-±1µA

GND

VCC or

0 5.5 - - 8 - 80 - 160 µA

GND

V

CC

- 4.5 to

-2.1

o

C -40oC TO 85oC -55oCTO125oC

V

CC

25

(V)

2--2- 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

- 100 360 - 450 - 490 µA

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

UNITSV

HCT Input Loading Table

INPUT UNIT LOADS

nCP 0.4
nMR 1

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Table,e.g.,
360µA max at 25oC.

Prerequisite for Switching Specifications

PARAMETER SYMBOL VCC (V)

HC TYPES

Maximum Clock
Frequency

Clock Pulse Width t

Reset Recovery Time t

f

MAX

REC

W

2 6--5-4-ns

4.5 30 - - 24 - 20 - ns
6 35- -28-24-ns
2 80 - - 100 - 120 - ns

4.5 16 - - 20 - 24 - ns
6 14- -17-20-ns
2 5--5-5-ns

4.55--5-5-ns
6 5--5-5-ns

o

25

C -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

5

CD74HC393, CD74HCT393

Prerequisite for Switching Specifications (Continued)

PARAMETER SYMBOL V

Reset Pulse Width t

HCT TYPES

Maximum Clock
Frequency

Clock Pulse Width t
Reset Recovery Time t
Reset Pulse Width t

f

MAX

REC

W

W

W

(V)

CC

2 80 - - 100 - 120 - ns

4.5 16 - - 20 - 24 - ns
6 14- -17-20-ns

4.5 27 - - 22 - 18 - MHz

4.5 19 - - 24 - 29 - ns

4.55--5-5-ns

4.5 16 - - 20 - 24 - ns

o

25

C -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Switching Specifications Input t

PARAMETER SYMBOL

, tf = 6ns

r

CONDITIONS

TEST

o

C -40oC TO 85oC -55oCTO125oC

V

CC

25

(V)

HC TYPES

Propagation Delay Time
(Figure 1)

to Qn + 1 4.5 - - 9 - 11 - 14 ns

Q

n

n

CP to nQ

CP to nQ

n

0

1

t

PLH,

t

PHL

t

PLH,

t

PHL

t

PLH,

t

PHL

CL= 50pF 2 - - 45 - 55 - 70 ns

=15pF 5 - 4 - - - - - ns

C

L

= 50pF 6 - - 8 - 9 - 12 ns

C

L

CL= 50pF 2 - - 150 - 190 - 225 ns

4.5 - - 30 - 38 - 59 ns

=15pF 5 - 12 - - - - - ns

C

L

C

= 50pF 6 - - 26 - 33 - 50 ns

L

CL= 50pF 2 - - 190 - 245 - 295 ns

4.5 - - 38 - 49 - 59 ns
6 - - 33 - 42 - 50 ns

CP to nQ

n

2

t

PLH,

t

PHL

CL= 50pF 2 - - 240 - 300 - 360 ns

4.5 - - 48 - 60 - 72 ns
6 - - 41 - 51 - 61 ns

CP to nQ

n

3

t

PLH,

t

PHL

CL= 50pF 2 - - 285 - 355 - 430 ns

4.5 - 57 - 71 - 86 ns
6 - - 48 - 60 - 73 ns

MR to Q

n

Output Transition Time
(Figure 1)

t

PLH,

t

t

TLH,tTHLCL

CL= 50pF 2 - - 135 - 170 - 205 ns

PHL

=15pF 5 - 11 - - - - - ns

C

L

= 50pF 6 - - 23 - 29 - 35 ns

C

L

4.5 - - 27 - 34 - 41 ns

= 50pF 2 - - 75 - 95 - 110 ns

4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns

Input Capacitance C
Power Dissipation Capacitance

C

CL= 50pF - - - 10 - 10 - 10 pF

IN

CL=15pF 5 - 20 - - - - - pF

PD

(Notes 4, 5)

UNITSMIN TYP MAX MIN MAX MIN MAX

6

CD74HC393, CD74HCT393

Switching Specifications Input t

PARAMETER SYMBOL

, tf = 6ns (Continued)

r

TEST

CONDITIONS

o

25

V

CC

C -40oC TO 85oC -55oCTO125oC

(V)

HCT TYPES

Propagation Delay Time
(Figure 1)

to Qn + 1 CL=15pF 5 - 4 - - - - - ns

Q

n

CP to nQ

n

CP to nQ

n

CP to nQ

n

CP to nQ

n

MR to Q

0

1

2

3

n

Output Transition t
Input Capacitance C
Power Dissipation Capacitance

t

PLH,

t

t

PLH,

t

t

PLH,

t

t

PLH,

t

t

PLH,

t

t

PLH,

t

TLH,tTHLCL

C

CL= 50pF 4.5 - - 12 - 15 - 18 ns

PHL

CL= 50pF 4.5 - - 32 - 40 - 48 ns

PHL

C
CL= 50pF 4.5 - - 44 - 55 - 66 ns

PHL

CL= 50pF 4.5 - - 50 - 63 - 75 ns

PHL

CL= 50pF 4.5 - - 62 - 78 - 93 ns

PHL

CL= 50pF 4.5 - - 32 - 40 - 48 ns

PHL

C

CL=15pF - - - 10 - 10 - 10 pF

IN

CL=15pF 5 - 21 - - - - - pF

PD

=15pF 5 - 13 - - - - - ns

L

=15pF 5 - 13 - - - - - ns

L

= 50pF 4.5 - - 15 - 19 - 22 ns

(Notes 4, 5)

NOTES:

is used to determine the dynamic power consumption, per stage.

4. C

PD

5. PD = V

2

fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CC

UNITSMIN TYP MAX MIN MAX MIN MAX

Test Circuits and Waveforms

tr = 6ns tf = 6ns

V

t

CC

GND

TLH

t

PHL

90%
50%
10%

t

PLH

90%

50%

10%

INPUT

t

INVERTING

OUTPUT

THL

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

= 6ns

t

PLH

t

f

1.3V

10%

90%

t

3V

GND

TLH

tr = 6ns

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

2.7V

1.3V

0.3V

FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

7

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