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CD74HC377M
Datasheet
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Texas Instruments CD74HCT377M, CD74HCT377E, CD74HC377M96, CD74HC377M, CD74HC377E Datasheet

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CD74HC377,
/ j
[ /Title (CD74 HC377 , CD74 HCT37
7) Sub­ect
(High Speed CMOS Logic Octal D­Type Flip-
Data sheet acquired from Harris Semiconductor SCHS184
September 1997
Features
• Buffered Common Clock
• Buffered Inputs
• Typical Propagation Delay = 17ns at C V
= 5V, TA = 25oC
CC
L
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
- 2V to 6V Operation
- High NoiseImmunity: N
= 30%, NIH= 30%of VCCat
IL
Pinout
Octal D-Type Flip-Flop with Data Enable
V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, V
IL
- CMOS Input Compatibility, I
Description
The Harris CD74HC377 and CD74HCT377 are octal D-type
C to 125oC
CD74HC377, CD74HCT377
flip-flops with a buffered clock (CP) common to all eight flip­flops. All the flip-flops are loaded simultaneously on the positive edge of the clock (CP) when the Data Enable ( Low.
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE
CD74HC377E -55 to 125 20 Ld PDIP E20.3
(PDIP, SOIC)
TOP VIEW
CD74HCT377
High Speed CMOS Logic
= 5V
= 0.8V (Max), VIH = 2V (Min)
l
≤ 1µA at VOL, V
OH
E) is
PKG.
NO.
Q D D Q Q D D Q
GND
1
E
2
0
3
0
4
1
5
1
6
2
7
2
8
3
9
3
10
V
20
CC
Q
19
7
D
18
7
D
17
6
Q
16
6
Q
15
5
D
14
5
D
13
4
12
Q
4
11
CP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© Harris Corporation 1997
1
File Number 1675.1
Functional Diagram
CD74HC377, CD74HCT377
3
D
0
4
D
1
7
D
2
8
D
3
13
D
4
14
D
5
17
D
6
18
D
7
CP
E
11 1
2
Q
5
Q
6
Q
9
Q
12
Q
15
Q
16
Q
19
Q
GND = 10 V
= 20
CC
0
1
2
3
4
5
6
7
TRUTH TABLE
INPUTS OUPUTS
OPERATING MODE
CP
ED
n
Q
n
Load “1” ↑ lh H Load “0” ↑ ll L Hold (Do Nothing) ↑ h X No Change
X H X No Change
NOTES: H = High Voltage Level Steady State. h = High Voltage Level One Set-up Time Prior to the Low to High Clock Transition. L = Low Voltage Level Steady State. l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition. X = Don’t Care. ↑ = Low to High Clock Transition.
Logic Diagram
E
CP
D
0
CP
D
1
QD
Q
0
CP
D
2
QD
Q
1
CP
D
3
QD
Q
2
CP
D
4
QD
Q
3
CP
D
5
QD
Q
4
CP
D
6
QD
Q
5
CP
D
7
QD
Q
QD
CP
6
Q
7
2
CD74HC377, CD74HCT377
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I
O
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, I
CC orIGND
. . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, V
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
CC
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CC
DC Electrical Specifications
PARAMETER SYMBOL
HC TYPES
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage CMOS Loads
High Level Output Voltage TTL Loads
Low Level Output Voltage CMOS Loads
Low Level Output Voltage TTL Loads
Input Leakage Current
Quiescent Device Current
V
IH
V
IL
V
OH
V
OL
I
I
I
CC
TEST
CONDITIONS
(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
I
V
CC
(V)
o
C -40oC TO 85oC -55oCTO125oC
25
UNITSV
- - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V
- - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V
VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
- - ---- - - - V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
- - ---- - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
VCC or
-6--±0.1 - ±1-±1µA
GND
VCC or
0 6 - - 8 - 80 - 160 µA
GND
3
CD74HC377, CD74HCT377
DC Electrical Specifications (Continued)
TEST
CONDITIONS
PARAMETER SYMBOL
HCT TYPES
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
V
IH
V
IL
V
OH
CMOS Loads High Level Output
Voltage TTL Loads
Low Level Output Voltage
V
OL
CMOS Loads Low Level Output
Voltage TTL Loads
Input Leakage Current
Quiescent Device Current
Additional Quiescent Device Current Per
I
I
I
CC
∆I
CC
Input Pin: 1 Unit Load
NOTE: For dual-supply systems theoretical worst case (V
(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
I
- - 4.5 to
- - 4.5 to
VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-4 4.5 3.98 - - 3.84 - 3.7 - V
VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V
4 4.5 - - 0.26 - 0.33 - 0.4 V
VCCand
0 5.5 - - ±0.1 - ±1-±1µA
GND
VCC or
0 5.5 - - 8 - 80 - 160 µA
GND
V
CC
- 4.5 to
-2.1
o
C -40oC TO 85oC -55oCTO125oC
V
CC
25
(V)
2--2- 2 - V
5.5
- - 0.8 - 0.8 - 0.8 V
5.5
- 100 360 - 450 - 490 µA
5.5
= 2.4V, VCC = 5.5V) specification is 1.8mA.
I
UNITSV
HCT Input Loading Table
INPUT UNIT LOADS
E 1.5
CP 0.5
All Dn Inputs 0.25
NOTE: Unit Load is ∆ICClimit specified in DC Electrical Table,e.g., 360µA max at 25oC.
Prerequisite for Switching Specifications
PARAMETER SYMBOL
HC TYPES
Maximum Clock Frequency
Clock Pulse Width t
f
MAX
W
TEST
CONDITIONS
- 26--5-4-MHz
- 2 80 - - 100 - 120 - ns
V
CC
(V)
4.5 30 - - 25 - 20 - MHz 6 35 - - 29 - 23 - MHz
4.5 16 - - 20 - 24 - ns 614- -17-20-ns
o
25
C -40oC TO 85oC -55oCTO125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
4
CD74HC377, CD74HCT377
Prerequisite for Switching Specifications (Continued)
PARAMETER SYMBOL
Set-up Time, E, Data to CP
Hold Time, Data to CP
Hold Time, E to CP
HCT TYPES
Maximum Clock Frequency
Clock Pulse Width t Set-up, Time
E, Data to CP Hold Time,
Data to CP Hold Time,
E to CP
t
SU
t
t
f
MAX
t
SU
t
t
H
H
W
H
H
TEST
CONDITIONS
- 2 60 - - 75 - 90 - ns
- 23--3-3-ns
- 25--5-5-ns
- 4.5 25 - - 20 - 16 - MHz
- 4.5 20 - - 25 - 30 - ns
- 4.5 12 - - 15 - 18 - ns
- 4.53--3-3-ns
- 4.55--5-5-ns
V
CC
(V)
4.5 12 - - 15 - 18 - ns 610- -13-15-ns
4.53--3-3-ns 63--3-3-ns
4.55--5-5-ns 65--5-5-ns
o
25
C -40oC TO 85oC -55oCTO125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
Switching Specifications Input t
PARAMETER SYMBOL
, tf = 6ns
r
TEST
CONDITIONS
o
C
V
CC
25
-40oC TO 85oC -55oC TO 125oC
(V)
HC TYPES
Propagation Delay (Figure 1) t
CP to Q 4.5 - - 35 - 44 - 53 ns
Output Transition Time (Figure 1)
PLH,
t
PHL
t
TLH,tTHLCL
CL= 50pF 2 - - 175 - 220 - 265 ns
C
=15pF 5 - 14 - - - - - ns
L
C
= 50pF 6 - - 30 - 37 - 45 ns
L
= 50pF 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns
Input Capacitance C Maximum Clock Frequency f Power Dissipation Capacitance
(Notes 4, 5)
MAXCL
C
CL= 50pF - - - 10 - 10 - 10 pF
IN
=15pF 5 - 60 - - - - - MHz
CL=15pF 5 - 31 - - - - - pF
PD
HCT TYPES
Propagation Delay (Figure 1) t
CP to Q C
Output Transition Time (Figure 1)
PLH,
t
PHL
t
TLH,tTHLCL
Input Capacitance C
CL= 50pF 4.5 - - 38 - 48 - 57 ns
=15pF 5 - 16 - - - - - ns
L
= 50pF 4.5 - - 15 - 19 - 22 ns
CL= 50pF - - - 10 - 10 - 10 pF
IN
UNITSMIN TYP MAX MIN MAX MIN MAX
5
CD74HC377, CD74HCT377
Switching Specifications Input t
, tf = 6ns (Continued)
r
PARAMETER SYMBOL
Maximum Clock Frequency f Power Dissipation Capacitance
(Notes 4, 5)
MAXCL
C
PD
NOTES:
is used to determine the dynamic power consumption, per flip-flop.
4. C
PD
5. PD = V
2
fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
CC
Test Circuits and Waveforms
tfC
L
50%
CLOCK
INPUT
DAT A
INPUT
t
SU(H)
trC
L
90%
10%
t
H(H)
-40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
TEST
CONDITIONS
o
C
V
CC
25
(V)
=15pF 5 - 50 - - - - - MHz
CL=15pF 5 - 35 - - - - - pF
t
H(L)
t
SU(L)
V
CC
GND
V
CC
50% GND
CLOCK
INPUT
DAT A
INPUT
t
SU(H)
trC
L
2.7V
0.3V
t
H(H)
1.3V
1.3V
tfC
L
1.3V
t
H(L)
1.3V
t
SU(L)
3V
GND
3V
GND
OUTPUT
t
REM
V
CC
SET, RESET OR PRESET
50%
90%
t
PLH
IC
t
TLH
C
L
50pF
90%
50%
10% t
PHL
t
THL
GND
FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVALTIME,
AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS
OUTPUT
t
REM
3V SET, RESET OR PRESET
1.3V
90%
1.3V t
IC
t
PLH
TLH
C
L
50pF
90%
1.3V 10%
t
t
PHL
THL
GND
FIGURE 2. HCT SETUP TIMES, HOLD TIMES, REMOVALTIME,
AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS
6
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