Texas Instruments CD74HCT126M96, CD74HCT126M, CD74HCT126E, CD74HC126M96, CD74HC126M Datasheet

CD74HC126,

/
j

[ /Title
(CD74
HC126
,
CD74
HCT12

6)
Sub­ect

(High
Speed
CMOS
Logic
Quad
Buffer,
Three­State)

Data sheet acquired from Harris Semiconductor
SCHS144

November 1997

Features

• Three-State Outputs

• Separate Output Enable Inputs

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

o

C to 125oC

CC

OH

CD74HCT126

High Speed CMOS Logic
Quad Buffer, Three-State

Description

The Harris CD74HC126 and CD74HCT126 contain four
independent three-state buffers, each having its own output
enable input, which when “low” puts the output in the high­impedance state.

Ordering Information

TEMP.RANGE

PART NUMBER

CD74HC126E -55 to 125 14 Ld PDIP E14.3
CD74HCT126E -55 to 125 14 Ld PDIP E14.3
CD74HC126M -55 to 125 14 Ld SOIC M14.15
CD74HCT126M -55 to 125 14 Ld SOIC M14.15

NOTES:

1. When ordering, use the entire part number.Add thesuffix 96to
obtain the variant in the tape and reel.

2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact yourlocal salesoffice or
Harris customer service for ordering information.

(oC) PACKAGE

PKG.

NO.

Pinout

CD74HC126, CD74HC126

(PDIP, SOIC)

TOP VIEW

1OE

1
2

1A
1Y

3

2OE

4

2A

5

2Y

6

GND

7

V

14

CC

4OE

13

4A

12

4Y

11

3OE

10

3A

9

3Y

8

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

1

File Number 1772.1

Functional Diagram

1

1OE

2

1A

4

2OE

5

2A

10

3OE

9

3A

13

4OE

12

4A

TRUTH TABLE

INPUTS OUTPUTS

nA nOE nY

CD74HC126, CD74HCT126

3

1Y

6

2Y

8

3Y

11

4Y

GND = 7

= 14

V

CC

HHH

LHL

XLZ

NOTE:
H = High Voltage Level
L = Low Voltage Level
X = Don’t Care
Z = High Impedance, OFF State

Logic Diagram

nA

nOE

P

nY

n

2

CD74HC126, CD74HCT126

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±70mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

VCC (V)

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

-6 4.5 3.98 - - 3.84 - 3.7 - V

-7.8 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V
6 4.5 - - 0.26 - 0.33 - 0.4 V

7.8 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1µA

GND

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

3

CD74HC126, CD74HCT126

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device
Current

Three-State Leakage
Current

I

I

CC

OZ

VCC or

GND

VIL or

V

IH

V

(V)

CC

0 6 - - 8 - 80 - 160 µA

-6--±0.5 - ±5-±10 µA

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

- - 4.5 to

5.5

V

IL

- - 4.5 to

5.5

V

OH

VIH or

V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

CMOS Loads
High Level Output

-6 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads

Low Level Output
Voltage

V

OL

VIH or

V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

CMOS Loads
Low Level Output

6 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

VCC to

I

0 5.5 - - ±0.1 - ±1-±1µA

GND

I

CC

VCC or

0 5.5 - - 8 - 80 - 160 µA

GND

∆I

CC

V

-2.1

CC

- 4.5 to

5.5
Input Pin: 1 Unit Load
(Note 4)

Three-State Leakage
Current

I

OZ

VIL or

V

IH

- 5.5 - - ±0.5 - ±5-±10 µA

NOTE:

4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

25oC -40oC TO 85oC -55oC TO 125oC

2-- 2 - 2 - V

- - 0.8 - 0.8 - 0.8 V

- 100 360 - 450 - 490 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

nA, nOE 1

NOTE: Unit Load is ∆ICClimit specified in DC Electrical
Specifications table, e.g., 360µA max at 25oC.

4

CD74HC126, CD74HCT126

Switching Specifications Input t

, tf = 6ns

r

TEST

PARAMETER SYMBOL

CONDITIONS V

CC

(V)

HC TYPES

Propagation Delay Data
to Outputs

t

PLH

, t

PHLCL

= 50pF 2 - 100 125 150 ns

4.5 - 20 25 30 ns
CL= 15pF 5 8 - - - ns
CL = 50pF 6 - 17 21 36 ns

Enable Delay Time t

PZL,tPZHCL

= 50pF 2 - 125 155 190 ns

4.5 - 25 31 38 ns
CL= 15pF 5 10 - - - ns
CL = 50pF 6 - 21 26 32 ns

Disabling Delay Time t

PLZ

, t

CL = 50pF 2 - 125 155 190 ns

PHZ

CL= 50pF 4.5 - 25 31 38 ns
CL= 15pF 5 10 - - - ns
CL = 50pF 6 - 21 26 32 ns

Output Transition Times t

TLH

, t

THLCL

= 50pF 2 - 60 75 90 ns

4.5 - 12 15 18 ns

6 - 10 13 15 ns
Input Capacitance C
Three-State Output

I

C

O

---1010 10pF

---2020 20pF

Capacitance
Power Dissipation

C

PD

- 5 30 - - - pF
Capacitance
(Notes 5, 6)

HCT TYPES

Propagation Delay Time
to Outputs

Output Enable Time t

t

, t

PLH

PHLCL

PZL,tPZHCL

= 50pF 4.5 - 24 30 36 ns

CL= 15pF 5 9 - - - ns

= 50pF 4.5 - 25 31 38 ns

CL= 15pF 5 10 - - - ns

Output Disabling Time t

PLZ

, t

PHZCL

= 50pF 4.5 - 28 35 42 ns

CL= 15pF 5 11 - - - ns
Output Transition Times t
Input Capacitance C
Three-State Output

TLH

, t

THLCL

I

C

O

= 50pF 4.5 - 12 15 18 ns

---1010 10pF

---2020 20pF

Capacitance
Power Dissipation

C

PD

- 5 36 - - - pF
Capacitance
(Notes 5, 6)

NOTES:

5. CPD is used to determine the dynamic power consumption, per multiplexer.

6. PD = V

2

fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CC

25oC -40oC TO 85oC -55oCTO125oC

UNITSTYP MAX MAX MAX

5

Test Circuits and Waveforms

tr = 6ns tf = 6ns

INPUT

90%
50%
10%

CD74HC126, CD74HCT126

tr = 6ns

V

CC

GND

INPUT

2.7V

1.3V

0.3V

= 6ns

t

f

3V

GND

INVERTING

OUTPUT

t

THL

t

PHL

t

PLH

50%

10%

90%

t

TLH

FIGURE 6. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

6ns 6ns

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

50%

t

t

OUTPUTS
ENABLED

PLZ

PHZ

10%

90%

90%

10%

t

PZL

t

PZH

OUTPUTS

DISABLED

50%

50%

FIGURE 8. HC THREE-STATE PROPAGATION DELAY

WAVEFORM

V

CC

GND

OUTPUTS
ENABLED

t

INVERTING

OUTPUT

THL

t

PHL

t

PLH

1.3V

10%

90%

t

TLH

FIGURE 7. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

0.3

t

t

6ns

PZL

1.3V

PZH

1.3V
OUTPUTS

ENABLED

t

r

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

t

t

OUTPUTS
ENABLED

6ns t

PLZ

PHZ

10%

90%

f

2.7

1.3

OUTPUTS

DISABLED

FIGURE 9. HCT THREE-STATE PROPAGATION DELAY

WAVEFORM

3V

GND

NOTE: Open drain waveforms t
VCC, CL = 50pF.

FIGURE 10. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

TIED HIGH

OR LOW

and t

PLZ

OTHER

INPUTS

OUTPUT

DISABLE

PZL

IC WITH

THREE-

STATE

OUTPUT

are the same as those for three-state shown on the left. The test circuit is Output RL=1kΩto

OUTPUT

= 1kΩ

R

L

C

L

50pF

VCC FOR t
GND FOR t

PLZ

PHZ

AND t

AND t

PZL

PZH

6

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