Texas Instruments CD 74 HC 109 INSTALLATION INSTRUCTIONS

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Data sheet acquired from Harris Semiconductor

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SCHS140E

March 1998 - Revised October 2003

CD54HC109, CD74HC109,

CD54HCT109, CD74HCT109

Dual J-K Flip-Flop with Set and Reset

Positive-Edge Trigger

/Title
CD74H

109,
D74H

T109)
Subject
Dual J-

Flip-

lop

ith Set

nd

eset

Features

• Asynchronous Set and Reset

• Schmitt Trigger Clock Inputs

• Typical f
T

= 25oC

A

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 54MHz at VCC = 5V, CL = 15pF,

MAX

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

o

C to 125oC

OH

Pinout

CD54HC109, CD54HCT109

(CERDIP)

CD74HC109, CD74HCT109

(PDIP, SOIC)

TOP VIEW

Description

The ’HC109 and ’HCT109 are dual J-K flip-flops with set and
reset. The flip-flop changes state with the positive transition
of Clock (1CP and 2CP).

The flip-flop is set and reset by active-low
respectively. A low on both the set and reset inputs
simultaneously will force both Q and
However, both set and reset going high simultaneously
results in an unpredictable output condition.

Q outputs high.

Ordering Information

TEMP. RANGE

PART NUMBER

CD54HC109F3A -55 to 125 16 Ld CERDIP
CD54HCT109F3A -55 to 125 16 Ld CERDIP
CD74HC109E -55 to 125 16 Ld PDIP

CC

CD74HC109M -55 to 125 16 Ld SOIC
CD74HC109MT -55 to 125 16 Ld SOIC
CD74HC109M96 -55 to 125 16 Ld SOIC
CD74HCT109E -55 to 125 16 Ld PDIP
CD74HCT109M -55 to 125 16 Ld SOIC
CD74HCT109MT -55 to 125 16 Ld SOIC
CD74HCT109M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of

250.

(oC) PACKAGE

S and R,

16

1

1R

2

1J

3

1K

4

1CP

5

1S

6

1Q

7

1Q

8

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© 2003, Texas Instruments Incorporated

V

CC

15

2R

14

2J

13

2K
2CP

12
11

2S

10

2Q

9

2Q

1

CD54HC109, CD74HC109, CD54HCT109, CD74HCT109

Functional Diagram

1S

5

1K

1CP

1R

2S

2K

2CP

2R

2

1J

3

4
1

11

14

2J

13

12

15

F/F 1

F/F 2

6

1Q

7

1

Q

10

2Q

9

Q

2

GND = 8
V

= 16

CC

TRUTH TABLE

INPUTS OUTPUTS

S RCPJ KQQ

LHXXXHL
H
L
H
H

L
L
H
H

XXXLH
X X X H (Note 1) H (Note 1)

↑ LLLH
↑ H L Toggle

HH↑ L H No Change
HH↑ HHHL
H H L X X No Change

H= High Level (Steady State)
L= Low Level (Steady State)
X= Don’t Care

↑= Low-to-High Transition

NOTE:

1. Unpredictable and unstable condition if both S and R go high simultaneously

Logic Diagram

CP

V

CC

GND

5(11)
S

2(14)
J

3(13)
K

4(12)

1(15)
R

16

S

J

FF

K

CL

CL R

8

Q

Q

6(10)

Q

7(9)

Q

2

CD54HC109, CD74HC109, CD54HCT109, CD74HCT109

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

CP Input Rise and Fall Time, tr, t

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)

Input Rise and Fall Time (All Inputs Except CP), tr, t

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

2. The package thermal impedance is calculated in accordance with JESD 51-7

CC

f

f

Thermal Resistance (Typical, Note 2) θJA (oC/W)

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73

Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

V

IH

V

IL

V

OH

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

VCC (V)

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

4.5 4.4 - - 4.4 - 4.4 - V
6 5.9 - - 5.9 - 5.9 - V

---------V

-4 4.5 3.96 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

3

CD54HC109, CD74HC109, CD54HCT109, CD74HCT109

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Low Level Output
Voltage
CMOS Loads

V

OL

VIH or

V

IL

VCC (V)

0.02 2 - - 0.1 - 0.1 - 0.1 V

4.5 - - 0.1 - 0.1 - 0.1 V
6 - - 0.1 - 0.1 - 0.1 V

Low Level Output
Voltage
TTL Loads

---------V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

Input Leakage
Current

Quiescent Device
Current

I

I

CC

VCC or

I

-6--±0.1 - ±1-±1 µA

GND

VCC or

0 6 - - 4 - 40 - 80 µA

GND

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

- - 4.5 to

5.5

V

IL

- - 4.5 to

5.5

V

OH

VIH or

V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

CMOS Loads
High Level Output

-4 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads

Low Level Output
Voltage CMOS Loads

Low Level Output

V

OL

VIH or

V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

4 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads

Input Leakage
Current

I

I

V

CC

- 5.5 - ±0.1 - ±1-±1 µA

and

GND

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

CC

∆I

CC

(Note 3)

VCC or

GND

V

CC

- 2.1

0 5.5 - - 4 - 40 - 80 µA

- 4.5 to

5.5

Input Pin: 1 Unit Load

NOTE:

3. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

25oC -40oC TO 85oC -55oC TO 125oC

2-- 2 - 2 - V

- - 0.8 - 0.8 - 0.8 V

- 100 360 - 450 - 490 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

All 0.3

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Specifica­tions table, e.g., 360µA max at 25oC.

4