Texas Instruments CD74HCT03M96, CD74HCT03M, CD74HCT03E, CD74HC03M96, CD74HC03M Datasheet

CD74HC03,

/

[ /Title
(CD74H
C03,
CD74H
CT03)

Subject
(High
Speed
CMOS
Logic
Quad 2­Input

Data sheet acquired from Harris Semiconductor
SCHS126

February 1998

Features

• Buffered Inputs

• Typical Propagation Delay: 8ns at V
C

= 15pF, TA = 25oC

L

• Output Pull-up to 10V

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

CC

= 5V,

o

Quad 2-Input NAND Gate with Open Drain

C to 125oC

CC

OH

CD74HCT03

High Speed CMOS Logic

Description

The Harris CD74HC03 and CD74HCT03 logic gates utilize
silicon gate CMOS technology to achieve operating speeds
similar to LSTTL gates with the low power consumption of
standard CMOS integrated circuits. Alldevices havethe abil­ity to drive 10 LSTTL loads. The 74HCT logic family is func­tionally as well as pin compatible with the standard 74LS
logic family.

These open drain NAND gates can drive into resistive loads
to output voltages as high as 10V. Minimum values of R
required verses load voltage are shown in Figure 2.

Ordering Information

TEMP.RANGE

PART NUMBER

CD74HC03E -55 to 125 14 Ld PDIP E14.3
CD74HCT03E -55 to 125 14 Ld PDIP E14.3
CD74HC03M -55 to 125 14 Ld SOIC M14.15
CD74HCT03M -55 to 125 14 Ld SOIC M14.15

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact yourlocal salesoffice or
Harris customer service for ordering information.

(oC) PACKAGE

PKG.

NO.

L

Pinout

CD74HC03, CD74HCT03

(PDIP, SOIC)

TOP VIEW

1A

1
2

1B

3

1Y

4

2A

5

2B

6

2Y

7

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

14

V

CC

4B

13
12

4A
4Y

11

3B

10

3A

9

3Y

8

1

File Number 1832.1

Functional Diagram

CD74HC03, CD74HCT03

1

1A

2

1B

4

2A

5

2B

9

3A

10

3B

12

4A

13

4B

AB Y

L L Z (Note 4) H (Note 3)
H L Z (Note 4) H (Note 3)
L H Z (Note 4) H (Note 3)
HHLL

NOTES:

3. Requires pull-up (RL to VL)

4. Without pull-up (high impedance)

TRUTH TABLE

3

6

8

11

GND = 7
V

CC

1Y

2Y

3Y

4Y

= 14

Logic Symbol

nA

nB

nY

2

CD74HC03, CD74HCT03

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC Drain Current, per Output, I

O

For -0.5V < VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

5. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 5) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Maximum Junction Temperature (Hermetic P ac kage or Die) . . . 175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

V

V

I

V

V

CC

V

IH

IL

OL

I

IH

IL

I

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

VCC (V)

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

---------V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

VCC or

0 6 - - 2 - 20 - 40 µA

GND

- - 4.5 to

2-- 2 - 2 - V

5.5

- - 4.5 to

- - 0.8 - 0.8 - 0.8 V

5.5

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

3

CD74HC03, CD74HCT03

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Low Level Output
Voltage CMOS Loads

Low Level Output

V

OL

VIH or

V

IL

VCC (V)

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

4.5 - - 0.26 - 0.33 - 0.4 V

Voltage
TTL Loads

Input Leakage
Current

I

I

V

CC

4 5.5 - ±0.1 - ±1-±1 µA

and

GND

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

CC

∆I

CC

(Note 6)

VCC or

GND

V

CC

- 2.1

0 5.5 - - 2 - 20 - 40 µA

- 4.5 to

5.5

Input Pin: 1 Unit Load

NOTE:

6. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

HCT Input Loading Table

25oC -40oC TO 85oC -55oC TO 125oC

- 100 360 - 450 - 490 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

INPUT UNIT LOADS

nA, nB 1

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Specifica­tions table, e.g., 360µA max at 25oC.

Switching Specifications Input t

, tf = 6ns

r

TEST

PARAMETER SYMBOL

CONDITIONS

HC TYPES

Propagation Delay,

t

PLH

, t

PHLCL

= 50pF 2 - - 100 - 125 - 150 ns

Input to Output (Figure 1)

PropagationDelay,DataInputto

t

PLH

, t

PHLCL

= 15pF 5 - 8 - ----ns

Output Y
Transition Times (Figure 1) t

Input Capacitance C
Power Dissipation Capacitance

TLH

, t

I

C

PD

THLCL

= 50pF 2 - - 75 - 95 18 110 ns

- - - - 10 - 10 - 10 pF

- 5-6.4-----pF

(Notes 7, 8)

HCT TYPES

Propagation Delay,

t

PLH

, t

PHLCL

= 50pF 4.5 - - 24 - 30 - 36 ns

Input to Output (Figure 1)
PropagationDelay,DataInputto

t

PLH

, t

PHLCL

= 15pF 5 - 9 - ----ns

Output Y
Transition Times (Figure 1) t
Input Capacitance C

TLH

, t

THLCL

I

= 50pF 4.5 - - 15 - 19 - 22 ns

- - - - 10 - 10 - 10 pF

V

CC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

4.5 - - 20 - 25 - 30 ns
6 - - 17 - 21 - 26 ns

4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns

4

CD74HC03, CD74HCT03

Switching Specifications Input t

PARAMETER SYMBOL

Power Dissipation Capacitance

, tf = 6ns (Continued)

r

TEST

CONDITIONS

C

PD

- 5-9-----pF

V

CC

25oC -40oC TO 85oC -55oC TO 125oC

(V)

(Notes 7, 8)

NOTES:

7. CPD is used to determine the dynamic power consumption, per gate.

8. PD = CPD V

2

fi + Σ (CL V

CC

2

fo) + Σ (V

CC

2

/RL) (Duty Factor “Low”)

L

where fi= input frequency, fo= output frequency, CL= output load capacitance, VCC= supply voltage, Duty Factor “Low” = percent of
time output is “low”, VL = output voltage, RL = pull-up resistor.

Test Circuits and Waveforms

INPUT LEVEL

t

THL

90%
10%

V

S

t

PZL

V

OH

V

OL

OUTPUT
LOW

1kΩ

50pF

V

CC

t

PLZ

nY

OUTPUT

nA(nB)

nB(nA)

LOW

V

S

OUTPUT

OFF

OPEN
DRAIN
NAND
GATE

V

CC

FIGURE 1. TRANSITION TIMES, PROPAGATION DELAY

TIMES, AND TEST CIRCUIT

800

V

L

700

600

500

400

300

200

MIN, PULLUP RESISTOR (Ω)

L

R

100

R

R

VCC = 5V

HC/HCT03

012345678910

L

V

ON

±10%

O

≤ 1.35V (HC V

R

ON

0.8V (HCT VIL MAX)

MAX =

V

L

V

L

MAX)

IL

0.26V
4mA

65Ω AT 25oC

R

L

V

O

, LOAD VOLTAGE (V)

=

HCT

HC

FIGURE 2. MINIMUM RESISTIVE LOAD vs LOAD VOLTAGE

UNITSMIN TYP MAX MIN MAX MIN MAX

tr = 6ns tf = 6ns

V

t

CC

GND

TLH

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

90%
50%
10%

t

90%

50%

10%

PLH

FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

= 6ns

t

PLH

t

f

1.3V

10%

90%

t

3V

GND

TLH

tr = 6ns

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

2.7V

1.3V

0.3V

FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

5

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