AC Types Feature 1.5-V to 5.5-V Operation
and Balanced Noise Immunity at 30% of the
Supply
D
Buffered Inputs
D
Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
D
Balanced Propagation Delays
D
±24-mA Output Drive Current
– Fanout to 15 F Devices
D
SCR-Latchup-Resistant CMOS Process and
CD54AC32 ...F PACKAGE
CD74AC32 ...E OR M PACKAGE
1A
1B
1Y
2A
2B
2Y
GND
(TOP VIEW)
1
14
2
13
3
12
4
11
5
10
6
7
9
8
V
4B
4A
4Y
3B
3A
3Y
CC
Circuit Design
D
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
description/ordering information
The ’AC32 devices are quadruple 2-input positive-OR gates. These devices perform the Boolean function
Y+A
• B or Y+A)B in positive logic.
ORDERING INFORMA TION
T
A
PDIP – ETubeCD74AC32ECD74AC32E
–
CDIP – FTubeCD54AC32F3ACD54AC32F3A
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
PACKAGE
–
†
TubeCD74AC32M
Tape and reelCD74AC32M96
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
FUNCTION TABLE
(each gate)
INPUTS
AB
HXH
XHH
LLL
OUTPUT
Y
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
CD54AC32, CD74AC32
∆t/∆v
Input transition rise or fall rate
ns/V
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCHS343 – MARCH 2003
logic diagram (positive logic)
A
B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage1.55.51.55.51.55.5V
CC
VCC = 1.5 V1.21.21.2
High-level input voltage
IH
Low-level input voltage
IL
Input voltage0V
I
Output voltage0V
O
High-level output currentVCC = 4.5 V to 5.5 V–24–24–24mA
Low-level output currentVCC = 4.5 V to 5.5 V242424mA
p
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
VCC = 3 V
VCC = 5.5 V3.853.853.85
VCC = 1.5 V0.30.30.3
VCC = 3 V
VCC = 5.5 V1.651.651.65
VCC = 1.5 V to 3 V505050
VCC = 3.6 V to 5.5 V202020
2.12.12.1
–55°C to
125°C
0.90.90.9
CC
CC
0V
0V
CC
CC
–40°C to
85°C
0V
0V
CC
CC
UNIT
V
V
V
V
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CC
(INPUT)
(OUTPUT)
A or B
Y
ns
(INPUT)
(OUTPUT)
A or B
Y
ns
CD54AC32, CD74AC32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCHS343 – MARCH 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETERTEST CONDITIONSV
1.5 V1.41.41.4
IOH = –50 µA
V
OH
V
OL
I
I
I
CC
C
†
i
T est one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize
power dissipation. T est verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
VI = VIH or V
VI = VIH or V
VI = VCC or GND5.5 V±0.1±1±1µA
VI = VCC or GND,IO = 05.5 V48040µA
IL
IL
IOH = –4 mA3 V2.582.42.48
IOH = –24 mA4.5 V3.943.73.8
IOH = –50 mA
IOH = –75 mA
IOL = 50 µA
IOL = 12 mA3 V0.360.50.44
IOL = 24 mA4.5 V0.360.50.44
IOL = 50 mA
IOL = 75 mA
†
†
†
†
3 V2.92.92.9
4.5 V4.44.44.4
5.5 V3.85
5.5 V3.85
1.5 V0.10.10.1
3 V0.10.10.1
4.5 V0.10.10.1
5.5 V1.65
5.5 V1.65
TA = 25°C
MINMAXMINMAXMINMAX
–55°C to
125°C
101010pF
–40°C to
85°C
UNIT
V
V
switching characteristics over recommended operating free-air temperature range,
V
CD54AC32F3AACTIVECDIPJ141TBDA42 SNPBN / A for Pkg Type
CD74AC32EACTIVEPDIPN1425Pb-Free
CD74AC32EE4ACTIVEPDIPN1425Pb-Free
CD74AC32MACTIVESOICD1450Green (RoHS &
no Sb/Br)
CD74AC32M96ACTIVESOICD142500 Green (RoHS &
no Sb/Br)
CD74AC32M96E4ACTIVESOICD142500 Green (RoHS &
no Sb/Br)
CD74AC32M96G4ACTIVESOICD142500 Green (RoHS &
no Sb/Br)
CD74AC32ME4ACTIVESOICD1450Green (RoHS &
no Sb/Br)
CD74AC32MG4ACTIVESOICD1450Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(RoHS)
(RoHS)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAUN / A for Pkg Type
CU NIPDAUN / A for Pkg Type
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
(3)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.