Texas Instruments CD4541BPWR, CD4541BM96, CD4541BM, CD4541BF3A, CD4541BF Datasheet

CD4541B

/
j

/

/

[ /Title
(CD45
41B)

Sub-

ect
(CMO
S Pro­gram­mable
Timer
High
Volt­age
Types
(20V
Rat­ing))

Autho
r ()

Key­words
(Har­ris
Semi­con­ductor,
CD400
0,
metal
gate,
CMOS
, pdip,
cerdip,
mil,
mili­tary,
mil

Data sheet acquired from Harris Semiconductor
SCHS085

Features

• Low Symmetrical Output Resistance, Typically 100Ω

at V

= 15V

DD

• Built-In Low-Power RC Oscillator

• Oscillator Frequency Range. . . . . . . . . . DC to 100kHz

• External Clock (Applied to Pin 3) can be Used Instead
of Oscillator

N

• Operates as 2
Transition Timer

Q Select Provides Output Logic Level Flexibility

•Q/

• AUTO or MASTER RESET Disables Oscillator During
Reset to Reduce Power Dissipation

• Operates With Very Slow Clock Rise and Fall Times

• Capable of Driving Six Low Power TTL Loads, Three
Low-Power Schottky Loads, or Six HTL Loads Over
the Rated Temperature Range

• Symmetrical Output Characteristics

• 100% Tested for Quiescent Current at 20V

• 5V, 10V, and 15V Parametric Ratings

• Meets All Requirements of JEDEC Standard No. 13B,
“Standard Specifications for Description of ‘B’ Series
CMOS Devices”

Frequency Divider or as a Single-

Ordering Information

TEMP.

PART NUMBER

CD4541BF -55 to 125 14 Ld CERDIP F14.3
CD4541BE -55 to 125 14 Ld PDIP E14.3
CD4541BH -55 to 125 Chip ­CD4541BM -55 to 125 14 Ld SOIC M14.15

RANGE (oC) PACKAGE

Pinout

CD4541B (CERDIP, PDIP, SOIC)

R

TC

C

TC

R

NC

AUTO RESET

MASTER RESET

V

SS

PKG.

NO.

S

1
2
3
4
5
6
7

CMOS Programmable Timer

High Voltage Types (20V Rating)

Description

CD4541B programmable timer consists of a 16-stage binary
counter, an oscillator that is controlled by external R-C compo­nents (2 resistors and a capacitor), an automatic power-on
reset circuit, and output control logic. The counter increments
on positive-edge clock transitions and can also be reset via the
MASTER RESET input.

The output from this timer is the Q or
10th, 13th, or 16th counter stage. The desired stage is chosen
using time-select inputs A and B (see Frequency Select Table).
The output is available in either of two modes selectable via the
MODE input, pin 10 (see TruthTable). When this MODE input is
a logic “1”, the output will be a continuous square wave having
a frequency equal to the oscillator frequency divided by 2
With the MODE input set to logic “0” and after a MASTER
RESET is initiated, the output (assuming Q output has been
selected) changes from a low to a high state after 2
and remains in that state until another MASTER RESET pulse
is applied or the MODE input is set to a logic “1”.

Timing is initialized by setting the AUTO RESET input (pin 5) to
logic “0” and turning power on. If pin 5 is set to logic “1”, the
AUT ORESET circuit is disabled and counting will not start until
after a positive MASTER RESET pulse is applied and returns
to a low level. The AUTO RESET consumes an appreciable
amount of power and should not be used if low-power operation
is desired. For reliable automatic power-on reset, V
be greater than 5V.

The RC oscillator, shown in Figure 2, oscillates with a
frequency determined by the RC network and is calculated
using:

f =

TOP VIEW

1

---------------------------------- -

2.3 R

TCCTC

V

14

DD

B

13
12

A

11

NC

10

MODE

9

Q/

8

OUTPUT

Where f is between 1kHz
and 100kHz

and R

S

Q SELECT

10k≥Ωand 2RTC≈

Q output from the 8th,

N-1

DD

N

counts

should

.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

1

File Number 1378.1

Functional Diagram

R

TC

C

TC

R

AR

MR

MODE

Q/

SELECT

CD4541B

12

A

13

B

1
2
3

S

5
6

10

9

Q

8

V

DD

V

SS

Q

= PIN 14
= PIN 7

Functional Block Diagram

3

†R

S

2

†C

TC

1

†R

TC

5

PWR ON

RESET

AUTO

RESET†

MANUAL RESET†

OSC

R

8-STAGE

COUNTER

R

6

N
P

N
P

V

= 14

DD

V

= 7 NC = 4, 11

SS

2102

8-STAGE

COUNTER

FIGURE 1.

12 13

†A †B

R

8

Q

1 OF 3

MUX

16

2
OR

13

8

2

R

10

†Q/Q SELECT

9

V

DD

†MODE

V

SS

† All inputs are protected by CMOS Protection Network.

FREQUENCY SELECTION TABLE

NO. OF

AB

STAGES N COUNT 2

N

0 0 13 8192
0 1 10 1024
108256
1 1 16 65536

TRUTH TABLE

STATE

PIN

01

5 Auto Reset On Auto Reset Disable
6 Master Reset Off Master Reset On
9 Output Initially Low After

Reset (Q)

Output Initially High After

Q)

Reset (

10 Single Transition Mode Recycle Mode

3

R

S

C

TC

R

TC

2

1

INTERNAL

RESET

TO CLOCK
CKT

FIGURE 2. RC OSCILLATOR CIRCUIT

2

CD4541B

Absolute Maximum Ratings Thermal Information

DC Supply - Voltage Range, V

Voltages Referenced to VSSTerminal . . . . . . . . . . -0.5V to +20V

Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD+0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . ±10mA

Device Dissipation Per Output Transistor

For TA = Full Package Temperature Range

(All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW

DD

Operating Conditions

Temperature Range TA. . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range

For TA = Full Package Temperature Range . . . . .3V (Min), 18V (Typ)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

CONDITIONS LIMITS AT INDICATED TEMPERATURES (oC)

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . 90 N/A

CERDIP Package . . . . . . . . . . . . . . . . 90 36

SOIC Package. . . . . . . . . . . . . . . . . . . 120 N/A

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range (T
Maximum Lead Temperature (Soldering 10s)

At Distance 1/16in ± 1/32in (1.59mm ±0.79mm)

from case for 10s Maximum . . . . . . . . . . . . . . . . . . . . . . . . 265oC

(SOIC - Lead Tips Only)

) . . . -65oC to 150oC

STG

PARAMETER

Quiescent Device
Current,
(Note 2) IDD (Max)

Output Low (Sink)
Current lOL(Min)

Output High (Source)
Current, IOH (Min)

Output Voltage:
Low-Level, VOL (Max)

V

O

(V)

- 0, 5 5 5 5 150 150 - 0.04 5 µA

- 0, 10 10 10 10 300 300 - 0.04 10 µA

- 0, 15 15 20 20 600 600 - 0.04 20 µA

- 0, 20 20 100 100 3000 3000 - 0.08 100 µA

0.4 0, 5 5 1.9 1.85 1.26 1.08 1.55 3.1 - µA

0.5 0, 10 10 5 4.8 3.3 2.8 4 8 - µA

1.5 0, 15 15 12.6 12 8.4 7.2 10 20 - µA

4.6 0, 5 5 -1.9 -1.85 -1.26 -1.08 -1.55 -3.1 - mA

2.5 0, 5 5 -6.2 -6 -4.1 -3 -5 -10 - mA

9.5 0, 10 10 -5 -4.8 -3.3 -2.8 -4 -8 - mA

13.5 0, 15 15 -12.6 -12 -8.4 -7.2 -10 -20 - mA

- 0, 5 5 - 0.05 - 0 0.05 mA

- 0, 10 10 - 0.05 - 0 0.05 mA

- 0, 15 15 - 0.05 - 0 0.05 mA

V

(V)

V

IN

DD

(V) -55 -40 85 125

MIN TYP MAX

25

UNITS

Output Voltage:
High-Level, VOH (Min)

Input Low Voltage,
VIL (Max)

- 0, 5 5 - 4.95 4.95 5 - mA

- 0, 10 10 - 9.95 9.95 10 - mA

- 0, 15 15 - 14.95 14.95 15 - mA

0.5, 4.5 - 5 - 1.5 - - 1.5 V
1, 9 - 10 - 3 - - 3 V

1.5, 13.5 - 15 - 4 - - 4 V

3